From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web11.1181.1589352554592985458 for ; Tue, 12 May 2020 23:49:15 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ray.ni@intel.com) IronPort-SDR: fHIES66TsYFTDNIpIKEH1KlV/3KNE+sCj5kmMZgK+vnvwj/A07PsdA56FQDk3tTHKASJoWIiOZ lW1oyQ2MPijQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2020 23:49:14 -0700 IronPort-SDR: D4yrMCrmmwoCxiwxJepYIwQ/056z47Z20SqdunGMmC6OfPi2vozZiXcvJPcJ09B5S8cMCF5PJS y4JJmdcvWa/g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,386,1583222400"; d="scan'208";a="437388265" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga005.jf.intel.com with ESMTP; 12 May 2020 23:49:14 -0700 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:49:13 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:49:13 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.210]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.91]) with mapi id 14.03.0439.000; Wed, 13 May 2020 14:49:09 +0800 From: "Ni, Ray" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBusDxe: Enable MaxReadRequestSize feature Thread-Topic: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBusDxe: Enable MaxReadRequestSize feature Thread-Index: AQHWJuYUJe62JSGvi0ytnelqFKTApKig+CSAgASfEjA= Date: Wed, 13 May 2020 06:49:09 +0000 Deferred-Delivery: Wed, 13 May 2020 06:49:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C53AE3F@SHSMSX104.ccr.corp.intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> <20200510161412.13832-9-ashraf.javeed@intel.com> In-Reply-To: <20200510161412.13832-9-ashraf.javeed@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Javeed, Ashraf > Sent: Monday, May 11, 2020 12:14 AM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Wang, Jian J ; Wu,= Hao A > Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBu= sDxe: Enable MaxReadRequestSize > feature >=20 > REF: > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 >=20 > Add the Program phase feature init routine for MaxReadRequestSize > PCIe feature. >=20 > Signed-off-by: Ashraf Javeed > Signed-off-by: Ray Ni > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > Cc: Ashraf Javeed > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++ > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 50 +++++++++++++++= +++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 6 ++++++ > 3 files changed, 59 insertions(+) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > index 634e26b..e1f739e 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > @@ -54,6 +54,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] =3D { > // > { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxPayloadSize), > TRUE, { TRUE, TRUE }, { MaxPayloadSizeScan, MaxPaylo= adSizeProgram } }, > + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, MaxReadRequestSize), > + TRUE, { TRUE, TRUE }, { NULL, MaxReadR= equestSizeProgram } }, > }; >=20 > /** > @@ -227,6 +229,7 @@ PcieNotifyDeviceState ( > CopyMem (&PcieDeviceState, &PciIoDevice->DeviceState, sizeof (PciIoDev= ice->DeviceState)); >=20 > PcieDeviceState.MaxPayloadSize =3D (UINT8)PciIoDevice->PciExpress= Capability.DeviceControl.Bits.MaxPayloadSize; > + PcieDeviceState.MaxReadRequestSize =3D (UINT8)PciIoDevice- > >PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize; > return mPciePlatformProtocol->NotifyDeviceState ( > mPciePlatformProtocol, > PciIoDevice->Handle, > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg= /Bus/Pci/PciBusDxe/PcieFeatures.c > index d1a78f7..a7591e6 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c > @@ -117,3 +117,53 @@ MaxPayloadSizeProgram ( > return EFI_SUCCESS; > } >=20 > +/** > + Program the PCIe Device Control register Max. Read Request Size field = per platform policy. > + > + @param PciDevice A pointer to the PCI_IO_DEVICE instance. > + @param Level The level of the PCI device in the heira= rchy. > + Level of root ports is 0. > + @param Context Pointer to feature specific context. > + > + @retval EFI_SUCCESS The data was read from or written to the= PCI device. > + @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not > + valid for the PCI configuration header o= f the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > +**/ > +EFI_STATUS > +MaxReadRequestSizeProgram ( > + IN PCI_IO_DEVICE *PciDevice, > + IN UINTN Level, > + IN VOID **Context > + ) > +{ > + ASSERT (*Context =3D=3D NULL); > + > + if (PciDevice->DeviceState.MaxReadRequestSize =3D=3D EFI_PCI_EXPRESS_D= EVICE_POLICY_NOT_APPLICABLE) { > + return EFI_SUCCESS; > + } > + if (PciDevice->DeviceState.MaxReadRequestSize =3D=3D EFI_PCI_EXPRESS_D= EVICE_POLICY_AUTO) { > + PciDevice->DeviceState.MaxReadRequestSize =3D (UINT8) PciDevice- > >PciExpressCapability.DeviceControl.Bits.MaxPayloadSize; > + } > + > + if (PciDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestS= ize !=3D PciDevice- > >DeviceState.MaxReadRequestSize) { > + DEBUG (( > + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x\n", > + __FUNCTION__, PciDevice->BusNumber, PciDevice->DeviceNumber, PciDe= vice->FunctionNumber, > + PciDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestS= ize, > + PciDevice->DeviceState.MaxReadRequestSize > + )); > + PciDevice->PciExpressCapability.DeviceControl.Bits.MaxReadRequestSiz= e =3D PciDevice->DeviceState.MaxReadRequestSize; > + > + return PciDevice->PciIo.Pci.Write ( > + &PciDevice->PciIo, > + EfiPciIoWidthUint16, > + PciDevice->PciExpressCapabilityOffset > + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, De= viceControl), > + 1, > + &PciDevice->PciExpressCapability.Devic= eControl.Uint16 > + ); > + } > + return EFI_SUCCESS; > +} > + > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg= /Bus/Pci/PciBusDxe/PcieFeatures.h > index 7b820e8..40e28b8 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h > @@ -24,5 +24,11 @@ MaxPayloadSizeProgram ( > IN VOID **Context > ); >=20 > +EFI_STATUS > +MaxReadRequestSizeProgram ( > + IN PCI_IO_DEVICE *PciDevice, > + IN UINTN Level, > + IN VOID **Context > + ); >=20 > #endif > -- > 2.21.0.windows.1