From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.1182.1589352555434537524 for ; Tue, 12 May 2020 23:49:15 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ray.ni@intel.com) IronPort-SDR: J7h/290btRcoX89hv1j3pa+kZM8GKZ36gFgqPI2Js09QfWa9SvDdM/mWsXOriPMiBVsWsK2v9H KUnalYdiKiCg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2020 23:49:14 -0700 IronPort-SDR: m8e2zVJA221Ueeyg5D8qnGpDf2LFViwcue01Wn4ZTVmk1uT0t3xGqn8V4zCrahwSOdrQYWx4AP mUfpzP0h4wWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,386,1583222400"; d="scan'208";a="262381725" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 12 May 2020 23:49:13 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:49:13 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:49:12 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.210]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.26]) with mapi id 14.03.0439.000; Wed, 13 May 2020 14:49:10 +0800 From: "Ni, Ray" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBusDxe: Enable CompletionTimeout feature Thread-Topic: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBusDxe: Enable CompletionTimeout feature Thread-Index: AQHWJuYUJe62JSGvi0ytnelqFKTApKig+CgAgASfG5A= Date: Wed, 13 May 2020 06:49:09 +0000 Deferred-Delivery: Wed, 13 May 2020 06:49:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C53AE4E@SHSMSX104.ccr.corp.intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> <20200510161412.13832-12-ashraf.javeed@intel.com> In-Reply-To: <20200510161412.13832-12-ashraf.javeed@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Javeed, Ashraf > Sent: Monday, May 11, 2020 12:14 AM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Wang, Jian J ; Wu,= Hao A > Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBu= sDxe: Enable CompletionTimeout feature >=20 > REF: > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 >=20 > Add the Program phase feature init routine for CompletionTimeout > PCIe feature. >=20 > Signed-off-by: Ashraf Javeed > Signed-off-by: Ray Ni > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > Cc: Ashraf Javeed > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++ > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 91 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 15 +++++++++++++++ > 3 files changed, 109 insertions(+) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > index 6bf06b0..e6d3363 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > @@ -60,6 +60,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] =3D { > TRUE, { TRUE, TRUE }, { NULL, RelaxedO= rderingProgram } }, > { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, NoSnoop), > TRUE, { TRUE, TRUE }, { NULL, NoSnoopP= rogram } }, > + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, CompletionTimeout), > + TRUE, { TRUE, TRUE }, { NULL, Completi= onTimeoutProgram}}, > }; >=20 > /** > @@ -236,6 +238,7 @@ PcieNotifyDeviceState ( > PcieDeviceState.MaxReadRequestSize =3D (UINT8)PciIoDevice- > >PciExpressCapability.DeviceControl.Bits.MaxReadRequestSize; > PcieDeviceState.RelaxedOrdering =3D (UINT8)PciIoDevice->PciExpress= Capability.DeviceControl.Bits.RelaxedOrdering; > PcieDeviceState.NoSnoop =3D (UINT8)PciIoDevice->PciExpress= Capability.DeviceControl.Bits.NoSnoop; > + PcieDeviceState.CompletionTimeout =3D (UINT8)PciIoDevice->PciExpress= Capability.DeviceControl2.Uint16 & 0x1F; >=20 > return mPciePlatformProtocol->NotifyDeviceState ( > mPciePlatformProtocol, > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePkg= /Bus/Pci/PciBusDxe/PcieFeatures.c > index 6c22feb..ca4052f 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c > @@ -267,3 +267,94 @@ NoSnoopProgram ( > return EFI_SUCCESS; > } >=20 > +/** > + Program PCIe feature Completion Timeout per the device-specific platfo= rm policy. > + > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. > + @param Level The level of the PCI device in the heira= rchy. > + Level of root ports is 0. > + @param Context Pointer to feature specific context. > + > + @retval EFI_SUCCESS The feature is initialized successfully. > + @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not > + valid for the PCI configuration header o= f the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > +**/ > +EFI_STATUS > +CompletionTimeoutProgram ( > + IN PCI_IO_DEVICE *PciIoDevice, > + IN UINTN Level, > + IN VOID **Context > + ) > +{ > + PCI_REG_PCIE_DEVICE_CONTROL2 DevicePolicy; > + UINTN RangeIndex; > + UINT8 SubRanges; > + > + if (PciIoDevice->DeviceState.CompletionTimeout =3D=3D EFI_PCI_EXPRESS_= DEVICE_POLICY_NOT_APPLICABLE || > + PciIoDevice->DeviceState.CompletionTimeout =3D=3D EFI_PCI_EXPRESS_= DEVICE_POLICY_AUTO) { > + return EFI_SUCCESS; > + } > + > + // > + // Interpret the policy value as BIT[0:4] in Device Control 2 Register > + // > + DevicePolicy.Uint16 =3D (UINT16) PciIoDevice->DeviceState.CompletionTi= meout; > + > + // > + // Ignore when device doesn't support to disable Completion Timeout wh= ile the policy requests. > + // > + if (PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.Completio= nTimeoutDisable =3D=3D 0 && > + DevicePolicy.Bits.CompletionTimeoutDisable =3D=3D 1) { > + return EFI_INVALID_PARAMETER; > + } > + > + if (DevicePolicy.Bits.CompletionTimeoutValue !=3D 0) { > + // > + // Ignore when the policy requests to use a range that's not support= ed by the device. > + // RangeIndex is 0 ~ 3 for Range A ~ D. > + // > + RangeIndex =3D DevicePolicy.Bits.CompletionTimeoutValue >> 2; > + if ((PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.Comple= tionTimeoutRanges & (1 < RangeIndex)) =3D=3D 0) { > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // Ignore when the policy doesn't request one and only one sub-range= for a certain range. > + // > + SubRanges =3D (UINT8) (DevicePolicy.Bits.CompletionTimeoutValue & (B= IT0 | BIT1)); > + if (SubRanges !=3D BIT0 && SubRanges !=3D BIT1) { > + return EFI_INVALID_PARAMETER; > + } > + } > + > + if ((PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionT= imeoutDisable > + !=3D DevicePolicy.Bits.CompletionTimeoutDisable) || > + (PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionT= imeoutValue > + !=3D DevicePolicy.Bits.CompletionTimeoutValue)) { > + DEBUG (( > + DEBUG_INFO, " %a [%02d|%02d|%02d]: Disable =3D %x -> %x, Timeout = =3D %x -> %x.\n", > + __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, P= ciIoDevice->FunctionNumber, > + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTi= meoutDisable, > + DevicePolicy.Bits.CompletionTimeoutDisable, > + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTi= meoutValue, > + DevicePolicy.Bits.CompletionTimeoutValue > + )); > + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTime= outDisable > + =3D DevicePolicy.Bits.CompletionTimeoutDisable; > + PciIoDevice->PciExpressCapability.DeviceControl2.Bits.CompletionTime= outValue > + =3D DevicePolicy.Bits.CompletionTimeoutValue; > + > + return PciIoDevice->PciIo.Pci.Write ( > + &PciIoDevice->PciIo, > + EfiPciIoWidthUint16, > + PciIoDevice->PciExpressCapabilityOffse= t > + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, De= viceControl2), > + 1, > + &PciIoDevice->PciExpressCapability.Dev= iceControl2.Uint16 > + ); > + } > + > + return EFI_SUCCESS; > +} > + > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePkg= /Bus/Pci/PciBusDxe/PcieFeatures.h > index 60b8742..bdb7004 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h > @@ -45,4 +45,19 @@ NoSnoopProgram ( > IN VOID **Context > ); >=20 > +/** > + Program PCIE feature Completion Timeout per the device-specific platfo= rm policy. > + > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. > + > + @retval EFI_SUCCESS The feature is initialized successfully. > + @retval EFI_INVALID_PARAMETER The policy is not supported by the devic= e. > +**/ > +EFI_STATUS > +CompletionTimeoutProgram ( > + IN PCI_IO_DEVICE *PciIoDevice, > + IN UINTN Level, > + IN VOID **Context > + ); > + > #endif > -- > 2.21.0.windows.1