From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.1197.1589352673807540140 for ; Tue, 12 May 2020 23:51:13 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ray.ni@intel.com) IronPort-SDR: SJb/RMlu+a+NMHPNCY1VteRsvfTfppLiR1A9IT1st0+Gs41jyhaPewE78R8kAkuKaOvzk6XPaF P+Ww9xwU8ERA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2020 23:51:13 -0700 IronPort-SDR: txcRGmAYpR9mn/yGuFEjd02bd0G7QJsyo0gLovZW1Tn83uRLBKQ3fQKX0NkDXKoT1avUhPzzEZ /ZylhvevE3mA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,386,1583222400"; d="scan'208";a="262382328" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 12 May 2020 23:51:13 -0700 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:51:12 -0700 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by FMSMSX153.amr.corp.intel.com (10.18.125.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:51:12 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.210]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.92]) with mapi id 14.03.0439.000; Wed, 13 May 2020 14:51:09 +0800 From: "Ni, Ray" To: "devel@edk2.groups.io" , "Javeed, Ashraf" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeModulePkg/PciBusDxe: Enable AtomicOp feature Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeModulePkg/PciBusDxe: Enable AtomicOp feature Thread-Index: AQHWJuYUJe62JSGvi0ytnelqFKTApKig+CoAgASfjoA= Date: Wed, 13 May 2020 06:51:09 +0000 Deferred-Delivery: Wed, 13 May 2020 06:51:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C53AEA9@SHSMSX104.ccr.corp.intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> <20200510161412.13832-14-ashraf.javeed@intel.com> In-Reply-To: <20200510161412.13832-14-ashraf.javeed@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Javeed, A= shraf > Sent: Monday, May 11, 2020 12:14 AM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Wang, Jian J ; Wu= , Hao A > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeM= odulePkg/PciBusDxe: Enable AtomicOp > feature >=20 > REF: > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 >=20 > Add the Program phase feature init routine for AtomicOp > PCIe feature. >=20 > Signed-off-by: Ashraf Javeed > Signed-off-by: Ray Ni > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > Cc: Ashraf Javeed > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c | 3 +++ > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c | 62 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h | 16 ++++++++++++++= ++ > 3 files changed, 81 insertions(+) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > index 35aaffa..401521b 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatureSupport.c > @@ -64,6 +64,8 @@ PCIE_FEATURE_ENTRY mPcieFeatures[] =3D { > TRUE, { TRUE, TRUE }, { NULL, Complet= ionTimeoutProgram}}, > { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, Ltr), > TRUE, { FALSE, TRUE }, { LtrScan, LtrProg= ram}}, > + { OFFSET_OF (EFI_PCI_EXPRESS_PLATFORM_POLICY, AtomicOp), > + TRUE, { TRUE, TRUE }, { NULL, AtomicO= pProgram}}, > }; >=20 > /** > @@ -241,6 +243,7 @@ PcieNotifyDeviceState ( > PcieDeviceState.RelaxedOrdering =3D (UINT8)PciIoDevice->PciExpres= sCapability.DeviceControl.Bits.RelaxedOrdering; > PcieDeviceState.NoSnoop =3D (UINT8)PciIoDevice->PciExpres= sCapability.DeviceControl.Bits.NoSnoop; > PcieDeviceState.CompletionTimeout =3D (UINT8)PciIoDevice->PciExpres= sCapability.DeviceControl2.Uint16 & 0x1F; > + PcieDeviceState.AtomicOp =3D (UINT8)PciIoDevice->PciExpres= sCapability.DeviceControl2.Bits.AtomicOpRequester; > PcieDeviceState.Ltr =3D (UINT8)PciIoDevice->PciExpres= sCapability.DeviceControl2.Bits.LtrMechanism; >=20 > return mPciePlatformProtocol->NotifyDeviceState ( > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c b/MdeModulePk= g/Bus/Pci/PciBusDxe/PcieFeatures.c > index 8c7fae0..407c94a 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.c > @@ -552,3 +552,65 @@ LtrProgram ( > return EFI_SUCCESS; > } >=20 > +/** > + Program AtomicOp. > + > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. > + @param Level The level of the PCI device in the heir= archy. > + Level of root ports is 0. > + @param Context Pointer to feature specific context. > + > + @retval EFI_SUCCESS setup of PCI feature AtomicOp is succes= sful. > + @retval EFI_UNSUPPORTED The address range specified by Offset, = Width, and Count is not > + valid for the PCI configuration header = of the PCI controller. > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. > +**/ > +EFI_STATUS > +AtomicOpProgram ( > + IN PCI_IO_DEVICE *PciIoDevice, > + IN UINTN Level, > + IN VOID **Context > + ) > +{ > + if (PciIoDevice->DeviceState.AtomicOp =3D=3D EFI_PCI_EXPRESS_DEVICE_P= OLICY_AUTO || > + PciIoDevice->DeviceState.AtomicOp =3D=3D EFI_PCI_EXPRESS_DEVICE_P= OLICY_NOT_APPLICABLE) { > + return EFI_SUCCESS; > + } > + > + // > + // BIT0 of the policy value is for AtomicOp Requester Enable (BIT6) > + // BIT1 of the policy value is for AtomicOp Egress Blocking (BIT7) > + // > + if ((PciIoDevice->DeviceState.AtomicOp >> 2) !=3D 0) { > + return EFI_INVALID_PARAMETER; > + } > + > + if (!PciIoDevice->PciExpressCapability.DeviceCapability2.Bits.AtomicO= pRouting) { > + PciIoDevice->DeviceState.AtomicOp &=3D ~BIT1; > + } > + if (PciIoDevice->DeviceState.AtomicOp !=3D > + BitFieldRead16 (PciIoDevice->PciExpressCapability.DeviceControl2.= Uint16, 6, 7)) { > + > + DEBUG (( > + DEBUG_INFO, " %a [%02d|%02d|%02d]: %x -> %x.\n", > + __FUNCTION__, PciIoDevice->BusNumber, PciIoDevice->DeviceNumber= , PciIoDevice->FunctionNumber, > + BitFieldRead16 (PciIoDevice->PciExpressCapability.DeviceControl= 2.Uint16, 6, 7), > + PciIoDevice->DeviceState.AtomicOp > + )); > + BitFieldWrite16 ( > + PciIoDevice->PciExpressCapability.DeviceControl2.Uint16, 6, 7, > + PciIoDevice->DeviceState.AtomicOp > + ); > + return PciIoDevice->PciIo.Pci.Write ( > + &PciIoDevice->PciIo, > + EfiPciIoWidthUint16, > + PciIoDevice->PciExpressCapabilityOf= fset > + + OFFSET_OF (PCI_CAPABILITY_PCIEXP,= DeviceControl2), > + 1, > + &PciIoDevice->PciExpressCapability.= DeviceControl2.Uint16 > + ); > + } > + > + return EFI_SUCCESS; > +} > + > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h b/MdeModulePk= g/Bus/Pci/PciBusDxe/PcieFeatures.h > index a9dacf3..5c70e41 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PcieFeatures.h > @@ -94,4 +94,20 @@ LtrProgram ( > IN VOID **Context > ); >=20 > +/** > + Program AtomicOp. > + > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. > + @param Level The level of the PCI device in the heirarchy. > + Level of root ports is 0. > + @param Context Pointer to feature specific context. > + > + @retval EFI_SUCCESS setup of PCI feature LTR is successful. > +**/ > +EFI_STATUS > +AtomicOpProgram ( > + IN PCI_IO_DEVICE *PciIoDevice, > + IN UINTN Level, > + IN VOID **Context > + ); > #endif > -- > 2.21.0.windows.1 >=20 >=20 >=20