From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web12.2665.1591067343788221642 for ; Mon, 01 Jun 2020 20:09:04 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: ray.ni@intel.com) IronPort-SDR: SNZBSXpTEUVaZFw8qBD/fKU+G6rbaZCqE+T30TyGK0FCHCoo9xYW8VXUrH4vNbvT1y/AuDVp8V aNvcoBDrjdXg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2020 20:09:02 -0700 IronPort-SDR: +uOMPvi20vZSqm4JR+trkmgHCbHeCQJSM1GNzlM+d2PW7EDYiQXslan1ccDw7CmZmnGk/dMTrW b2FbSLrxJvjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,462,1583222400"; d="scan'208";a="312135605" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by FMSMGA003.fm.intel.com with ESMTP; 01 Jun 2020 20:09:02 -0700 Received: from fmsmsx151.amr.corp.intel.com (10.18.125.4) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 1 Jun 2020 20:09:02 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 1 Jun 2020 20:09:02 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.161]) by shsmsx102.ccr.corp.intel.com ([169.254.2.36]) with mapi id 14.03.0439.000; Tue, 2 Jun 2020 11:08:59 +0800 From: "Ni, Ray" To: "Wang, Iwen Evelyn" , "devel@edk2.groups.io" CC: "Huang, Jenny" , "Shih, More" , "Chaganty, Rangasai V" , "Yao, Jiewen" , "Sheng, W" Subject: Re: [PATCH] IntelSiliconPkg-Vtd: Set all IOMMU PMR to same range Thread-Topic: [PATCH] IntelSiliconPkg-Vtd: Set all IOMMU PMR to same range Thread-Index: AQHWOG9OYeqaGpC4CU2dc7ieRG3kzqjEpUsg Date: Tue, 2 Jun 2020 03:08:58 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C596125@SHSMSX104.ccr.corp.intel.com> References: <20200601234925.11108-1-iwen.evelyn.wang@intel.com> In-Reply-To: <20200601234925.11108-1-iwen.evelyn.wang@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Evelyn, Can you include more info in the commit message? such was reason and result= of this change. > -----Original Message----- > From: Wang, Iwen Evelyn > Sent: Tuesday, June 2, 2020 7:49 AM > To: devel@edk2.groups.io > Cc: Huang, Jenny ; Shih, More ; Ni, Ray ; Chaganty, > Rangasai V ; Yao, Jiewen ; Sheng, W > Subject: [PATCH] IntelSiliconPkg-Vtd: Set all IOMMU PMR to same range >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2775 >=20 > Signed-off-by: Evelyn Wang > Cc: Jenny Huang > Cc: More Shih > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Jiewen Yao > Cc: W Sheng > --- > .../Feature/VTd/IntelVTdPmrPei/DmarTable.c | 38 +++++++++++++++-= ------ > 1 file changed, 26 insertions(+), 12 deletions(-) >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Dma= rTable.c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c > index d920d136f1..fd64051032 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.= c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.= c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -13,7 +13,7 @@ > #include > #include > #include > - > +#include > #include "IntelVTdPmrPei.h" >=20 > /** > @@ -502,19 +502,17 @@ ProcessRmrr ( > UINT64 RmrrMask; > UINTN LowBottom; > UINTN LowTop; > - UINTN HighBottom; > + UINT64 HighBottom; > UINT64 HighTop; > EFI_ACPI_DMAR_HEADER *AcpiDmarTable; > + VTD_PMR_INFO_HOB *VtdPmrHob; > + VOID *VtdPmrHobPtr; >=20 > + VtdPmrHobPtr =3D GetFirstGuidHob (&gVtdPmrInfoDataHobGuid); > AcpiDmarTable =3D VTdInfo->AcpiDmarTable; >=20 > DEBUG ((DEBUG_INFO," RMRR (Base 0x%016lx, Limit 0x%016lx)\n", DmarRmr= r->ReservedMemoryRegionBaseAddress, > DmarRmrr->ReservedMemoryRegionLimitAddress)); >=20 > - if ((DmarRmrr->ReservedMemoryRegionBaseAddress =3D=3D 0) || > - (DmarRmrr->ReservedMemoryRegionLimitAddress =3D=3D 0)) { > - return ; > - } > - > DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)(= (UINTN)(DmarRmrr + 1)); > while ((UINTN)DmarDevScopeEntry < (UINTN)DmarRmrr + DmarRmrr->Header.L= ength) { > ASSERT (DmarDevScopeEntry->Type =3D=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_T= YPE_PCI_ENDPOINT); > @@ -523,10 +521,26 @@ ProcessRmrr ( > if (VTdIndex !=3D (UINTN)-1) { > RmrrMask =3D LShiftU64 (1, VTdIndex); >=20 > - LowBottom =3D 0; > - LowTop =3D (UINTN)DmarRmrr->ReservedMemoryRegionBaseAddress; > - HighBottom =3D (UINTN)DmarRmrr->ReservedMemoryRegionLimitAddress += 1; > - HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); > + if (VtdPmrHobPtr =3D=3D NULL) { > + LowBottom =3D 0; > + LowTop =3D (UINTN)DmarRmrr->ReservedMemoryRegionBaseAddress; > + HighBottom =3D DmarRmrr->ReservedMemoryRegionLimitAddress + 1; > + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); > + } else { > + /** > + When gVtdPmrInfoDataHobGuid exists, it means: > + 1. Dma buffer is reserved by memory initialize code > + 2. PeiGetVtdPmrAlignmentLib is used to get alignment > + 3. PMR ranges are determined by the system memory map > + 4. PMR ranges will be conveyed through VTD_PMR_INFO_HOB > + 5. All IOMMU PMR should have the same ranges > + **/ > + VtdPmrHob =3D GET_GUID_HOB_DATA (VtdPmrHobPtr); > + LowBottom =3D VtdPmrHob->ProtectedLowBase; > + LowTop =3D VtdPmrHob->ProtectedLowLimit; > + HighBottom =3D VtdPmrHob->ProtectedHighBase; > + HighTop =3D VtdPmrHob->ProtectedHighLimit; > + } >=20 > SetDmaProtectedRange ( > VTdInfo, > -- > 2.16.2.windows.1