From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web12.1576.1592374175942309079 for ; Tue, 16 Jun 2020 23:09:36 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ray.ni@intel.com) IronPort-SDR: wc82EaFEivBzLF+lzatFdJfMrWx1NwZOmm5jhTiT/L92nFunLKM/LrLLUYcHa3BLkyrMpT2zxV gk13NzduBK/A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2020 23:09:35 -0700 IronPort-SDR: /0gEl7Gx3ZKdJYZ6E/l67HzDB3HoLAKu/AjPFby8KzD5Ipm8UoPNU9W6f8DyDmmFYRbRjxelgw Jvk37Sg3QHAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,521,1583222400"; d="scan'208";a="277171990" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga006.jf.intel.com with ESMTP; 16 Jun 2020 23:09:34 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 16 Jun 2020 23:09:33 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 16 Jun 2020 23:09:33 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.161]) by shsmsx102.ccr.corp.intel.com ([169.254.2.36]) with mapi id 14.03.0439.000; Wed, 17 Jun 2020 14:09:30 +0800 From: "Ni, Ray" To: "Ma, Maurice" , "devel@edk2.groups.io" CC: "Dong, Guo" , "You, Benjamin" Subject: Re: [PATCH V2 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoardInfo HOB Thread-Topic: [PATCH V2 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr stored in AcpiBoardInfo HOB Thread-Index: AQHWOiAupwK/k0N9iUiAeKQKdHvA6qjIi+VwgBPZUGA= Date: Wed, 17 Jun 2020 06:09:30 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C5BCD14@SHSMSX104.ccr.corp.intel.com> References: <20200604032710.970-1-ray.ni@intel.com> <20200604032710.970-3-ray.ni@intel.com> In-Reply-To: Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Maurice, > -----Original Message----- > From: Ma, Maurice > Sent: Monday, June 8, 2020 11:05 PM > To: Ni, Ray ; devel@edk2.groups.io > Cc: Dong, Guo ; You, Benjamin > Subject: RE: [PATCH V2 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr st= ored in AcpiBoardInfo HOB >=20 > Hi, Ray, >=20 > I noticed in this V2 patch, you removed the following line from the DSC f= ile. > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE) > It will make the PcdPciExpressBaseAddress become PcdsFixedAtBuild type in= stead of > PcdsDynamicDefault. Is this your intention ? Yes. I want all modules in the payload access the PCI configure space in tw= o ways: 1. Through PciRootBridgeIo/PciIo, this calling stack depends on the AcpiBo= ardInfo HOB because PciSegmentLibSegmentInfo is used. 2. Through PciCf8Lib. In both ways the PCIE base address are configurable. But if the concern is about performance impact of using CF8/CFC, I can keep= the PciExpressLib access path. >=20 > Also this V2 patch forced PcdLib class instance to be BasePciLibCf8. It = means all PCI configuration space access will use I/O > port access. We prefer using BasePciSegmentLibPci. I think we should k= eep the original code for this so that it is > configurable. >=20 > Also can we sync up DSC changes into UefiPayloadPkgIa32.dsc as well ? Sure. I will apply the similar change to Ia32.dsc after I understand how to= change the X64.dsc. >=20 > Thanks > Maurice > > -----Original Message----- > > From: Ni, Ray > > Sent: Wednesday, June 3, 2020 20:27 > > To: devel@edk2.groups.io > > Cc: Ma, Maurice ; Dong, Guo ; > > You, Benjamin > > Subject: [PATCH V2 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr stor= ed in > > AcpiBoardInfo HOB > > > > Today's UefiPayloadPkg always uses 0xE0000000 as the PCIE base address = and > > ignores the value set in AcpiBoardInfo HOB created by the boot loader. = This > > makes the payload binary cannot work in environment where the PCIE base > > address set by boot loader doesn't equal to 0xE0000000. > > > > The patch enhances UefiPayloadPkg so that the PCIE base address set by = boot > > loader in the AcpiBoardInfo HOB is used. > > > > Signed-off-by: Ray Ni > > Cc: Maurice Ma > > Cc: Guo Dong > > Cc: Benjamin You > > --- > > .../PciSegmentInfoLibAcpiBoardInfo.c | 59 +++++++++++++++++++ > > .../PciSegmentInfoLibAcpiBoardInfo.inf | 36 +++++++++++ > > UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 16 +---- > > 3 files changed, 98 insertions(+), 13 deletions(-) create mode 100644 > > UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLib= Ac > > piBoardInfo.c > > create mode 100644 > > UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLib= Ac > > piBoardInfo.inf > > > > diff --git > > a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoL= ib > > AcpiBoardInfo.c > > b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoL= ib > > AcpiBoardInfo.c > > new file mode 100644 > > index 0000000000..d37c91cc9f > > --- /dev/null > > +++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentI= n > > +++ foLibAcpiBoardInfo.c > > @@ -0,0 +1,59 @@ > > +/** @file+ PCI Segment Information Library that returns one segment > > whose+ segment base address is retrieved from AcpiBoardInfo HOB.++ > > Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-= License- > > Identifier: BSD-2-Clause-Patent++**/++#include +#include > > ++#include +#include > > +#include ++STATIC > > PCI_SEGMENT_INFO mPciSegment0 =3D {+ 0, // Segment number+ 0, // To= be > > fixed later+ 0, // Start bus number+ 255 // End bus number+};++/**+ = Return > > an array of PCI_SEGMENT_INFO holding the segment information.++ Note: = The > > returned array/buffer is owned by callee.++ @param Count Return the = count > > of segments.++ @retval A callee owned array holding the segment > > information.+**/+PCI_SEGMENT_INFO *+EFIAPI+GetPciSegmentInfo (+ UINTN > > *Count+ )+{+ EFI_HOB_GUID_TYPE *GuidHob;+ ACPI_BOARD_INFO > > *AcpiBoardInfo;++ ASSERT (Count !=3D NULL);+ if (Count =3D=3D NULL) {= + return > > NULL;+ }++ if (mPciSegment0.BaseAddress =3D=3D 0) {+ //+ // Fin= d the acpi > > board information guid hob+ //+ GuidHob =3D GetFirstGuidHob > > (&gUefiAcpiBoardInfoGuid);+ ASSERT (GuidHob !=3D NULL);++ AcpiBoa= rdInfo =3D > > (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (GuidHob);+ > > mPciSegment0.BaseAddress =3D AcpiBoardInfo->PcieBaseAddress;+ }+ *Cou= nt =3D > > 1;+ return &mPciSegment0;+}diff --git > > a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoL= ib > > AcpiBoardInfo.inf > > b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoL= ib > > AcpiBoardInfo.inf > > new file mode 100644 > > index 0000000000..ec4dbaaa55 > > --- /dev/null > > +++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentI= n > > +++ foLibAcpiBoardInfo.inf > > @@ -0,0 +1,36 @@ > > +## @file+# PCI Segment Information Library that returns one segment > > whose+# segment base address is retrieved from AcpiBoardInfo HOB.+#+# > > Copyright (c) 2020, Intel Corporation. All rights reserved.
+#+# SP= DX- > > License-Identifier: BSD-2-Clause-Patent+#+#+##++[Defines]+ INF_VERSION > > =3D 0x00010005+ BASE_NAME =3D PciSegmentInfoLibAc= piBoardInfo+ > > FILE_GUID =3D 0EA82AA2-6C36-4FD5-BC90-FFA3ECB5E0CE= + > > MODULE_TYPE =3D BASE+ VERSION_STRING = =3D 1.0+ > > LIBRARY_CLASS =3D PciSegmentInfoLib | DXE_DRIVER++#+# = The > > following information is for reference only and not required by the bui= ld > > tools.+#+# VALID_ARCHITECTURES =3D IA32 X64 EBC+#++[Sources]= + > > PciSegmentInfoLibAcpiBoardInfo.c++[Packages]+ MdePkg/MdePkg.dec+ > > UefiPayloadPkg/UefiPayloadPkg.dec++[LibraryClasses]+ PcdLib+ HobLib+ > > DebugLibdiff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > index 0736cd9954..62d680eb79 100644 > > --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > > @@ -3,7 +3,7 @@ > > # # Provides drivers and definitions to create uefi payload for bootlo= aders. #-# > > Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+= # > > Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
= # SPDX- > > License-Identifier: BSD-2-Clause-Patent # ##@@ -38,11 +38,6 @@ [Defines= ] > > # DEFINE MAX_LOGICAL_PROCESSORS =3D 64 - #- # PCI options-= #- > > DEFINE PCIE_BASE =3D 0xE0000000- # # Serial port= set up #@@ - > > 122,14 +117,10 @@ [LibraryClasses] > > PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf > > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf-!if $(PC= IE_BASE) > > =3D=3D 0 PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > > PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf-!else- > > PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf- > > PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf-!e= ndif- > > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.= i > > nf+ > > PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLi > > bSegmentInfo.inf+ > > PciSegmentInfoLib|UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo= /Pc > > iSegmentInfoLibAcpiBoardInfo.inf > > PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePe= C > > offGetEntryPointLib.inf > > CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCache > > MaintenanceLib.inf@@ -288,7 +279,6 @@ [PcdsFixedAtBuild] > > gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE > > gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, > > 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66,= 0x23, > > 0x31 } - > > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE) !if > > $(SOURCE_DEBUG_ENABLE) > > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2-- > > 2.26.2.windows.1 >=20