From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9E3781A1E72 for ; Thu, 20 Oct 2016 23:12:57 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP; 20 Oct 2016 23:12:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,375,1473145200"; d="scan'208";a="21968094" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga006.fm.intel.com with ESMTP; 20 Oct 2016 23:12:57 -0700 Received: from fmsmsx152.amr.corp.intel.com (10.18.125.5) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 20 Oct 2016 23:12:56 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX152.amr.corp.intel.com (10.18.125.5) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 20 Oct 2016 23:12:56 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.206]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.96]) with mapi id 14.03.0248.002; Fri, 21 Oct 2016 14:12:53 +0800 From: "Yao, Jiewen" To: "Yarlagadda, Satya P" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] IntelFsp2Pkg: Added changes to enable FPDT performance measurements Thread-Index: AQHSK17t4Vp91kFZ+EiMQGgbuF9AcKCybYEA Date: Fri, 21 Oct 2016 06:12:52 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C50386B4FD5@shsmsx102.ccr.corp.intel.com> References: <20161021054924.32-1-satya.p.yarlagadda@intel.com> In-Reply-To: <20161021054924.32-1-satya.p.yarlagadda@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelFsp2Pkg: Added changes to enable FPDT performance measurements X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Oct 2016 06:12:57 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: jiewen.yao@intel.com > -----Original Message----- > From: Yarlagadda, Satya P > Sent: Friday, October 21, 2016 1:49 PM > To: edk2-devel@lists.01.org > Cc: Ma, Maurice ; Yao, Jiewen > ; Mudusuru, Giri P > Subject: [PATCH] IntelFsp2Pkg: Added changes to enable FPDT performance > measurements >=20 > IntelFsp2Pkg: > 1.Defined performance measure mask to mask the Perf id (Bits 63:56) of th= e > Perf Data from FSP Global data. > 2.Replaced the hard coded perf ids to use the standard defines > from FspStatuscode.h > 3.Add the PerfData form Fsp Global data ( for TempRaminit entry, > TempramInit exit, memoryinit entry) to FPDT entries >=20 > IntelFsp2WrapperPkg: > Moved the code to add the FSP FPDT records and wrapper FPDT records > from ReadytoBoot event to EndofFirmware event >=20 > Cc: Maurice Ma > Cc: Jiewen Yao > Cc: Giri P Mudusuru > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Satya Yarlagadda > --- > IntelFsp2Pkg/Include/FspGlobalData.h | 1 + > .../BaseFspPlatformLib/BaseFspPlatformLib.inf | 4 ++ > .../Library/BaseFspPlatformLib/FspPlatformNotify.c | 33 +++++++++---- > .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.c | 55 > +++++++++++----------- > .../FspmWrapperPeim/FspmWrapperPeim.c | 5 +- > .../FspsWrapperPeim/FspsWrapperPeim.c | 5 +- > 6 files changed, 61 insertions(+), 42 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h > b/IntelFsp2Pkg/Include/FspGlobalData.h > index 8ac3199..7de2660 100644 > --- a/IntelFsp2Pkg/Include/FspGlobalData.h > +++ b/IntelFsp2Pkg/Include/FspGlobalData.h > @@ -38,6 +38,7 @@ typedef struct { >=20 > #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') > #define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', > 'R', 'F') > +#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF >=20 > typedef struct { > UINT32 Signature; > diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.i= nf > b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf > index d04689e..907482d 100644 > --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf > +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf > @@ -44,6 +44,10 @@ > [Guids] > gFspPerformanceDataGuid ## > CONSUMES ## GUID > gFspEventEndOfFirmwareGuid ## > PRODUCES ## GUID > + gEfiEventReadyToBootGuid ## > CONSUMES ## Event > + > +[Protocols] > + gEfiPciEnumerationCompleteProtocolGuid ## > CONSUMES >=20 > [FixedPcd] > gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry ## > CONSUMES > diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > index 66b6cdb..755e84f 100644 > --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c > @@ -121,15 +121,12 @@ FspSiliconInitDone ( > // > SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT); > DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - End\n")); > - > - PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, > 0x907F); > - > + PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_EXIT); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > SetFspApiReturnStatus (EFI_SUCCESS); >=20 > Pei2LoaderSwitchStack(); >=20 > - PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, > 0x6000); > } >=20 > /** > @@ -143,6 +140,7 @@ FspMemoryInitDone ( > IN OUT VOID **HobListPtr > ) > { > + FSP_GLOBAL_DATA *FspData; > // > // Calling use FspMemoryInit API > // Update HOB and return the control directly > @@ -155,8 +153,13 @@ FspMemoryInitDone ( > // This is the end of the FspMemoryInit API > // Give control back to the boot loader > // > - SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT); > DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspMemoryInitApi() - End\n")); > + SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT); > + FspData =3D GetFspGlobalDataPointer (); > + PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, > (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), > FSP_STATUS_CODE_TEMP_RAM_INIT | > FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY); > + PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, > (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), > FSP_STATUS_CODE_TEMP_RAM_INIT | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > + PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, > (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), > FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_ENTRY); > + PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_EXIT); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_EXIT); > SetFspApiReturnStatus (EFI_SUCCESS); > Pei2LoaderSwitchStack (); > @@ -166,14 +169,16 @@ FspMemoryInitDone ( > // > if (GetFspApiCallingIndex () =3D=3D TempRamExitApiIndex) { > SetPhaseStatusCode (FSP_STATUS_CODE_TEMP_RAM_EXIT); > - REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_TEMP_RAM_EXIT | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY); > + PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_TEMP_RAM_EXIT | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_TEMP_RAM_EXIT | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - Begin\n")); > } else { > - SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY); > - DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n")); > SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT); > + SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY); > + PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_ENTRY); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_ENTRY); > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n")); > } > } >=20 > @@ -192,16 +197,18 @@ FspTempRamExitDone ( > // This is the end of the TempRamExit API > // Give control back to the boot loader > // > - SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT); > DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - End\n")); > + SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT); > + PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_TEMP_RAM_EXIT | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_TEMP_RAM_EXIT | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > SetFspApiReturnStatus (EFI_SUCCESS); > Pei2LoaderSwitchStack (); >=20 > SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT); > SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY); > - DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n")); > + PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_ENTRY); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_ENTRY); > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n")); > } >=20 > /** > @@ -229,12 +236,15 @@ FspWaitForNotify ( >=20 > if (NotificationCount =3D=3D 0) { > SetPhaseStatusCode > (FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION); > + PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > } else if (NotificationCount =3D=3D 1) { > SetPhaseStatusCode > (FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION); > + PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > } else if (NotificationCount =3D=3D 2) { > SetPhaseStatusCode > (FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION); > + PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > } >=20 > @@ -262,10 +272,13 @@ FspWaitForNotify ( > SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT + > Count); >=20 > if ((NotificationCount - 1) =3D=3D 0) { > + PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > } else if ((NotificationCount - 1) =3D=3D 1) { > + PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > } else if ((NotificationCount - 1) =3D=3D 2) { > + PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > REPORT_STATUS_CODE (EFI_PROGRESS_CODE, > FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); > } > Pei2LoaderSwitchStack(); > diff --git > a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > index 0797f44..a692632 100644 > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > @@ -25,6 +25,7 @@ > #include > #include > #include > +#include >=20 > typedef > EFI_STATUS > @@ -91,9 +92,9 @@ OnPciEnumerationComplete ( > } >=20 > NotifyPhaseParams.Phase =3D EnumInitPhaseAfterPciEnumeration; > - PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > 0x6000); > + PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > Status =3D CallFspNotifyPhase (&NotifyPhaseParams); > - PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x607F); > + PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); >=20 > // > // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED > status > @@ -130,16 +131,13 @@ OnReadyToBoot ( > { > NOTIFY_PHASE_PARAMS NotifyPhaseParams; > EFI_STATUS Status; > - ADD_PERFORMANCE_RECORD_PROTOCOL *AddPerfRecordInterface; > - EFI_PEI_HOB_POINTERS Hob; > - VOID **FspHobListPtr; >=20 > gBS->CloseEvent (Event); >=20 > NotifyPhaseParams.Phase =3D EnumInitPhaseReadyToBoot; > - PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > 0x4000); > + PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > Status =3D CallFspNotifyPhase (&NotifyPhaseParams); > - PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x407F); > + PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); >=20 > // > // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED > status > @@ -154,23 +152,6 @@ OnReadyToBoot ( > } else { > DEBUG((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot Success.\n")); > } > - > - Status =3D gBS->LocateProtocol ( > - &gAddPerfRecordProtocolGuid, > - NULL, > - (VOID**) &AddPerfRecordInterface > - ); > - if (EFI_ERROR (Status)) { > - DEBUG((DEBUG_INFO, "gAddPerfRecordProtocolGuid - Locate > protocol failed\n")); > - return; > - } else { > - Hob.Raw =3D GetHobList (); > - if (Hob.Raw !=3D NULL) { > - Hob.Raw =3D GetNextGuidHob (&gFspHobGuid, Hob.Raw); > - FspHobListPtr =3D GET_GUID_HOB_DATA(Hob.Raw); > - AddPerfRecordInterface->AddPerformanceRecords((VOID > *)(UINTN)(((UINT32)(UINTN)*FspHobListPtr) & 0xFFFFFFFF)); > - } > - } > } >=20 > /** > @@ -189,15 +170,18 @@ OnEndOfFirmware ( > IN VOID *Context > ) > { > - NOTIFY_PHASE_PARAMS NotifyPhaseParams; > - EFI_STATUS Status; > + NOTIFY_PHASE_PARAMS NotifyPhaseParams; > + EFI_STATUS Status; > + ADD_PERFORMANCE_RECORD_PROTOCOL *AddPerfRecordInterface; > + EFI_PEI_HOB_POINTERS Hob; > + VOID **FspHobListPtr; >=20 > gBS->CloseEvent (Event); >=20 > NotifyPhaseParams.Phase =3D EnumInitPhaseEndOfFirmware; > - PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > 0x2000); > + PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > Status =3D CallFspNotifyPhase (&NotifyPhaseParams); > - PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x207F); > + PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT); >=20 > // > // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED > status > @@ -212,6 +196,21 @@ OnEndOfFirmware ( > } else { > DEBUG((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware > Success.\n")); > } > + Status =3D gBS->LocateProtocol ( > + &gAddPerfRecordProtocolGuid, > + NULL, > + (VOID**) &AddPerfRecordInterface > + ); > + if (EFI_ERROR (Status)) { > + DEBUG((DEBUG_INFO, "gAddPerfRecordProtocolGuid - Locate > protocol failed\n")); > + return; > + } else { > + Hob.Raw =3D GetFirstGuidHob (&gFspHobGuid); > + if (Hob.Raw !=3D NULL) { > + FspHobListPtr =3D GET_GUID_HOB_DATA (Hob.Raw); > + AddPerfRecordInterface->AddPerformanceRecords ((VOID > *)(UINTN)(((UINT32)(UINTN)*FspHobListPtr) & 0xFFFFFFFF)); > + } > + } > } >=20 > /** > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > index 0f6a7bd..f1d1cd6 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > @@ -38,6 +38,7 @@ > #include > #include > #include > +#include >=20 > extern EFI_GUID gFspHobGuid; >=20 > @@ -89,8 +90,8 @@ PeiFspMemoryInit ( > TimeStampCounterStart =3D AsmReadTsc (); > Status =3D CallFspMemoryInit (FspmUpdDataPtr, &FspHobListPtr); > // Create hobs after memory initialization and not in temp RAM. Hence > passing the recorded timestamp here > - PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, > TimeStampCounterStart, 0xD000); > - PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0xD07F); > + PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, > TimeStampCounterStart, FSP_STATUS_CODE_MEMORY_INIT | > FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY); > + PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_EXIT); > DEBUG ((DEBUG_INFO, "Total time spent executing > FspMemoryInitApi: %d millisecond\n", DivU64x32 (GetTimeInNanoSecond > (AsmReadTsc () - TimeStampCounterStart), 1000000))); >=20 > // > diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > index 1701b63..ddc19c7 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > @@ -38,6 +38,7 @@ > #include > #include > #include > +#include >=20 > extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc; > extern EFI_GUID gFspHobGuid; > @@ -253,9 +254,9 @@ PeiMemoryDiscoveredNotify ( > UpdateFspsUpdData ((VOID *)FspsUpdDataPtr); >=20 > TimeStampCounterStart =3D AsmReadTsc (); > - PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > 0x9000); > + PERF_START_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_ENTRY); > Status =3D CallFspSiliconInit ((VOID *)FspsUpdDataPtr); > - PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, 0x907F); > + PERF_END_EX(&gFspApiPerformanceGuid, "EventRec", NULL, 0, > FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | > FSP_STATUS_CODE_API_EXIT); > DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d > millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - > TimeStampCounterStart), 1000000))); >=20 > // > -- > 2.10.0.windows.1