From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 68C151A1E28 for ; Fri, 21 Oct 2016 22:14:47 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP; 21 Oct 2016 22:14:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,528,1473145200"; d="scan'208,217";a="1057448333" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 21 Oct 2016 22:14:46 -0700 Received: from fmsmsx123.amr.corp.intel.com (10.18.125.38) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 21 Oct 2016 22:14:46 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx123.amr.corp.intel.com (10.18.125.38) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 21 Oct 2016 22:14:41 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.206]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.209]) with mapi id 14.03.0248.002; Sat, 22 Oct 2016 13:14:37 +0800 From: "Yao, Jiewen" To: "Dong, Guo" , "Mudusuru, Giri P" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if signaling first event. Thread-Index: AQHSKMk+4IDiZaFn1kmptzPOoZUo06CtCLIAgAAI7YCAAIazIP//jAcAgAZtWjD//4LCgIAA3XYg Date: Sat, 22 Oct 2016 05:14:36 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C50386B57BB@shsmsx102.ccr.corp.intel.com> References: <4666AEFED60F8E4198B42BB01DCEABDF76F16C6A@ORSMSX113.amr.corp.intel.com> <0DE6ECBAEEB99B4DA9564FF580F3580A0D2C340A@fmsmsx120.amr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386B2B30@shsmsx102.ccr.corp.intel.com> <0DE6ECBAEEB99B4DA9564FF580F3580A0D2C3452@fmsmsx120.amr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386B5687@shsmsx102.ccr.corp.intel.com> <0DE6ECBAEEB99B4DA9564FF580F3580A0D2C4342@fmsmsx120.amr.corp.intel.com> In-Reply-To: <0DE6ECBAEEB99B4DA9564FF580F3580A0D2C4342@fmsmsx120.amr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if signaling first event. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 22 Oct 2016 05:14:47 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable My thinking is to define mask for ALL APIs, not 3. We have 5 APIs, and 3 sub API for notify phase. How about this : # BIT0~15 is for function: # BIT0 - Mask TempRamInit # BIT1 - Mask MemoryInit # BIT2 - Mask TempRamExit # BIT3 - Mask SiliconInit # BIT4 - Mask NotifyPhase # BIT16~32 is for sub-function: # BIT16 - Mask NotifyPhase (AfterPciEnumeration) # BIT17 - Mask NotifyPhase (ReadyToBoot) # BIT18 - Mask NotifyPhase (EndOfFirmware) # Any undefined BITs are reserved for future use PcdFspApiSkipMask|UINT32 You can use BIT16 now. We may use BIT0+BIT2 later. And any other combinatio= n in the future. From: Dong, Guo Sent: Saturday, October 22, 2016 7:52 AM To: Yao, Jiewen ; Mudusuru, Giri P ; edk2-devel@lists.01.org Cc: Ma, Maurice ; Yarlagadda, Satya P Subject: RE: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if si= gnaling first event. I am OK with bit mask PCD. Now only 3 APIs in this driver. Do we really need UINT64? Thanks, Guo From: Yao, Jiewen Sent: Friday, October 21, 2016 4:23 PM To: Dong, Guo >; Mudusuru, Gi= ri P >; edk2-de= vel@lists.01.org Cc: Ma, Maurice >; Yarlag= adda, Satya P > Subject: RE: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if si= gnaling first event. Understood. I agree that is a valid usage model. So how about we define a bit mask for every function? Such as "PcdFspApiSki= pMask|UINT64" - I am open on any naming proposal. In the future we may need skip some other functions such as InitTempRam or = TempRamExit. Thank you Yao Jiewen From: Dong, Guo Sent: Tuesday, October 18, 2016 1:11 PM To: Yao, Jiewen >; Mudusu= ru, Giri P >; e= dk2-devel@lists.01.org Cc: Ma, Maurice >; Yarlag= adda, Satya P > Subject: RE: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if si= gnaling first event. Hi Jiewen, For Coreboot boot loader, PCI device enumeration is done in coreboot, so it= is nature Coreboot sends PciEnumerationComplete to FSP. UEFI payload would= send FSP ReadyToBoot and EndOfFirmware notification. If there is other boot loader that sends ReadyToBoot and EndOfFirmware in d= ifferent firmware component, we may add PCDs for them later. Thanks, Guo From: Yao, Jiewen Sent: Monday, October 17, 2016 9:10 PM To: Dong, Guo >; Mudusuru, Gi= ri P >; edk2-de= vel@lists.01.org Cc: Ma, Maurice >; Yarlag= adda, Satya P >; Yao, Jiewen > Subject: RE: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if si= gnaling first event. Hi I am a little concern on this as well. If today, there is a POC require skipping PciEnumerationComplete. There might be the other POC tomorrow to skip ReadyToBoot Then another POC to skip EventExitBootServices. We will be exhausted to add POC to skip each separately. Can this POC handle all 3 event together? Or not handle 3 event completely? Thank you Yao Jiewen From: Dong, Guo Sent: Tuesday, October 18, 2016 12:04 PM To: Mudusuru, Giri P >; edk2-devel@lists.01.org Cc: Yao, Jiewen >; Ma, Ma= urice >; Yarlagadda, Saty= a P > Subject: RE: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if si= gnaling first event. Hi Giri, Thank you for the comment. In our POC implementation, Coreboot will notify FSP EnumerationComplete. A= nd in UEFI payload, the other 2 FSP notifications will be called from FspWr= apperNotifyDxe. Thanks, Guo -----Original Message----- From: Mudusuru, Giri P Sent: Monday, October 17, 2016 8:32 PM To: Dong, Guo >; edk2-devel@l= ists.01.org Cc: Yao, Jiewen >; Ma, Ma= urice >; Yarlagadda, Saty= a P > Subject: RE: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if si= gnaling first event. Hello Guo, FSP wrapper and Coreboot are bootloaders consuming FSP binary. FSP must get called Post PCI bus enumeration to do the required silicon ini= tialization. Why do we need a PCD to skip it? Thanks, -Giri > -----Original Message----- > From: Dong, Guo > Sent: Monday, October 17, 2016 3:53 PM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen >; Mudu= suru, Giri P > >; Dong, Guo = > > Subject: [edk2] [PATCH] IntelFsp2WrapperPkg: Add a PCD to control if > signaling first event. > > PciEnumerationComplete might be signaled to FSP in Coreboot. Add a PCD > PcdNotifyPciEnumerationComplete so FspWrapperNotifyDxe driver could be > used in this case. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: gdong1 > > --- > .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.c | 18 ++++++++++--= ------ > .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf | 3 ++- > IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 5 +++++ > 3 files changed, 17 insertions(+), 9 deletions(-) > > diff --git > a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > index 0797f44..45eae4b 100644 > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > @@ -246,14 +246,16 @@ FspWrapperNotifyDxeEntryPoint ( > return EFI_SUCCESS; > } > > - ProtocolNotifyEvent =3D EfiCreateProtocolNotifyEvent ( > - &gEfiPciEnumerationCompleteProtocolGuid, > - TPL_CALLBACK, > - OnPciEnumerationComplete, > - NULL, > - &Registration > - ); > - ASSERT (ProtocolNotifyEvent !=3D NULL); > + if (PcdGetBool(PcdNotifyPciEnumerationComplete)) { > + ProtocolNotifyEvent =3D EfiCreateProtocolNotifyEvent ( > + &gEfiPciEnumerationCompleteProtocolGuid, > + TPL_CALLBACK, > + OnPciEnumerationComplete, > + NULL, > + &Registration > + ); > + ASSERT (ProtocolNotifyEvent !=3D NULL); } > > Status =3D EfiCreateEventReadyToBootEx ( > TPL_CALLBACK, > diff --git > a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > index f851f68..f28356d 100644 > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > @@ -61,7 +61,8 @@ > gFspHobGuid ## CONSUMES ## HOB > > [Pcd] > - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdNotifyPciEnumerationComplete ## > CONSUMES > > [Depex] > TRUE > diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > index d9d2d80..52ed9d8 100644 > --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > @@ -74,6 +74,11 @@ > ## This is the base address of FSP-T/M/S > > gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32| > 0x00000300 > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32 > |0x00000301 > + ## Indicates if the FSP wrapper will notify FSP > PciEnumerationComplete.

> + # TRUE - FSP wrapper will notify PciEnumerationComplete to FSP.
> + # FALSE - FSP wrapper will NOT notify PciEnumerationComplete to FSP.=
> + # @Prompt Notify FSP PciEnumerationComplete. > + > gIntelFsp2WrapperTokenSpaceGuid.PcdNotifyPciEnumerationComplete|TRUE| > BOOLEAN|0x40000009 > > [PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx] > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32| > 0x00001001 > -- > 2.7.0.windows.1