From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 337A01A1E46 for ; Mon, 24 Oct 2016 21:54:43 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP; 24 Oct 2016 21:54:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,544,1473145200"; d="scan'208,217";a="23242448" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga006.fm.intel.com with ESMTP; 24 Oct 2016 21:54:42 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 24 Oct 2016 21:54:42 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.206]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.209]) with mapi id 14.03.0248.002; Tue, 25 Oct 2016 12:54:39 +0800 From: "Yao, Jiewen" To: "Mudusuru, Giri P" , "Dong, Guo" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH v2] IntelFsp2WrapperPkg: Add a PCD to control if signaling PciEnumerationComplete. Thread-Index: AQHSLhiCbp+2IcKxU0utwjZG5RCrr6C4PTxQ///EVgCAAJn50A== Date: Tue, 25 Oct 2016 04:54:39 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C50386B6928@shsmsx102.ccr.corp.intel.com> References: <74D8A39837DF1E4DA445A8C0B3885C50386B671C@shsmsx102.ccr.corp.intel.com> <4666AEFED60F8E4198B42BB01DCEABDF76F299F8@ORSMSX113.amr.corp.intel.com> In-Reply-To: <4666AEFED60F8E4198B42BB01DCEABDF76F299F8@ORSMSX113.amr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [PATCH v2] IntelFsp2WrapperPkg: Add a PCD to control if signaling PciEnumerationComplete. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Oct 2016 04:54:43 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Agree all. From: Mudusuru, Giri P Sent: Tuesday, October 25, 2016 11:43 AM To: Yao, Jiewen ; Dong, Guo ; edk= 2-devel@lists.01.org Cc: Ma, Maurice Subject: RE: [edk2] [PATCH v2] IntelFsp2WrapperPkg: Add a PCD to control if= signaling PciEnumerationComplete. We can add full description with note that only skip NotifyPhase Post PCI e= numeration is implemented. 1) Change "BIT0~15 is for function:" to "BIT[15:0] is for function:" and "B= IT16~32 is for sub-function:" to "BIT[32:16] is for sub-function:" for cons= istency 2) Suggest to rename fix below define FSP_API_NOTIFY_PHASE_AFTER_PCI_ENUME= RATION to be consistent with other usage +#define PCI_ENUMERATION_COMPLETE_API BIT16 3) Also for PCD naming suggest to change PcdSkipFspApi Thanks, -Giri > -----Original Message----- > From: Yao, Jiewen > Sent: Monday, October 24, 2016 4:18 PM > To: Dong, Guo >; edk2-devel= @lists.01.org > Cc: Mudusuru, Giri P >; Ma, Maurice > > > Subject: RE: [edk2] [PATCH v2] IntelFsp2WrapperPkg: Add a PCD to control = if > signaling PciEnumerationComplete. > > Thanks Guo. Can we add full description for the PCD? > > # BIT0~15 is for function: > # BIT0 - Mask TempRamInit > # BIT1 - Mask MemoryInit > # BIT2 - Mask TempRamExit > # BIT3 - Mask SiliconInit > # BIT4 - Mask NotifyPhase > # BIT16~32 is for sub-function: > # BIT16 - Mask NotifyPhase (AfterPciEnumeration) > # BIT17 - Mask NotifyPhase (ReadyToBoot) > # BIT18 - Mask NotifyPhase (EndOfFirmware) > # Any undefined BITs are reserved for future use > > > Thank you > Yao Jiewen > > > -----Original Message----- > > From: Dong, Guo > > Sent: Tuesday, October 25, 2016 1:03 AM > > To: edk2-devel@lists.01.org > > Cc: Yao, Jiewen >; Mu= dusuru, Giri P > > >; Ma, Maur= ice >; Dong, > > Guo > > > Subject: [edk2] [PATCH v2] IntelFsp2WrapperPkg: Add a PCD to control if > > signaling PciEnumerationComplete. > > > > PciEnumerationComplete might be signaled to FSP in Coreboot. So FSP > > wrapper driver don't need send it again. Add a PCD to control if a > > FSP API could be skipped from FspWrapperNotifyDxe driver. > > > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Guo Dong > > > Reviewed-by: Maurice Ma > > > Reviewed-by: Jiewen Yao > > > Reviewed-by: Giri P Mudusuru > > > --- > > .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.c | 22 > > ++++++++++++++-------- > > .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf | 1 + > > IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 8 ++++++++ > > 3 files changed, 23 insertions(+), 8 deletions(-) > > > > diff --git > > a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > > index 0797f44..969debc 100644 > > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > > +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c > > @@ -26,6 +26,8 @@ > > #include > > #include > > > > +#define PCI_ENUMERATION_COMPLETE_API BIT16 > > + > > typedef > > EFI_STATUS > > (EFIAPI * ADD_PERFORMANCE_RECORDS)( > > @@ -237,6 +239,7 @@ FspWrapperNotifyDxeEntryPoint ( > > EFI_EVENT ReadyToBootEvent; > > VOID *Registration; > > EFI_EVENT ProtocolNotifyEvent; > > + UINT32 FspApiMask; > > > > // > > // Load this driver's image to memory > > @@ -246,14 +249,17 @@ FspWrapperNotifyDxeEntryPoint ( > > return EFI_SUCCESS; > > } > > > > - ProtocolNotifyEvent =3D EfiCreateProtocolNotifyEvent ( > > - > > &gEfiPciEnumerationCompleteProtocolGuid, > > - TPL_CALLBACK, > > - OnPciEnumerationComplete, > > - NULL, > > - &Registration > > - ); > > - ASSERT (ProtocolNotifyEvent !=3D NULL); > > + FspApiMask =3D PcdGet32 (PcdFspApiSkipMask); > > + if ((FspApiMask & PCI_ENUMERATION_COMPLETE_API) =3D=3D 0) { > > + ProtocolNotifyEvent =3D EfiCreateProtocolNotifyEvent ( > > + > > &gEfiPciEnumerationCompleteProtocolGuid, > > + TPL_CALLBACK, > > + OnPciEnumerationComplete, > > + NULL, > > + &Registration > > + ); > > + ASSERT (ProtocolNotifyEvent !=3D NULL); > > + } > > > > Status =3D EfiCreateEventReadyToBootEx ( > > TPL_CALLBACK, > > diff --git > > a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > > index f851f68..9ef81ff 100644 > > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > > +++ > > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > > @@ -62,6 +62,7 @@ > > > > [Pcd] > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## > > CONSUMES > > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspApiSkipMask ## > > CONSUMES > > > > [Depex] > > TRUE > > diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > > b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > > index d9d2d80..534f482 100644 > > --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > > +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > > @@ -75,6 +75,14 @@ > > > > gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT3 > > 2|0x00000300 > > > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT > > 32|0x00000301 > > > > + ## This PCD indicates if FSP APIs are skipped from FSP wrapper.
<= BR> > > + # If a bit is set, that means this FSP API is skipped.
> > + # If a bit is clear, that means this FSP API is NOT skipped.
> > + # BIT16 - Mask NotifyPhase (AfterPciEnumeration).
> > + # Any undefined BITs are reserved for future use.
> > + # @Prompt FSP API skip mask from FSP wrapper. > > + > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspApiSkipMask|0x00000000|UINT3 > > 2|0x40000009 > > + > > [PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx] > > > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT > > 32|0x00001001 > > > > \ No newline at end of file > > -- > > 2.7.0.windows.1