From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA34D81D3D for ; Fri, 4 Nov 2016 06:28:45 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP; 04 Nov 2016 06:28:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,443,1473145200"; d="scan'208,217";a="27534752" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga005.jf.intel.com with ESMTP; 04 Nov 2016 06:28:47 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 4 Nov 2016 06:28:47 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 4 Nov 2016 06:28:46 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.206]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.104]) with mapi id 14.03.0248.002; Fri, 4 Nov 2016 21:28:44 +0800 From: "Yao, Jiewen" To: Paolo Bonzini , "Kinney, Michael D" , Laszlo Ersek CC: "Tian, Feng" , =?iso-8859-1?Q?Radim_Kr=3Fm=E1=3F?= , "edk2-devel@ml01.01.org" , "Fan, Jeff" , "Zeng, Star" Thread-Topic: [edk2] [PATCH 0/6] Enable SMM page level protection. Thread-Index: AQHSNZ8XswckCVz0V0usOM0dRj4P2qDIQKiAgAAj+QD//4+B8IAAh/AA//+jakCAAAFJoIAAAZQw//983YAAADuvgAAQ+CXwAACRugAAFH28gA== Date: Fri, 4 Nov 2016 13:28:43 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C50386BE6A3@shsmsx102.ccr.corp.intel.com> References: <74D8A39837DF1E4DA445A8C0B3885C50386BE1E9@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386BE2A5@shsmsx102.ccr.corp.intel.com> <188de6ef-f0cb-a330-bfdf-0fe4eec503ba@redhat.com> In-Reply-To: <188de6ef-f0cb-a330-bfdf-0fe4eec503ba@redhat.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [PATCH 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Nov 2016 13:28:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Thank you Paolo. I tried below way. But it does not help too much. It still takes more than = 1 minutes to boot with SMP=3D8. SendSmiIpiAllExcludingSelf (); IoWrite8 (ICH9_APM_STS, DataPort =3D=3D NULL ? 0 : *DataPort); IoWrite8 (ICH9_APM_CNT, CommandPort =3D=3D NULL ? 0 : *CommandPort); I also tried to reduce the timeout PCD to: gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000 However, I find CPU-2 is still missing. Maybe it is caused by QEMU emulate AP in serial mode, not parallel mode. I think it might be best choice to set PcdCpuSmmSyncMode|0x1 It also helps cover a very corner case in SMM. :) At same time, would you mind help to take a look at the S3 unstable issue? = If you have any clue, please let me know. Thank you Yao Jiewen From: Paolo Bonzini [mailto:pbonzini@redhat.com] Sent: Friday, November 4, 2016 7:34 PM To: Yao, Jiewen ; Kinney, Michael D ; Laszlo Ersek Cc: Tian, Feng ; Radim Kr?m=E1? ; = edk2-devel@ml01.01.org; Fan, Jeff ; Zeng, Star Subject: Re: [edk2] [PATCH 0/6] Enable SMM page level protection. On 04/11/2016 04:20, Yao, Jiewen wrote: > Good info. Thanks! > > I do not understand below word. I still see a **huge** performance gap. > > I am confused on how is it resolved in previous patch. Or do I need > configure something for my QEMU? The delay you're seeing comes from SmmWaitForApArrival. See this explanation: ---- Port 0xb2 on QEMU only sends an SMI to the currently executing processor. The SMI handler, however, and in particular SmmWaitForApArrival, currently expects that SmmControl2DxeTrigger triggers an SMI IPI on all processors rather than just the BSP. Thus all SMM invocations loop for a second (the default value of PcdCpuSmmApSyncTimeout) before SmmWaitForApArrival sends another SMI IPI to the APs. ---- Can you try calling SendSmiIpiAllExcludingSelf in SmmControl2DxeTrigger (OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c) before the I/O port writes? Thanks, Paolo