From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9C90181EC0 for ; Fri, 11 Nov 2016 01:12:15 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP; 11 Nov 2016 01:12:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,620,1473145200"; d="scan'208";a="30067322" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga006.fm.intel.com with ESMTP; 11 Nov 2016 01:12:19 -0800 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 11 Nov 2016 01:12:18 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 11 Nov 2016 01:12:18 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.239]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.138]) with mapi id 14.03.0248.002; Fri, 11 Nov 2016 17:12:16 +0800 From: "Yao, Jiewen" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: "Tian, Feng" , "Kinney, Michael D" , Paolo Bonzini , "Laszlo Ersek" , "Fan, Jeff" , "Zeng, Star" Thread-Topic: [edk2] [PATCH V3 0/6] Enable SMM page level protection. Thread-Index: AQHSO/pAI7G2Yg21Yk2nIlgPeIwk7qDTfLhA Date: Fri, 11 Nov 2016 09:12:16 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C50386CF501@shsmsx102.ccr.corp.intel.com> References: <1478854859-11096-1-git-send-email-jiewen.yao@intel.com> In-Reply-To: <1478854859-11096-1-git-send-email-jiewen.yao@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH V3 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Nov 2016 09:12:15 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable HI Laszlo I fixed the IA32 boot issue in this patch with DEBUG message update you sug= gested. My unit test failed before. Now it can pass. I validated on a real IA32 and Windows OVMF with and without XD. For QEMU installation, it is still on progress. We have setup a Fedora 24 host, download QEMU, and install it. But we are still struggling to make QEMU boot on Fedora. Your step by step is great. There is still some minor place we stuck in due= to my ignorance. My goal is still to setup an environment like yours for our validation or i= ssue reproduce. It just need take some time, more than I expected. sign... Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Jiewen Yao > Sent: Friday, November 11, 2016 5:01 PM > To: edk2-devel@lists.01.org > Cc: Tian, Feng ; Kinney, Michael D > ; Paolo Bonzini ; > Laszlo Ersek ; Fan, Jeff ; Zeng, > Star > Subject: [edk2] [PATCH V3 0/6] Enable SMM page level protection. >=20 >=20 > =3D=3D=3D=3D below is V3 description =3D=3D=3D=3D > 1) PiSmmCpu: Fix CpuIndex corruption issue due to stack malposition. > (Many thanks to Laszlo Ersek for catching it.) > 2) PiSmmCpu: Add ASSERT for CpuIndex check. > 3) PiSmmCpu: Use DEBUG_VERBOSE for page table update. > 4) PiSmmCpu: Do not report DEBUG message for Ap non present > when PcdCpuSmmSyncMode=3D=3D1 (Relex mode). > 5) PiSmmCpu: Do not report DEBUG message for AP removed > when PcdCpuHotPlugSupport=3D=3DTRUE. >=20 > Tested combination: > 1) XD disabled > 2) XD enabled in SMM and disabled in non-SMM. > 3) XD enabled in SMM and enabled in non-SMM. >=20 > =3D=3D=3D=3D below is V2 description =3D=3D=3D=3D > 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue. > 2) PiSmmCpu: Add debug info on StartupAp() fails. > 3) PiSmmCpu: Add ASSERT for AllocatePages(). > 4) PiSmmCpu: Add protection detail in commit message. > 5) UefiCpuPkg.dsc: Add page table footprint info in commit message. >=20 > =3D=3D=3D=3D below is V1 description =3D=3D=3D=3D > This series patch enables SMM page level protection. > Features are: > 1) PiSmmCore reports SMM PE image code/data information > in EdkiiPiSmmMemoryAttributeTable, if the SMM image is page aligned. > 2) PiSmmCpu consumes EdkiiPiSmmMemoryAttributeTable > and set XD for data page and RO for code page. > 3) PiSmmCpu enables Static Paging for X64 according to > PcdCpuSmmStaticPageTable. If it is true, 1G paging for above 4G > is used as long as it is supported. > 4) PiSmmCpu sets importance data structure to be read only, > such as Gdt, Idt, SmmEntrypoint, and PageTable itself. >=20 > tested platform: > 1) Intel internal platform (X64). > 2) EDKII Quark IA32 > 3) EDKII Vlv2 X64 > 4) EDKII OVMF IA32 and IA32X64. (with -smp 8) >=20 > Cc: Jeff Fan > Cc: Feng Tian > Cc: Star Zeng > Cc: Michael D Kinney > Cc: Laszlo Ersek > Cc: Paolo Bonzini > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao >=20 > Jiewen Yao (6): > MdeModulePkg/Include: Add PiSmmMemoryAttributesTable.h > MdeModulePkg/dec: Add gEdkiiPiSmmMemoryAttributesTableGuid. > MdeModulePkg/PiSmmCore: Add MemoryAttributes support. > UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable. > UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection. > QuarkPlatformPkg/dsc: enable Smm paging protection. >=20 > MdeModulePkg/Core/PiSmmCore/Dispatcher.c | 66 + > MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c | 1509 > ++++++++++++++++++++ > MdeModulePkg/Core/PiSmmCore/Page.c | 775 > +++++++++- > MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 40 > + > MdeModulePkg/Core/PiSmmCore/PiSmmCore.h | 91 > ++ > MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf | 2 > + > MdeModulePkg/Core/PiSmmCore/Pool.c | 16 > + > MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h | 51 + > MdeModulePkg/MdeModulePkg.dec | > 3 + > QuarkPlatformPkg/Quark.dsc | 6 + > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 71 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 75 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 75 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 79 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S | 226 > +-- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 36 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 36 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 37 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 4 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 135 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | > 144 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | > 156 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | > 5 +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | > 871 +++++++++++ > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 39 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 274 > +++- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 59 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 62 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 69 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S | 250 > +--- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm | 35 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 31 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 30 > +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 7 > +- > UefiCpuPkg/UefiCpuPkg.dec | 8 + > 36 files changed, 4585 insertions(+), 803 deletions(-) > create mode 100644 > MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c > create mode 100644 > MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h > create mode 100644 > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >=20 > -- > 2.7.4.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel