From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A69E981F1B for ; Thu, 17 Nov 2016 04:03:30 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP; 17 Nov 2016 04:03:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,653,1473145200"; d="scan'208,217";a="32458680" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga006.fm.intel.com with ESMTP; 17 Nov 2016 04:03:35 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 17 Nov 2016 04:03:34 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.239]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.239]) with mapi id 14.03.0248.002; Thu, 17 Nov 2016 20:03:32 +0800 From: "Yao, Jiewen" To: Laszlo Ersek , "Kinney, Michael D" , "Fan, Jeff" , "edk2-devel@lists.01.org" CC: Paolo Bonzini , "Tian, Feng" , "Zeng, Star" Thread-Topic: [edk2] [PATCH V3 0/6] Enable SMM page level protection. Thread-Index: AQHSQGvdp+FP26f1OUuEs0NS0REgSqDb3XIAgACHh8CAAAV6AIAAqY/w Date: Thu, 17 Nov 2016 12:03:31 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C50386D6831@shsmsx102.ccr.corp.intel.com> References: <1478854859-11096-1-git-send-email-jiewen.yao@intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4A2DF9C8@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386D626B@shsmsx102.ccr.corp.intel.com> <17b2381f-0233-df0f-d27f-8e2c8fd4736e@redhat.com> In-Reply-To: <17b2381f-0233-df0f-d27f-8e2c8fd4736e@redhat.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [PATCH V3 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Nov 2016 12:03:30 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Oops, my bad. Thank you for check in that for me. Thank you Yao Jiewen From: Laszlo Ersek [mailto:lersek@redhat.com] Sent: Thursday, November 17, 2016 5:55 PM To: Yao, Jiewen ; Kinney, Michael D ; Fan, Jeff ; edk2-devel@lists.01.org Cc: Paolo Bonzini ; Tian, Feng ; = Zeng, Star Subject: Re: [edk2] [PATCH V3 0/6] Enable SMM page level protection. Jiewen, On 11/17/16 02:36, Yao, Jiewen wrote: > You are right. That is good suggestion to mention it. I will add. > > Thank you > Yao Jiewen You forgot to commit patch #1 from the series, and the build is now broken. ... I have now committed patch #1 for you, with the following commit message modifications (all according to feedback on the list): - added my T-b - added Jeff's R-b - added Mike's R-b - added Mike's paragraph (visible below) about gEdkiiPiSmmMemoryAttributesTableGuid Commit 97d2760429d6. Also I see patch #6 (17abe97671ee), for QuarkPlatformPkg, got committed with my Tested-by. I didn't test that patch, and I even said so -- I wrote "For patches #1 through #5". Please be more careful about last minute changes and about applying feedback tags. Thanks Laszlo > From: Kinney, Michael D > Sent: Thursday, November 17, 2016 9:31 AM > To: Fan, Jeff >; Yao, Jiewe= n >; edk2-devel@lists.01.= org; Kinney, Michael D > > Cc: Tian, Feng >; Zeng, S= tar >; Laszlo Ersek >; Paolo Bonzini > > Subject: RE: [PATCH V3 0/6] Enable SMM page level protection. > > Jiewen, > > The new file MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c and the > new code in MdeModulePkg/Core/PiSmmCore/Page.c are based on the algorithm= s > and implementation from MdeModulePkg/Core/Dxe/Misc/MemoryAttributesTable.= c > and MdeModulePkg/Core/Dxe/Mem/Page.c. > > Also, the new GUID gEdkiiPiSmmMemoryAttributesTableGuid and its associate= d > structure are based on the EFI_MEMORY_ATTRIBUTES_TABLE and GUID from the > UEFI Specification. > > I recommend you update the commit messages to highlight that these new > components are based on the Memory Attributes Table feature from the UEFI > Specification and the existing DXE Core implementation that supports that > feature. > > With those commit message updates, Series > > Reviewed-by: Michael Kinney >> > > Mike > >> -----Original Message----- >> From: Fan, Jeff >> Sent: Wednesday, November 16, 2016 4:45 PM >> To: Yao, Jiewen >>; edk2-devel@lists.01= .org> >> Cc: Tian, Feng >>; Zeng, Star >>; Kinney, >> Michael D >>; L= aszlo Ersek >>; Paolo >> Bonzini >> >> Subject: RE: [PATCH V3 0/6] Enable SMM page level protection. >> >> Reviewed-by: Jeff Fan >> >> >> Thanks! >> >> -----Original Message----- >> From: Yao, Jiewen >> Sent: Friday, November 11, 2016 5:01 PM >> To: edk2-devel@lists.01.org> >> Cc: Fan, Jeff; Tian, Feng; Zeng, Star; Kinney, Michael D; Laszlo Ersek; = Paolo Bonzini >> Subject: [PATCH V3 0/6] Enable SMM page level protection. >> >> >> =3D=3D=3D=3D below is V3 description =3D=3D=3D=3D >> 1) PiSmmCpu: Fix CpuIndex corruption issue due to stack malposition. >> (Many thanks to Laszlo Ersek >> for catching it.) >> 2) PiSmmCpu: Add ASSERT for CpuIndex check. >> 3) PiSmmCpu: Use DEBUG_VERBOSE for page table update. >> 4) PiSmmCpu: Do not report DEBUG message for Ap non present when PcdCpuS= mmSyncMode=3D=3D1 >> (Relex mode). >> 5) PiSmmCpu: Do not report DEBUG message for AP removed when >> PcdCpuHotPlugSupport=3D=3DTRUE. >> >> Tested combination: >> 1) XD disabled >> 2) XD enabled in SMM and disabled in non-SMM. >> 3) XD enabled in SMM and enabled in non-SMM. >> >> =3D=3D=3D=3D below is V2 description =3D=3D=3D=3D >> 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue. >> 2) PiSmmCpu: Add debug info on StartupAp() fails. >> 3) PiSmmCpu: Add ASSERT for AllocatePages(). >> 4) PiSmmCpu: Add protection detail in commit message. >> 5) UefiCpuPkg.dsc: Add page table footprint info in commit message. >> >> =3D=3D=3D=3D below is V1 description =3D=3D=3D=3D >> This series patch enables SMM page level protection. >> Features are: >> 1) PiSmmCore reports SMM PE image code/data information in >> EdkiiPiSmmMemoryAttributeTable, if the SMM image is page aligned. >> 2) PiSmmCpu consumes EdkiiPiSmmMemoryAttributeTable and set XD for data = page and RO >> for code page. >> 3) PiSmmCpu enables Static Paging for X64 according to PcdCpuSmmStaticPa= geTable. If >> it is true, 1G paging for above 4G is used as long as it is supported. >> 4) PiSmmCpu sets importance data structure to be read only, such as Gdt,= Idt, >> SmmEntrypoint, and PageTable itself. >> >> tested platform: >> 1) Intel internal platform (X64). >> 2) EDKII Quark IA32 >> 3) EDKII Vlv2 X64 >> 4) EDKII OVMF IA32 and IA32X64. (with -smp 8) >> >> Cc: Jeff Fan >> >> Cc: Feng Tian >> >> Cc: Star Zeng >> >> Cc: Michael D Kinney >> >> Cc: Laszlo Ersek >> >> Cc: Paolo Bonzini >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Jiewen Yao >> >> >> Jiewen Yao (6): >> MdeModulePkg/Include: Add PiSmmMemoryAttributesTable.h >> MdeModulePkg/dec: Add gEdkiiPiSmmMemoryAttributesTableGuid. >> MdeModulePkg/PiSmmCore: Add MemoryAttributes support. >> UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable. >> UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection. >> QuarkPlatformPkg/dsc: enable Smm paging protection. >> >> MdeModulePkg/Core/PiSmmCore/Dispatcher.c | 66 + >> MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c | 1509 +++++++++= +++++++++++ >> MdeModulePkg/Core/PiSmmCore/Page.c | 775 +++++++++= - >> MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 40 + >> MdeModulePkg/Core/PiSmmCore/PiSmmCore.h | 91 ++ >> MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf | 2 + >> MdeModulePkg/Core/PiSmmCore/Pool.c | 16 + >> MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h | 51 + >> MdeModulePkg/MdeModulePkg.dec | 3 + >> QuarkPlatformPkg/Quark.dsc | 6 + >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 71 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 75 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 75 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 79 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S | 226 +-- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 36 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 36 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 37 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 4 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 135 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 144 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 156 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 5 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 871 +++++++++= ++ >> UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 39 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 274 +++- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 59 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 62 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 69 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S | 250 +--- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm | 35 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 31 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 30 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 7 +- >> UefiCpuPkg/UefiCpuPkg.dec | 8 + >> 36 files changed, 4585 insertions(+), 803 deletions(-) create mode 100= 644 >> MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c >> create mode 100644 MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable= .h >> create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >> >> -- >> 2.7.4.windows.1 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel >