From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5B29081EBA for ; Tue, 6 Dec 2016 23:44:53 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP; 06 Dec 2016 23:44:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,310,1477983600"; d="scan'208";a="1078568869" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga001.fm.intel.com with ESMTP; 06 Dec 2016 23:44:52 -0800 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 6 Dec 2016 23:44:52 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX153.amr.corp.intel.com (10.18.125.6) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 6 Dec 2016 23:44:52 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.239]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.218]) with mapi id 14.03.0248.002; Wed, 7 Dec 2016 15:44:50 +0800 From: "Yao, Jiewen" To: "Kinney, Michael D" , "edk2-devel@lists.01.org" CC: "Wei, David" , "Guo, Mang" Thread-Topic: [Patch] Vlv2TbltDevicePkg/PlatformInitPei: Better SMRAM size alignment Thread-Index: AQHST4QZ2vlKj2/gtEWbxHjvKulNT6D8HICQ Date: Wed, 7 Dec 2016 07:44:49 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C50386E1B3D@shsmsx102.ccr.corp.intel.com> References: <1481003182-33040-1-git-send-email-michael.d.kinney@intel.com> In-Reply-To: <1481003182-33040-1-git-send-email-michael.d.kinney@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] Vlv2TbltDevicePkg/PlatformInitPei: Better SMRAM size alignment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Dec 2016 07:44:53 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Kinney, Michael D > Sent: Tuesday, December 6, 2016 1:46 PM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Wei, David ; > Guo, Mang > Subject: [Patch] Vlv2TbltDevicePkg/PlatformInitPei: Better SMRAM size > alignment >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D260 >=20 > Update workaround to be more generic. >=20 > * Search for the largest region between 1MB and 4GB > * Find all adjacent regions to compute total size > * Minimum aligned size if 4KB > * Mark extended region to align size as EFI_ALLOCATED > * If an adjacent EFI_ALLOCATED region is present, then > increase the size of the adjacent region. > * If adjacent EFI_ALLOCATED region is not present, then > allocate a new HOB with one extra entry to describe > the extended region to align the total size. Preserve > the last entry in the descriptor list for compatibility. >=20 > This is a workaround until the binary module that produces the > gEfiSmmPeiSmramMemoryReserveGuid HOB is updated >=20 > Cc: Jiewen Yao > Cc: David Wei > Cc: Mang Guo > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kinney > --- > .../PlatformInitPei/PlatformEarlyInit.c | 147 > ++++++++++++++++++++- > 1 file changed, 143 insertions(+), 4 deletions(-) >=20 > diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c > b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c > index f8ea09a..0db940c 100644 > --- a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c > +++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c > @@ -821,17 +821,156 @@ PlatformEarlyInitEntry ( > EFI_PEI_HOB_POINTERS Hob; > EFI_PLATFORM_CPU_INFO PlatformCpuInfo; > EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock; > + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *NewDescriptorBlock; > + UINTN Index; > + UINTN MaxIndex; > + UINT64 Base; > UINT64 Size; > + UINT64 NewSize; >=20 > // > - // Make sure last SMRAM region is aligned > + // Make sure base and size of the SMRAM region is aligned > // > Hob.Raw =3D GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid); > if (Hob.Raw !=3D NULL) { > DescriptorBlock =3D GET_GUID_HOB_DATA (Hob.Raw); > - Size =3D > DescriptorBlock->Descriptor[DescriptorBlock->NumberOfSmmReservedRegion > s - 1].PhysicalSize; > - Size =3D LShiftU64 (1, HighBitSet64 (Size - 1) + 1); > - > DescriptorBlock->Descriptor[DescriptorBlock->NumberOfSmmReservedRegion > s - 1].PhysicalSize =3D Size; > + DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB\n")); > + for (Index =3D 0; Index < DescriptorBlock->NumberOfSmmReservedRegion= s; > Index++) { > + DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=3D%016lx > Size=3D%016lx State=3D%02x\n", > + Index, > + DescriptorBlock->Descriptor[Index].PhysicalStart, > + DescriptorBlock->Descriptor[Index].PhysicalSize, > + DescriptorBlock->Descriptor[Index].RegionState > + )); > + } > + > + // > + // Find the largest usable range of SMRAM between 1MB and 4GB > + // > + for (Index =3D 0, MaxIndex =3D 0, Size =3D 0; Index < > DescriptorBlock->NumberOfSmmReservedRegions; Index++) { > + // > + // Skip any SMRAM region that is already allocated, needs testing,= or > needs ECC initialization > + // > + if ((DescriptorBlock->Descriptor[Index].RegionState & > (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) !=3D > 0) { > + continue; > + } > + // > + // Skip any SMRAM region below 1MB > + // > + if (DescriptorBlock->Descriptor[Index].CpuStart < BASE_1MB) { > + continue; > + } > + // > + // Skip any SMRAM region that is above 4GB or crosses the 4GB > boundary > + // > + if ((DescriptorBlock->Descriptor[Index].CpuStart + > DescriptorBlock->Descriptor[Index].PhysicalSize) >=3D BASE_4GB) { > + continue; > + } > + // > + // Cache the largest SMRAM region index > + // > + if (DescriptorBlock->Descriptor[Index].PhysicalSize >=3D > DescriptorBlock->Descriptor[MaxIndex].PhysicalSize) { > + MaxIndex =3D Index; > + } > + } > + > + // > + // Find the extent of the contiguous SMRAM region that surrounds the > largest usable SMRAM range > + // > + Base =3D DescriptorBlock->Descriptor[MaxIndex].CpuStart; > + Size =3D DescriptorBlock->Descriptor[MaxIndex].PhysicalSize; > + for (Index =3D 0; Index < DescriptorBlock->NumberOfSmmReservedRegion= s; > Index++) { > + if (DescriptorBlock->Descriptor[Index].CpuStart < Base && > + Base =3D=3D (DescriptorBlock->Descriptor[Index].CpuStart + > DescriptorBlock->Descriptor[Index].PhysicalSize)) { > + Base =3D DescriptorBlock->Descriptor[Index].CpuStart; > + Size +=3D DescriptorBlock->Descriptor[Index].PhysicalSize; > + } else if ((Base + Size) =3D=3D DescriptorBlock->Descriptor[Index]= .CpuStart) > { > + Size +=3D DescriptorBlock->Descriptor[Index].PhysicalSize; > + } > + } > + > + // > + // Round SMRAM region up to nearest power of 2 that is at least 4KB > + // > + NewSize =3D MAX (LShiftU64 (1, HighBitSet64 (Size - 1) + 1), SIZE_4K= B); > + if ((Base & ~(NewSize - 1)) !=3D Base) { > + // > + // SMRAM region Base Address has smaller alignment than SMRAM > region Size > + // This is not compatible with SMRR settings > + // > + DEBUG((DEBUG_ERROR, "ERROR: SMRAM Region Size has larger > alignment than SMRAM Region Base\n")); > + DEBUG((DEBUG_ERROR, " SMRAM Region Base=3D%016lx > Size=3D%016lx\n", Base, NewSize)); > + ASSERT (FALSE); > + } else if (Size !=3D NewSize) { > + // > + // See if the size difference can be added to an adjacent descript= or that > is already allocated > + // > + for (Index =3D 0; Index < > DescriptorBlock->NumberOfSmmReservedRegions; Index++) { > + if ((DescriptorBlock->Descriptor[Index].CpuStart + > DescriptorBlock->Descriptor[Index].PhysicalSize) =3D=3D (Base + Size)) { > + if (((DescriptorBlock->Descriptor[Index].RegionState) & > EFI_ALLOCATED) !=3D 0) { > + DescriptorBlock->Descriptor[Index].PhysicalSize +=3D (NewSiz= e - > Size); > + Size =3D NewSize; > + break; > + } > + } > + } > + > + if (Size !=3D NewSize) { > + // > + // Add an allocated descriptor to the SMM PEI SMRAM Memory > Reserved HOB to accomodate the larger size. > + // > + Index =3D DescriptorBlock->NumberOfSmmReservedRegions; > + NewDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK > *)BuildGuidHob ( > + &gEfiSmmPeiSmramMemoryReserveGuid, > + sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + ((Index + 1) * > sizeof (EFI_SMRAM_DESCRIPTOR)) > + ); > + ASSERT (NewDescriptorBlock !=3D NULL); > + > + // > + // Copy old EFI_SMRAM_HOB_DESCRIPTOR_BLOCK to new > allocated region > + // > + CopyMem ( > + NewDescriptorBlock, > + DescriptorBlock, > + sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (Index * sizeof > (EFI_SMRAM_DESCRIPTOR)) > + ); > + > + // > + // Make sure last descriptor in NewDescriptorBlock contains last > descriptor from DescriptorBlock > + // > + CopyMem ( > + &NewDescriptorBlock->Descriptor[Index], > + &NewDescriptorBlock->Descriptor[Index - 1], > + sizeof (EFI_SMRAM_DESCRIPTOR) > + ); > + > + // > + // Fill next to last descriptor with an allocated descriptor tha= t aligns > the total size of SMRAM > + // > + NewDescriptorBlock->Descriptor[Index - 1].CpuStart =3D Base > + Size; > + NewDescriptorBlock->Descriptor[Index - 1].PhysicalStart =3D Base= + > Size; > + NewDescriptorBlock->Descriptor[Index - 1].PhysicalSize =3D NewS= ize > - Size; > + NewDescriptorBlock->Descriptor[Index - 1].RegionState =3D > DescriptorBlock->Descriptor[MaxIndex].RegionState | EFI_ALLOCATED; > + NewDescriptorBlock->NumberOfSmmReservedRegions++; > + > + // > + // Invalidate the original gEfiSmmPeiSmramMemoryReserveGuid > HOB > + // > + ZeroMem (&Hob.Guid->Name, sizeof (&Hob.Guid->Name)); > + } > + > + Hob.Raw =3D GetFirstGuidHob > (&gEfiSmmPeiSmramMemoryReserveGuid); > + DescriptorBlock =3D GET_GUID_HOB_DATA (Hob.Raw); > + DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB - > Updated\n")); > + for (Index =3D 0; Index < > DescriptorBlock->NumberOfSmmReservedRegions; Index++) { > + DEBUG((DEBUG_INFO, " SMRAM Descriptor[%02x]: Start=3D%016lx > Size=3D%016lx State=3D%02x\n", > + Index, > + DescriptorBlock->Descriptor[Index].PhysicalStart, > + DescriptorBlock->Descriptor[Index].PhysicalSize, > + DescriptorBlock->Descriptor[Index].RegionState > + )); > + } > + } > } >=20 > // > -- > 2.6.3.windows.1