From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 71A0281FAD for ; Thu, 26 Jan 2017 04:17:06 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP; 26 Jan 2017 04:17:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,289,1477983600"; d="scan'208,217";a="1087521039" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga001.jf.intel.com with ESMTP; 26 Jan 2017 04:17:05 -0800 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 26 Jan 2017 04:17:05 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 26 Jan 2017 04:17:05 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0248.002; Thu, 26 Jan 2017 20:17:03 +0800 From: "Yao, Jiewen" To: Leif Lindholm CC: "edk2-devel@lists.01.org" , Ard Biesheuvel , Andrew Fish Thread-Topic: [PATCH 2/3] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage Thread-Index: AQHSd81J7+5cJZE6YUup/V47k+N5faFKrBRw Date: Thu, 26 Jan 2017 12:17:02 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A8E5EC7@shsmsx102.ccr.corp.intel.com> References: <1485419955-26652-1-git-send-email-jiewen.yao@intel.com> <1485419955-26652-3-git-send-email-jiewen.yao@intel.com> <20170126121105.GW25883@bivouac.eciton.net> In-Reply-To: <20170126121105.GW25883@bivouac.eciton.net> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [PATCH 2/3] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2017 12:17:06 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thank you, Leif. You are right. I found I missed some other after I did a global search for = EFI_MEMORY_WP. I will send V2 ARM patch soon. Thank you Yao Jiewen From: Leif Lindholm [mailto:leif.lindholm@linaro.org] Sent: Thursday, January 26, 2017 8:11 PM To: Yao, Jiewen Cc: edk2-devel@lists.01.org; Ard Biesheuvel ; An= drew Fish Subject: Re: [PATCH 2/3] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage On Thu, Jan 26, 2017 at 04:39:14PM +0800, Jiewen Yao wrote: > Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, > according to UEFI spec, we should use EFI_MEMORY_RO for write protection. > The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Hi Jiewen, The change looks sane, given the clarification of the specification, but there are several instances of EFI_MEMORY_WP in comments left around from Andrew Fish's original ARM implementation. I think they should be updated too. Andrew: can you confirm what the below snipped from ArmPkg/Drivers/CpuDxe/Arm/Mmu.c was meant to convey? --- case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; --- Regards, Leif > Cc: Leif Lindholm > > Cc: Ard Biesheuvel > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > > --- > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 2 +- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 5 +---- > 2 files changed, 2 insertions(+), 5 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/= AArch64/Mmu.c > index d8bb419..4703b33 100644 > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > @@ -224,7 +224,7 @@ EfiAttributeToArmAttribute ( > ArmAttributes |=3D TT_AF; > > // Determine protection attributes > - if (EfiAttributes & EFI_MEMORY_WP) { > + if (EfiAttributes & EFI_MEMORY_RO) { > ArmAttributes |=3D TT_AP_RO_RO; > } > > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/= Mmu.c > index 14fc22d..e375cbe 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -730,9 +730,6 @@ EfiAttributeToArmAttribute ( > ArmAttributes =3D TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_AL= LOC; // TEX [2:0] =3D 001, C=3D1, B=3D1 > break; > > - case EFI_MEMORY_WP: > - case EFI_MEMORY_XP: > - case EFI_MEMORY_RP: > case EFI_MEMORY_UCE: > default: > // Cannot be implemented UEFI definition unclear for ARM > @@ -743,7 +740,7 @@ EfiAttributeToArmAttribute ( > } > > // Determine protection attributes > - if (EfiAttributes & EFI_MEMORY_WP) { > + if (EfiAttributes & EFI_MEMORY_RO) { > ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; > } else { > ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; > -- > 2.7.4.windows.1 >