From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3E70A81FAE for ; Thu, 26 Jan 2017 04:38:08 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP; 26 Jan 2017 04:38:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,289,1477983600"; d="scan'208,217";a="1099189809" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga001.fm.intel.com with ESMTP; 26 Jan 2017 04:38:07 -0800 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 26 Jan 2017 04:38:07 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 26 Jan 2017 04:38:06 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.177]) with mapi id 14.03.0248.002; Thu, 26 Jan 2017 20:38:04 +0800 From: "Yao, Jiewen" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: Leif Lindholm , Ard Biesheuvel , "Andrew Fish (afish@apple.com)" Thread-Topic: [edk2] [PATCH V2 2/3] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage Thread-Index: AQHSd9BgEnwe1jlhvU6XQd9tBkr5M6FKsTVA Date: Thu, 26 Jan 2017 12:38:03 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A8E5EEF@shsmsx102.ccr.corp.intel.com> References: <1485433938-6888-1-git-send-email-jiewen.yao@intel.com> In-Reply-To: <1485433938-6888-1-git-send-email-jiewen.yao@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [PATCH V2 2/3] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2017 12:38:08 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Leif Here is 2nd patch. I did a global replace for EFI_MEMORY_WP. I have to send this patch because I updated DxeCore to use EFI_MEMORY_RO an= d EFI_MEMORY_XP for PE image protection. Assuming the original EFI_MEMORY_WP can work, I think this EFI_MEMORY_RO up= date is no harm. But if the original EFI_MEMORY_WP is not validated, this core update has ri= sk. (Such as X86 CPU, we need apply a patch to support EFI_MEMORY_RO.) Is that possible that you help me do a quick validation to check if the Dxe= Core update breaks anything on ARM? Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ji= ewen > Yao > Sent: Thursday, January 26, 2017 8:32 PM > To: edk2-devel@lists.01.org > Cc: Leif Lindholm ; Ard Biesheuvel > > Subject: [edk2] [PATCH V2 2/3] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO > usage > > Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, > according to UEFI spec, we should use EFI_MEMORY_RO for write protection. > The EFI_MEMORY_WP is the cache attribute instead of memory attribute. > > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > --- > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 2 +- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 13 +++++-------- > ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 ++-- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 2 +- > 4 files changed, 9 insertions(+), 12 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > index d8bb419..4703b33 100644 > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > @@ -224,7 +224,7 @@ EfiAttributeToArmAttribute ( > ArmAttributes |=3D TT_AF; > > // Determine protection attributes > - if (EfiAttributes & EFI_MEMORY_WP) { > + if (EfiAttributes & EFI_MEMORY_RO) { > ArmAttributes |=3D TT_AP_RO_RO; > } > > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > index 14fc22d..348b205 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -62,7 +62,7 @@ SectionToGcdAttributes ( > // determine protection attributes > switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { > case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write > - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; > + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; > break; > > case TT_DESCRIPTOR_SECTION_AP_RW_NO: > @@ -73,7 +73,7 @@ SectionToGcdAttributes ( > // read only cases map to write-protect > case TT_DESCRIPTOR_SECTION_AP_RO_NO: > case TT_DESCRIPTOR_SECTION_AP_RO_RO: > - *GcdAttributes |=3D EFI_MEMORY_WP; > + *GcdAttributes |=3D EFI_MEMORY_RO; > break; > > default: > @@ -126,7 +126,7 @@ PageToGcdAttributes ( > // determine protection attributes > switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { > case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write > - //*GcdAttributes |=3D EFI_MEMORY_WP | EFI_MEMORY_RP; > + //*GcdAttributes |=3D EFI_MEMORY_RO | EFI_MEMORY_RP; > break; > > case TT_DESCRIPTOR_PAGE_AP_RW_NO: > @@ -137,7 +137,7 @@ PageToGcdAttributes ( > // read only cases map to write-protect > case TT_DESCRIPTOR_PAGE_AP_RO_NO: > case TT_DESCRIPTOR_PAGE_AP_RO_RO: > - *GcdAttributes |=3D EFI_MEMORY_WP; > + *GcdAttributes |=3D EFI_MEMORY_RO; > break; > > default: > @@ -730,9 +730,6 @@ EfiAttributeToArmAttribute ( > ArmAttributes =3D > TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] =3D > 001, C=3D1, B=3D1 > break; > > - case EFI_MEMORY_WP: > - case EFI_MEMORY_XP: > - case EFI_MEMORY_RP: > case EFI_MEMORY_UCE: > default: > // Cannot be implemented UEFI definition unclear for ARM > @@ -743,7 +740,7 @@ EfiAttributeToArmAttribute ( > } > > // Determine protection attributes > - if (EfiAttributes & EFI_MEMORY_WP) { > + if (EfiAttributes & EFI_MEMORY_RO) { > ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RO_RO; > } else { > ArmAttributes |=3D TT_DESCRIPTOR_SECTION_AP_RW_RW; > diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > index 723604d..acdf1eb 100644 > --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > @@ -236,7 +236,7 @@ CpuConvertPagesToUncachedVirtualAddress ( > // be the PCI address. Code should always use the CPU address, and we = will > or in VirtualMask > // to that address. > // > - Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0); > + Status =3D SetMemoryAttributes (Address, Length, EFI_MEMORY_RO, 0); > if (!EFI_ERROR (Status)) { > Status =3D SetMemoryAttributes (Address | VirtualMask, Length, > EFI_MEMORY_UC, VirtualMask); > } > @@ -264,7 +264,7 @@ CpuReconvertPages ( > // > // Unmap the aliased Address > // > - Status =3D SetMemoryAttributes (Address | VirtualMask, Length, > EFI_MEMORY_WP, 0); > + Status =3D SetMemoryAttributes (Address | VirtualMask, Length, > EFI_MEMORY_RO, 0); > if (!EFI_ERROR (Status)) { > // > // Restore atttributes > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index 540069a..5bc80a6 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -89,7 +89,7 @@ PageAttributeToGcdAttribute ( > // Determine protection attributes > if (((PageAttributes & TT_AP_MASK) =3D=3D TT_AP_NO_RO) || ((PageAttrib= utes > & TT_AP_MASK) =3D=3D TT_AP_RO_RO)) { > // Read only cases map to write-protect > - GcdAttributes |=3D EFI_MEMORY_WP; > + GcdAttributes |=3D EFI_MEMORY_RO; > } > > // Process eXecute Never attribute > -- > 2.7.4.windows.1 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel