From: "Yao, Jiewen" <jiewen.yao@intel.com>
To: "Wu, Hao A" <hao.a.wu@intel.com>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Subject: Re: [PATCH v3 06/12] IntelFspWrapperPkg: Refine casting expression result to bigger size
Date: Sat, 25 Feb 2017 05:51:05 +0000 [thread overview]
Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A8F54AA@shsmsx102.ccr.corp.intel.com> (raw)
In-Reply-To: <1487999555-9764-7-git-send-email-hao.a.wu@intel.com>
Reviewed-by: jiewen.yao@intel.com
> -----Original Message-----
> From: Wu, Hao A
> Sent: Saturday, February 25, 2017 1:12 PM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A <hao.a.wu@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
> Subject: [PATCH v3 06/12] IntelFspWrapperPkg: Refine casting expression result
> to bigger size
>
> There are cases that the operands of an expression are all with rank less
> than UINT64/INT64 and the result of the expression is explicitly cast to
> UINT64/INT64 to fit the target size.
>
> An example will be:
> UINT32 a,b;
> // a and b can be any unsigned int type with rank less than UINT64, like
> // UINT8, UINT16, etc.
> UINT64 c;
> c = (UINT64) (a + b);
>
> Some static code checkers may warn that the expression result might
> overflow within the rank of "int" (integer promotions) and the result is
> then cast to a bigger size.
>
> The commit refines codes by the following rules:
> 1). When the expression is possible to overflow the range of unsigned int/
> int:
> c = (UINT64)a + b;
>
> 2). When the expression will not overflow within the rank of "int", remove
> the explicit type casts:
> c = a + b;
>
> 3). When the expression will be cast to pointer of possible greater size:
> UINT32 a,b;
> VOID *c;
> c = (VOID *)(UINTN)(a + b); --> c = (VOID *)((UINTN)a + b);
>
> 4). When one side of a comparison expression contains only operands with
> rank less than UINT32:
> UINT8 a;
> UINT16 b;
> UINTN c;
> if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...}
>
> For rule 4), if we remove the 'UINTN' type cast like:
> if (a + b > c) {...}
> The VS compiler will complain with warning C4018 (signed/unsigned
> mismatch, level 3 warning) due to promoting 'a + b' to type 'int'.
>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> ---
> IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c | 4 ++--
> IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c | 12 ++++++------
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c
> b/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c
> index 6f06e24..089413c 100644
> --- a/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c
> +++ b/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c
> @@ -1,6 +1,6 @@
> /** @file
>
> -Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
>
> This program and the accompanying materials
> are licensed and made available under the terms and conditions
> @@ -115,7 +115,7 @@ RelocateImageUnder4GIfNeeded (
> // Align buffer on section boundary
> //
> ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;
> - ImageContext.ImageAddress &=
> ~((EFI_PHYSICAL_ADDRESS)(ImageContext.SectionAlignment - 1));
> + ImageContext.ImageAddress &=
> ~((EFI_PHYSICAL_ADDRESS)ImageContext.SectionAlignment - 1);
> //
> // Load the image to our new buffer
> //
> diff --git a/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c
> b/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c
> index 162d244..accd6e4 100644
> --- a/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c
> +++ b/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c
> @@ -1,7 +1,7 @@
> /** @file
> Provide FSP API related function.
>
> - Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at
> @@ -98,7 +98,7 @@ CallFspInit (
> EFI_STATUS Status;
> BOOLEAN InterruptState;
>
> - FspInitApi = (FSP_INIT)(UINTN)(FspHeader->ImageBase +
> FspHeader->FspInitEntryOffset);
> + FspInitApi = (FSP_INIT)((UINTN)FspHeader->ImageBase +
> FspHeader->FspInitEntryOffset);
> InterruptState = SaveAndDisableInterrupts ();
> Status = Execute32BitCode ((UINTN)FspInitApi, (UINTN)FspInitParams);
> SetInterruptState (InterruptState);
> @@ -125,7 +125,7 @@ CallFspNotifyPhase (
> EFI_STATUS Status;
> BOOLEAN InterruptState;
>
> - NotifyPhaseApi = (FSP_NOTIFY_PHASE)(UINTN)(FspHeader->ImageBase +
> FspHeader->NotifyPhaseEntryOffset);
> + NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase +
> FspHeader->NotifyPhaseEntryOffset);
> InterruptState = SaveAndDisableInterrupts ();
> Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
> (UINTN)NotifyPhaseParams);
> SetInterruptState (InterruptState);
> @@ -152,7 +152,7 @@ CallFspMemoryInit (
> EFI_STATUS Status;
> BOOLEAN InterruptState;
>
> - FspMemoryInitApi = (FSP_MEMORY_INIT)(UINTN)(FspHeader->ImageBase +
> FspHeader->FspMemoryInitEntryOffset);
> + FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase +
> FspHeader->FspMemoryInitEntryOffset);
> InterruptState = SaveAndDisableInterrupts ();
> Status = Execute32BitCode ((UINTN)FspMemoryInitApi,
> (UINTN)FspMemoryInitParams);
> SetInterruptState (InterruptState);
> @@ -179,7 +179,7 @@ CallTempRamExit (
> EFI_STATUS Status;
> BOOLEAN InterruptState;
>
> - TempRamExitApi = (FSP_TEMP_RAM_EXIT)(UINTN)(FspHeader->ImageBase
> + FspHeader->TempRamExitEntryOffset);
> + TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase
> + FspHeader->TempRamExitEntryOffset);
> InterruptState = SaveAndDisableInterrupts ();
> Status = Execute32BitCode ((UINTN)TempRamExitApi,
> (UINTN)TempRamExitParam);
> SetInterruptState (InterruptState);
> @@ -206,7 +206,7 @@ CallFspSiliconInit (
> EFI_STATUS Status;
> BOOLEAN InterruptState;
>
> - FspSiliconInitApi = (FSP_SILICON_INIT)(UINTN)(FspHeader->ImageBase +
> FspHeader->FspSiliconInitEntryOffset);
> + FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase +
> FspHeader->FspSiliconInitEntryOffset);
> InterruptState = SaveAndDisableInterrupts ();
> Status = Execute32BitCode ((UINTN)FspSiliconInitApi,
> (UINTN)FspSiliconInitParam);
> SetInterruptState (InterruptState);
> --
> 1.9.5.msysgit.0
next prev parent reply other threads:[~2017-02-25 5:51 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-25 5:12 [PATCH v3 00/12] Refine casting expression result to bigger size Hao Wu
2017-02-25 5:12 ` [PATCH v3 01/12] MdePkg: " Hao Wu
2017-02-25 5:12 ` [PATCH v3 02/12] MdeModulePkg: " Hao Wu
2017-03-06 1:37 ` Tian, Feng
2017-02-25 5:12 ` [PATCH v3 03/12] FatPkg: " Hao Wu
2017-02-27 5:07 ` Ni, Ruiyu
2017-02-25 5:12 ` [PATCH v3 04/12] IntelFrameworkModulePkg: " Hao Wu
2017-02-27 7:06 ` Fan, Jeff
2017-02-25 5:12 ` [PATCH v3 05/12] IntelFsp2WrapperPkg: " Hao Wu
2017-02-25 5:51 ` Yao, Jiewen
2017-02-25 5:12 ` [PATCH v3 06/12] IntelFspWrapperPkg: " Hao Wu
2017-02-25 5:51 ` Yao, Jiewen [this message]
2017-02-25 5:12 ` [PATCH v3 07/12] NetworkPkg: " Hao Wu
2017-02-27 2:21 ` Wu, Jiaxin
2017-02-25 5:12 ` [PATCH v3 08/12] PcAtChipsetPkg: " Hao Wu
2017-02-27 7:24 ` Ni, Ruiyu
2017-02-25 5:12 ` [PATCH v3 09/12] SecurityPkg/Opal: " Hao Wu
2017-03-06 1:40 ` Dong, Eric
2017-02-25 5:12 ` [PATCH v3 10/12] ShellPkg: " Hao Wu
2017-02-27 2:22 ` Ni, Ruiyu
2017-02-27 16:38 ` Carsey, Jaben
2017-02-25 5:12 ` [PATCH v3 11/12] SourceLevelDebugPkg: " Hao Wu
2017-02-27 7:27 ` Fan, Jeff
2017-02-25 5:12 ` [PATCH v3 12/12] UefiCpuPkg: " Hao Wu
2017-02-27 7:27 ` Fan, Jeff
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