From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 02D7782156 for ; Fri, 24 Feb 2017 21:51:20 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2017 21:51:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,202,1484035200"; d="scan'208";a="828285876" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2017 21:51:20 -0800 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 24 Feb 2017 21:51:20 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 24 Feb 2017 21:51:20 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.177]) with mapi id 14.03.0248.002; Sat, 25 Feb 2017 13:51:09 +0800 From: "Yao, Jiewen" To: "Wu, Hao A" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH v3 05/12] IntelFsp2WrapperPkg: Refine casting expression result to bigger size Thread-Index: AQHSjyXZXrRbAaPVpUC6gXzeZIvjF6F5OARw Date: Sat, 25 Feb 2017 05:51:09 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A8F54B9@shsmsx102.ccr.corp.intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> <1487999555-9764-6-git-send-email-hao.a.wu@intel.com> In-Reply-To: <1487999555-9764-6-git-send-email-hao.a.wu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 05/12] IntelFsp2WrapperPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 25 Feb 2017 05:51:21 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: jiewen.yao@intel.com > -----Original Message----- > From: Wu, Hao A > Sent: Saturday, February 25, 2017 1:12 PM > To: edk2-devel@lists.01.org > Cc: Wu, Hao A ; Yao, Jiewen > Subject: [PATCH v3 05/12] IntelFsp2WrapperPkg: Refine casting expression = result > to bigger size >=20 > There are cases that the operands of an expression are all with rank less > than UINT64/INT64 and the result of the expression is explicitly cast to > UINT64/INT64 to fit the target size. >=20 > An example will be: > UINT32 a,b; > // a and b can be any unsigned int type with rank less than UINT64, like > // UINT8, UINT16, etc. > UINT64 c; > c =3D (UINT64) (a + b); >=20 > Some static code checkers may warn that the expression result might > overflow within the rank of "int" (integer promotions) and the result is > then cast to a bigger size. >=20 > The commit refines codes by the following rules: > 1). When the expression is possible to overflow the range of unsigned int= / > int: > c =3D (UINT64)a + b; >=20 > 2). When the expression will not overflow within the rank of "int", remov= e > the explicit type casts: > c =3D a + b; >=20 > 3). When the expression will be cast to pointer of possible greater size: > UINT32 a,b; > VOID *c; > c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); >=20 > 4). When one side of a comparison expression contains only operands with > rank less than UINT32: > UINT8 a; > UINT16 b; > UINTN c; > if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} >=20 > For rule 4), if we remove the 'UINTN' type cast like: > if (a + b > c) {...} > The VS compiler will complain with warning C4018 (signed/unsigned > mismatch, level 3 warning) due to promoting 'a + b' to type 'int'. >=20 > Cc: Jiewen Yao > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Hao Wu > --- > IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c | > 4 ++-- > IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c | 10 > +++++----- > 2 files changed, 7 insertions(+), 7 deletions(-) >=20 > diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c > b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c > index ff2f563..dc5ef89 100644 > --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c > +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/LoadBelow4G.c > @@ -1,6 +1,6 @@ > /** @file >=20 > -Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> +Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
>=20 > This program and the accompanying materials > are licensed and made available under the terms and conditions > @@ -115,7 +115,7 @@ RelocateImageUnder4GIfNeeded ( > // Align buffer on section boundary > // > ImageContext.ImageAddress +=3D ImageContext.SectionAlignment - 1; > - ImageContext.ImageAddress &=3D > ~((EFI_PHYSICAL_ADDRESS)(ImageContext.SectionAlignment - 1)); > + ImageContext.ImageAddress &=3D > ~((EFI_PHYSICAL_ADDRESS)ImageContext.SectionAlignment - 1); > // > // Load the image to our new buffer > // > diff --git > a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c > b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c > index 8cf136f..38de415 100644 > --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c > +++ > b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c > @@ -1,7 +1,7 @@ > /** @file > Provide FSP API related function. >=20 > - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at > @@ -99,7 +99,7 @@ CallFspNotifyPhase ( > return EFI_DEVICE_ERROR; > } >=20 > - NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)(UINTN)(FspHeader->ImageBase + > FspHeader->NotifyPhaseEntryOffset); > + NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + > FspHeader->NotifyPhaseEntryOffset); > InterruptState =3D SaveAndDisableInterrupts (); > Status =3D Execute32BitCode ((UINTN)NotifyPhaseApi, > (UINTN)NotifyPhaseParams, (UINTN)NULL); > SetInterruptState (InterruptState); > @@ -132,7 +132,7 @@ CallFspMemoryInit ( > return EFI_DEVICE_ERROR; > } >=20 > - FspMemoryInitApi =3D (FSP_MEMORY_INIT)(UINTN)(FspHeader->ImageBase + > FspHeader->FspMemoryInitEntryOffset); > + FspMemoryInitApi =3D (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + > FspHeader->FspMemoryInitEntryOffset); > InterruptState =3D SaveAndDisableInterrupts (); > Status =3D Execute32BitCode ((UINTN)FspMemoryInitApi, > (UINTN)FspmUpdDataPtr, (UINTN)HobListPtr); > SetInterruptState (InterruptState); > @@ -163,7 +163,7 @@ CallTempRamExit ( > return EFI_DEVICE_ERROR; > } >=20 > - TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)(UINTN)(FspHeader->ImageBase > + FspHeader->TempRamExitEntryOffset); > + TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase > + FspHeader->TempRamExitEntryOffset); > InterruptState =3D SaveAndDisableInterrupts (); > Status =3D Execute32BitCode ((UINTN)TempRamExitApi, > (UINTN)TempRamExitParam, (UINTN)NULL); > SetInterruptState (InterruptState); > @@ -194,7 +194,7 @@ CallFspSiliconInit ( > return EFI_DEVICE_ERROR; > } >=20 > - FspSiliconInitApi =3D (FSP_SILICON_INIT)(UINTN)(FspHeader->ImageBase + > FspHeader->FspSiliconInitEntryOffset); > + FspSiliconInitApi =3D (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + > FspHeader->FspSiliconInitEntryOffset); > InterruptState =3D SaveAndDisableInterrupts (); > Status =3D Execute32BitCode ((UINTN)FspSiliconInitApi, > (UINTN)FspsUpdDataPtr, (UINTN)NULL); > SetInterruptState (InterruptState); > -- > 1.9.5.msysgit.0