From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0065E21A18AAA for ; Mon, 27 Mar 2017 18:40:37 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP; 27 Mar 2017 18:40:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,234,1486454400"; d="scan'208,217";a="81278074" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga005.fm.intel.com with ESMTP; 27 Mar 2017 18:40:37 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 18:40:37 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 18:40:37 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.212]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.82]) with mapi id 14.03.0248.002; Tue, 28 Mar 2017 09:40:33 +0800 From: "Yao, Jiewen" To: "Duran, Leo" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Singh, Brijesh" Thread-Topic: [RFC] [PATCH 0/3] Add IOMMU support. Thread-Index: AQHSpzNqnOYLD0s+1UWqSZtZeyjIoqGpePFA Date: Tue, 28 Mar 2017 01:40:32 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A914BF3@shsmsx102.ccr.corp.intel.com> References: <1490434122-16200-1-git-send-email-jiewen.yao@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: [RFC] [PATCH 0/3] Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Mar 2017 01:40:38 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Leo I do intercept 4 I/O operation in *PciIo*, instead of *PciRootBridgeIo*. See: https://lists.01.org/pipermail/edk2-devel/2017-March/009021.html There are 4 gIoMmuProtocol->SetAttribute() I believe you can clear/set SEV = action there. Would you please double check that? Thank you Yao Jiewen From: Duran, Leo [mailto:leo.duran@amd.com] Sent: Tuesday, March 28, 2017 3:51 AM To: Yao, Jiewen ; edk2-devel@lists.01.org Cc: Ni, Ruiyu ; Singh, Brijesh Subject: RE: [RFC] [PATCH 0/3] Add IOMMU support. Hi Yao, This patch-set, in its current form, does not address all of the required S= EV functionality for PcIHostBridgeIo. Basically, we need to intercept all 4 I/O Operations: - IoMap() - IoUnmap() - IoAllocateBuffer() - IoFreeBuffer() SEV I/O intercepts would do this: 1) IoMap() - Allocate an accessible bounce buffer (AllocateType depends on consumer's = capabilities). - Clear SEV mask on retuned mapped DMA buffer - On DMA Read: CopyMem() from consumer buffer to mapped buffer (bounce oper= ation) 2) IoUnmap() - On DMA Write: CopyMem() from mapped buffer to consumer buffer (bounce ope= ration) - Restore SEV mask on mapped DMA buffer 3) IoAllocateBuffer() - Allocate an accessible buffer (AllocateType depends on consumer's capabil= ities). - Clear SEV mask on allocated buffer - return allocated buffer 4) IoFreeBuffer() - Restore SEV mask on allocated buffer - Free allocated buffer For an sample on how we've intercepted BmDmaLib operations, please refer to= the patch-sets posted by Brijesh: https://lists.01.org/pipermail/edk2-devel/2017-March/008838.html https://lists.01.org/pipermail/edk2-devel/2017-March/008840.html Thanks, Leo > -----Original Message----- > From: Jiewen Yao [mailto:jiewen.yao@intel.com] > Sent: Saturday, March 25, 2017 4:29 AM > To: edk2-devel@lists.01.org > Cc: Ruiyu Ni >; Duran, Leo = >; > Singh, Brijesh > > Subject: [RFC] [PATCH 0/3] Add IOMMU support. > > This patch series adds IOMMU protocol and updates the consumer to > support IOMMU based DMA access in UEFI. > > This patch series can support the BmDmaLib request for AMD SEV. > submitted by Duran, Leo > and= Brijesh Singh > >. > https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and > https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html. > We can have an AMD SEV specific IOMMU driver to produce IOMMU > protocol, and clear SEV in IOMMU->SetAttribute(). > > This patch series can also support Intel VTd based DMA protection, > requested by Jiewen Yao >, discussed in > https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html. > We can have an Intel VTd specific IOMMU driver to produce IOMMU > protocol, and update VTd engine to grant or deny access in IOMMU- > >SetAttribute(). > > This patch series does not provide a full Intel VTd driver, which will be > provide in other patch in the future. > > The purpose of this patch series to review if this IOMMU protocol design = can > meet all DMA access and management requirement. > > Cc: Ruiyu Ni > > Cc: Leo Duran > > Cc: Brijesh Singh > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > > > > Jiewen Yao (3): > MdeModulePkg/Include: Add IOMMU protocol definition. > MdeModulePkg/PciHostBridge: Add IOMMU support. > MdeModulePkg/PciBus: Add IOMMU support. > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 12 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 10 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 100 +++++++= +++++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 3 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 7 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 172 > +++++++++++++++++++- > MdeModulePkg/Include/Protocol/IoMmu.h | 132 > +++++++++++++++ > MdeModulePkg/MdeModulePkg.dec | 3 + > 10 files changed, 436 insertions(+), 5 deletions(-) create mode 100644 > MdeModulePkg/Include/Protocol/IoMmu.h > > -- > 2.7.4.windows.1