From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2346121A134BF for ; Tue, 2 May 2017 18:16:39 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP; 02 May 2017 18:16:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,281,1491289200"; d="scan'208,217";a="81751732" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 02 May 2017 18:16:38 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 2 May 2017 18:16:38 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 2 May 2017 18:16:37 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.246]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Wed, 3 May 2017 09:16:36 +0800 From: "Yao, Jiewen" To: Brijesh Singh , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , Leo Duran , "Ard Biesheuvel" Thread-Topic: [RFC] [PATCH V4 0/3] Add IOMMU support. Thread-Index: AQHSw4hoQQ6RtS0U4kOi+KISlm6ZoaHhzq0w Date: Wed, 3 May 2017 01:16:35 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A936C98@shsmsx102.ccr.corp.intel.com> References: <1493473882-7336-1-git-send-email-jiewen.yao@intel.com> <5e873437-0ba3-46ce-71cb-9e6ef0cf3811@amd.com> In-Reply-To: <5e873437-0ba3-46ce-71cb-9e6ef0cf3811@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: [RFC] [PATCH V4 0/3] Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 03 May 2017 01:16:39 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Awesome. Thank you! From: Brijesh Singh [mailto:brijesh.singh@amd.com] Sent: Wednesday, May 3, 2017 5:09 AM To: Yao, Jiewen ; edk2-devel@lists.01.org Cc: brijesh.singh@amd.com; Ni, Ruiyu ; Leo Duran ; Ard Biesheuvel Subject: Re: [RFC] [PATCH V4 0/3] Add IOMMU support. Hi Yao, On 04/29/2017 08:51 AM, Jiewen Yao wrote: > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V4 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > Refine the EDKII_IOMMU_PROTOCOL. > > 1) Add AllocateBuffer/FreeBuffer/Map/Unmap() API. > They are similar to DmaLib in EmbeddedPkg and > similar to the previous BmDmaLib (by leo.duran@amd.com). > > These APIs are invoked by PciHostBridge driver > to allocate DMA memory. > > The PciHostBridge driver (IOMMU consumer) is simplified: > It uses IOMMU, if IOMMU protocol is present. > Else it uses original logic. > > 2) Add SetMappingAttribute() API. > It is similar to SetAttribute() API in V1. > > This API is invoked by PciBus driver to set DMA > access attribute (read/write) for device. > > The PciBus driver (IOMMU consumer) is simplified: > It sets access attribute in Map/Unmap, > if IOMMU protocol is present. > > 3) Remove SetRemapAddress/GetRemapAddress() API. > Because PciHostBridge/PciBus can call the APIs defined > above, there is no need to provide remap capability. > > -- Sample producer drivers: > 1) The sample VTd driver (IOMMU producer) > is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/IntelVTdD= xe > > It is added to show the concept. It is not fully implemented yet. > It will not be checked in in this patch. > > 2) The sample AMD SEV driver (IOMMU producer) > is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleAmd= SevDxe > (code is borrowed from leo.duran@amd.com and br= ijesh.singh@amd.com) > > This is not a right place to put this driver. > I have reworked my SEV patch series to produce the IOMMU protocol (very sim= ilar to SampleAmdSevDxe) when SEV is enabled. The model seems to work just fine. I am able to perfor= m the DMA operations inside the SEV guest. Thank you for the work. Tested-by: Brijesh Singh > > It is added to show the concept. > It is not fully implemented. It will not be checked in. > Please do not use it directly. > > 3) The sample STYX driver (IOMMU producer) > is at https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleSty= xDxe > (code is borrowed from ard.biesheuvel@linaro.org) > > This is not a right place to put this driver. > > It is added to show the concept. > It is not fully implemented. It will not be checked in. > Please do not use it directly. > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V3 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > 1) Add Remap capability (from Ard Biesheuvel) > Add EDKII_IOMMU_REMAP_ADDRESS API in IOMMU_PROTOCOL. > > NOTE: The code is not fully validated yet. > The purpose is to collect feedback to decide the next step. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V2 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > 1) Enhance Unmap() in PciIo (From Ruiyu Ni) > Maintain a local list of MapInfo and match it in Unmap. > > 2) CopyMem for ReadOperation in PciIo after SetAttribute (Leo Duran) > Fix a bug in V1 that copy mem for read happen before SetAttribute, > which will break AMD SEV solution. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V1 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > > This patch series adds IOMMU protocol and updates the consumer > to support IOMMU based DMA access in UEFI. > > This patch series can support the BmDmaLib request for AMD SEV. > submitted by Duran, Leo > and= Brijesh Singh >. > https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and > https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html. > We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol, > and clear SEV in IOMMU->SetAttribute(). > > This patch series can also support Intel VTd based DMA protection, > requested by Jiewen Yao >, discussed in > https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html. > We can have an Intel VTd specific IOMMU driver to produce IOMMU protocol, > and update VTd engine to grant or deny access in IOMMU->SetAttribute(). > > This patch series does not provide a full Intel VTd driver, which > will be provide in other patch in the future. > > The purpose of this patch series to review if this IOMMU protocol design > can meet all DMA access and management requirement. > > Cc: Ruiyu Ni > > Cc: Leo Duran > > Cc: Brijesh Singh > > Cc: Ard Biesheuvel > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > > > Jiewen Yao (3): > MdeModulePkg/Include: Add IOMMU protocol definition. > MdeModulePkg/PciHostBridge: Add IOMMU support. > MdeModulePkg/PciBus: Add IOMMU support. > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 9 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 37 +++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 37 +++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 2 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 2 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 61 ++++ > MdeModulePkg/Include/Protocol/IoMmu.h | 310 +++++++= +++++++++++++ > MdeModulePkg/MdeModulePkg.dec | 3 + > 10 files changed, 463 insertions(+) > create mode 100644 MdeModulePkg/Include/Protocol/IoMmu.h >