From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0930021962321 for ; Mon, 12 Jun 2017 23:41:52 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jun 2017 23:43:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,337,1493708400"; d="scan'208";a="1181709598" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga002.fm.intel.com with ESMTP; 12 Jun 2017 23:43:05 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 12 Jun 2017 23:43:04 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 12 Jun 2017 23:43:04 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.122]) with mapi id 14.03.0319.002; Tue, 13 Jun 2017 14:43:02 +0800 From: "Yao, Jiewen" To: "Fan, Jeff" , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" Thread-Topic: [PATCH] UefiCpuPkg/SmmCpuFeatureLib: Add more CPU ID for SmmFeatureControl. Thread-Index: AQHS5AZX8aDEBfrMOEee0+kuSOcfW6IiWIPg Date: Tue, 13 Jun 2017 06:43:02 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A96868D@shsmsx102.ccr.corp.intel.com> References: <1497233616-25564-1-git-send-email-jiewen.yao@intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4C609152@shsmsx102.ccr.corp.intel.com> In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4C609152@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/SmmCpuFeatureLib: Add more CPU ID for SmmFeatureControl. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jun 2017 06:41:52 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Sure, I will send V2 patch soon. > -----Original Message----- > From: Fan, Jeff > Sent: Tuesday, June 13, 2017 1:32 PM > To: Yao, Jiewen ; edk2-devel@lists.01.org > Cc: Kinney, Michael D > Subject: RE: [PATCH] UefiCpuPkg/SmmCpuFeatureLib: Add more CPU ID for > SmmFeatureControl. >=20 > Jiewen, >=20 > Besides you added ModelId, we still have the following ModelId support SM= M > Code Access Check feature in IA32 SDM. >=20 > Processor: ModelId > Goldmont 0x5C > HaswellE 0x3F > XeonD 0x4F, 0x56 > XeonPhi 0x57 >=20 > Could you also add them into your patch? >=20 > Thank! > Jeff >=20 > -----Original Message----- > From: Yao, Jiewen > Sent: Monday, June 12, 2017 10:14 AM > To: edk2-devel@lists.01.org > Cc: Fan, Jeff; Kinney, Michael D > Subject: [PATCH] UefiCpuPkg/SmmCpuFeatureLib: Add more CPU ID for > SmmFeatureControl. >=20 > Add more CPU ID which can support SmmFeatureControl, according to IA32 SD= M. >=20 > Cc: Jeff Fan > Cc: Michael Kinney > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > --- > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > index 079baa4..b0c442e 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > @@ -296,7 +296,8 @@ SmmCpuFeaturesInitializeProcessor ( > // Intel(R) Core(TM) Processor Family MSRs. > // > if (FamilyId =3D=3D 0x06) { > - if (ModelId =3D=3D 0x3C || ModelId =3D=3D 0x45 || ModelId =3D=3D 0x4= 6) { > + if (ModelId =3D=3D 0x3C || ModelId =3D=3D 0x45 || ModelId =3D=3D 0x4= 6 || > + ModelId =3D=3D 0x3D || ModelId =3D=3D 0x47 || ModelId =3D=3D 0x4= E || > + ModelId =3D=3D 0x4F) { > // > // Check to see if the CPU supports the SMM Code Access Check feat= ure > // Do not access this MSR unless the CPU supports the > SmmRegFeatureControl > -- > 2.7.4.windows.1