From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E842021D491BD for ; Thu, 10 Aug 2017 17:17:31 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP; 10 Aug 2017 17:19:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,355,1498546800"; d="scan'208";a="1181515307" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 10 Aug 2017 17:19:51 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 10 Aug 2017 17:19:51 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.183]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.114]) with mapi id 14.03.0319.002; Fri, 11 Aug 2017 08:19:49 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] IntelSiliconPkg: Fix VS2015 NOOPT IA32 build failure in IntelVTdDxe Thread-Index: AQHTEakXXOL5eLPRdE2EHfM0Gy2NP6J+S7Sg Date: Fri, 11 Aug 2017 00:19:48 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A98FA9E@shsmsx102.ccr.corp.intel.com> References: <1502349500-90056-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1502349500-90056-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelSiliconPkg: Fix VS2015 NOOPT IA32 build failure in IntelVTdDxe X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Aug 2017 00:17:32 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Zeng, Star > Sent: Thursday, August 10, 2017 3:18 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Yao, Jiewen > Subject: [PATCH] IntelSiliconPkg: Fix VS2015 NOOPT IA32 build failure in > IntelVTdDxe >=20 > There are VS2015 NOOPT IA32 build failure like below in IntelVTdDxe. > XXX.lib(XXX.obj) : error LNK2001: unresolved external symbol __allshl > XXX.lib(XXX.obj) : error LNK2001: unresolved external symbol __aullshr >=20 > This patch is to update Vtd.h to use UINT32 instead of UINT64 for > bitfields in structure definition, and also update IntelVTdDxe code > accordingly. >=20 > Cc: Jiewen Yao > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Star Zeng > --- > IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 225 > ++++++++++++----------- > IntelSiliconPkg/IntelVTdDxe/DmaProtection.h | 2 + > IntelSiliconPkg/IntelVTdDxe/PciInfo.c | 4 +- > IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 39 ++-- > IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c | 12 +- > IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 2 +- > 6 files changed, 152 insertions(+), 132 deletions(-) >=20 > diff --git a/IntelSiliconPkg/Include/IndustryStandard/Vtd.h > b/IntelSiliconPkg/Include/IndustryStandard/Vtd.h > index 5c6a494eae34..3b7012c5a576 100644 > --- a/IntelSiliconPkg/Include/IndustryStandard/Vtd.h > +++ b/IntelSiliconPkg/Include/IndustryStandard/Vtd.h > @@ -26,9 +26,10 @@ >=20 > typedef union { > struct { > - UINT64 Present:1; > - UINT64 Reserved_1:11; > - UINT64 ContextTablePointer:52; > + UINT32 Present:1; > + UINT32 Reserved_1:11; > + UINT32 ContextTablePointerLo:20; > + UINT32 ContextTablePointerHi:32; >=20 > UINT64 Reserved_64; > } Bits; > @@ -40,13 +41,15 @@ typedef union { >=20 > typedef union { > struct { > - UINT64 LowerPresent:1; > - UINT64 Reserved_1:11; > - UINT64 LowerContextTablePointer:52; > - > - UINT64 UpperPresent:1; > - UINT64 Reserved_65:11; > - UINT64 UpperContextTablePointer:52; > + UINT32 LowerPresent:1; > + UINT32 Reserved_1:11; > + UINT32 LowerContextTablePointerLo:20; > + UINT32 LowerContextTablePointerHi:32; > + > + UINT32 UpperPresent:1; > + UINT32 Reserved_65:11; > + UINT32 UpperContextTablePointerLo:20; > + UINT32 UpperContextTablePointerHi:32; > } Bits; > struct { > UINT64 Uint64Lo; > @@ -56,17 +59,19 @@ typedef union { >=20 > typedef union { > struct { > - UINT64 Present:1; > - UINT64 FaultProcessingDisable:1; > - UINT64 TranslationType:2; > - UINT64 Reserved_4:8; > - UINT64 SecondLevelPageTranslationPointer:52; > - > - UINT64 AddressWidth:3; > - UINT64 Ignored_67:4; > - UINT64 Reserved_71:1; > - UINT64 DomainIdentifier:16; > - UINT64 Reserved_88:40; > + UINT32 Present:1; > + UINT32 FaultProcessingDisable:1; > + UINT32 TranslationType:2; > + UINT32 Reserved_4:8; > + UINT32 SecondLevelPageTranslationPointerLo:20; > + UINT32 SecondLevelPageTranslationPointerHi:32; > + > + UINT32 AddressWidth:3; > + UINT32 Ignored_67:4; > + UINT32 Reserved_71:1; > + UINT32 DomainIdentifier:16; > + UINT32 Reserved_88:8; > + UINT32 Reserved_96:32; > } Bits; > struct { > UINT64 Uint64Lo; > @@ -76,51 +81,54 @@ typedef union { >=20 > typedef union { > struct { > - UINT64 Present:1; > - UINT64 FaultProcessingDisable:1; > - UINT64 TranslationType:3; > - UINT64 ExtendedMemoryType:3; > - UINT64 DeferredInvalidateEnable:1; > - UINT64 PageRequestEnable:1; > - UINT64 NestedTranslationEnable:1; > - UINT64 PASIDEnable:1; > - UINT64 SecondLevelPageTranslationPointer:52; > - > - UINT64 AddressWidth:3; > - UINT64 PageGlobalEnable:1; > - UINT64 NoExecuteEnable:1; > - UINT64 WriteProtectEnable:1; > - UINT64 CacheDisable:1; > - UINT64 ExtendedMemoryTypeEnable:1; > - UINT64 DomainIdentifier:16; > - UINT64 SupervisorModeExecuteProtection:1; > - UINT64 ExtendedAccessedFlagEnable:1; > - UINT64 ExecuteRequestsEnable:1; > - UINT64 SecondLevelExecuteEnable:1; > - UINT64 Reserved_92:4; > - UINT64 PageAttributeTable0:3; > - UINT64 Reserved_Pat0:1; > - UINT64 PageAttributeTable1:3; > - UINT64 Reserved_Pat1:1; > - UINT64 PageAttributeTable2:3; > - UINT64 Reserved_Pat2:1; > - UINT64 PageAttributeTable3:3; > - UINT64 Reserved_Pat3:1; > - UINT64 PageAttributeTable4:3; > - UINT64 Reserved_Pat4:1; > - UINT64 PageAttributeTable5:3; > - UINT64 Reserved_Pat5:1; > - UINT64 PageAttributeTable6:3; > - UINT64 Reserved_Pat6:1; > - UINT64 PageAttributeTable7:3; > - UINT64 Reserved_Pat7:1; > - > - UINT64 PASIDTableSize:4; > - UINT64 Reserved_132:8; > - UINT64 PASIDTablePointer:52; > - > - UINT64 Reserved_192:12; > - UINT64 PASIDStateTablePointer:52; > + UINT32 Present:1; > + UINT32 FaultProcessingDisable:1; > + UINT32 TranslationType:3; > + UINT32 ExtendedMemoryType:3; > + UINT32 DeferredInvalidateEnable:1; > + UINT32 PageRequestEnable:1; > + UINT32 NestedTranslationEnable:1; > + UINT32 PASIDEnable:1; > + UINT32 SecondLevelPageTranslationPointerLo:20; > + UINT32 SecondLevelPageTranslationPointerHi:32; > + > + UINT32 AddressWidth:3; > + UINT32 PageGlobalEnable:1; > + UINT32 NoExecuteEnable:1; > + UINT32 WriteProtectEnable:1; > + UINT32 CacheDisable:1; > + UINT32 ExtendedMemoryTypeEnable:1; > + UINT32 DomainIdentifier:16; > + UINT32 SupervisorModeExecuteProtection:1; > + UINT32 ExtendedAccessedFlagEnable:1; > + UINT32 ExecuteRequestsEnable:1; > + UINT32 SecondLevelExecuteEnable:1; > + UINT32 Reserved_92:4; > + UINT32 PageAttributeTable0:3; > + UINT32 Reserved_Pat0:1; > + UINT32 PageAttributeTable1:3; > + UINT32 Reserved_Pat1:1; > + UINT32 PageAttributeTable2:3; > + UINT32 Reserved_Pat2:1; > + UINT32 PageAttributeTable3:3; > + UINT32 Reserved_Pat3:1; > + UINT32 PageAttributeTable4:3; > + UINT32 Reserved_Pat4:1; > + UINT32 PageAttributeTable5:3; > + UINT32 Reserved_Pat5:1; > + UINT32 PageAttributeTable6:3; > + UINT32 Reserved_Pat6:1; > + UINT32 PageAttributeTable7:3; > + UINT32 Reserved_Pat7:1; > + > + UINT32 PASIDTableSize:4; > + UINT32 Reserved_132:8; > + UINT32 PASIDTablePointerLo:20; > + UINT32 PASIDTablePointerHi:32; > + > + UINT32 Reserved_192:12; > + UINT32 PASIDStateTablePointerLo:20; > + UINT32 PASIDStateTablePointerHi:32; > } Bits; > struct { > UINT64 Uint64_1; > @@ -132,63 +140,66 @@ typedef union { >=20 > typedef union { > struct { > - UINT64 Present:1; > - UINT64 Reserved_1:2; > - UINT64 PageLevelCacheDisable:1; > - UINT64 PageLevelWriteThrough:1; > - UINT64 Reserved_5:6; > - UINT64 SupervisorRequestsEnable:1; > - UINT64 FirstLevelPageTranslationPointer:52; > + UINT32 Present:1; > + UINT32 Reserved_1:2; > + UINT32 PageLevelCacheDisable:1; > + UINT32 PageLevelWriteThrough:1; > + UINT32 Reserved_5:6; > + UINT32 SupervisorRequestsEnable:1; > + UINT32 FirstLevelPageTranslationPointerLo:20; > + UINT32 FirstLevelPageTranslationPointerHi:32; > } Bits; > UINT64 Uint64; > } VTD_PASID_ENTRY; >=20 > typedef union { > struct { > - UINT64 Reserved_0:32; > - UINT64 ActiveReferenceCount:16; > - UINT64 Reserved_48:15; > - UINT64 DeferredInvalidate:1; > + UINT32 Reserved_0:32; > + UINT32 ActiveReferenceCount:16; > + UINT32 Reserved_48:15; > + UINT32 DeferredInvalidate:1; > } Bits; > UINT64 Uint64; > } VTD_PASID_STATE_ENTRY; >=20 > typedef union { > struct { > - UINT64 Present:1; > - UINT64 ReadWrite:1; > - UINT64 UserSupervisor:1; > - UINT64 PageLevelWriteThrough:1; > - UINT64 PageLevelCacheDisable:1; > - UINT64 Accessed:1; > - UINT64 Dirty:1; > - UINT64 PageSize:1; // It is PageAttribute:1 for 4K page entry > - UINT64 Global:1; > - UINT64 Ignored_9:1; > - UINT64 ExtendedAccessed:1; > - UINT64 Ignored_11:1; > + UINT32 Present:1; > + UINT32 ReadWrite:1; > + UINT32 UserSupervisor:1; > + UINT32 PageLevelWriteThrough:1; > + UINT32 PageLevelCacheDisable:1; > + UINT32 Accessed:1; > + UINT32 Dirty:1; > + UINT32 PageSize:1; // It is PageAttribute:1 for 4K page entry > + UINT32 Global:1; > + UINT32 Ignored_9:1; > + UINT32 ExtendedAccessed:1; > + UINT32 Ignored_11:1; > // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M = page > entry > - UINT64 Address:40; > - UINT64 Ignored_52:11; > - UINT64 ExecuteDisable:1; > + UINT32 AddressLo:20; > + UINT32 AddressHi:20; > + UINT32 Ignored_52:11; > + UINT32 ExecuteDisable:1; > } Bits; > UINT64 Uint64; > } VTD_FIRST_LEVEL_PAGING_ENTRY; >=20 > typedef union { > struct { > - UINT64 Read:1; > - UINT64 Write:1; > - UINT64 Execute:1; > - UINT64 ExtendedMemoryType:3; > - UINT64 IgnorePAT:1; > - UINT64 PageSize:1; > - UINT64 Ignored_8:3; > - UINT64 Snoop:1; > - UINT64 Address:40; > - UINT64 Ignored_52:10; > - UINT64 TransientMapping:1; > - UINT64 Ignored_63:1; > + UINT32 Read:1; > + UINT32 Write:1; > + UINT32 Execute:1; > + UINT32 ExtendedMemoryType:3; > + UINT32 IgnorePAT:1; > + UINT32 PageSize:1; > + UINT32 Ignored_8:3; > + UINT32 Snoop:1; > + UINT32 AddressLo:20; > + UINT32 AddressHi:20; > + UINT32 Ignored_52:10; > + UINT32 TransientMapping:1; > + UINT32 Ignored_63:1; > } Bits; > UINT64 Uint64; > } VTD_SECOND_LEVEL_PAGING_ENTRY; > @@ -299,7 +310,6 @@ typedef union { > UINT32 NWFS:1; // No Write Flag Support > UINT32 EAFS:1; // Extended Accessed Flag Support > UINT32 PSS:5; // PASID Size Supported > - > UINT32 Rsvd_40:24; > } Bits; > UINT64 Uint64; > @@ -307,8 +317,9 @@ typedef union { >=20 > typedef union { > struct { > - UINT64 Rsvd_0:12; > - UINT64 FI:52; // FaultInfo > + UINT32 Rsvd_0:12; > + UINT32 FILo:20; // FaultInfo > + UINT32 FIHi:32; // FaultInfo >=20 > UINT32 SID:16; // Source Identifier > UINT32 Rsvd_80:13; > diff --git a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h > b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h > index 6efed6e555d1..8cfa69cb2364 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h > +++ b/IntelSiliconPkg/IntelVTdDxe/DmaProtection.h > @@ -41,6 +41,8 @@ > #include > #include >=20 > +#define VTD_64BITS_ADDRESS(Lo, Hi) (LShiftU64 (Lo, 12) | LShiftU64 (Hi, = 32)) > + > #define ALIGN_VALUE_UP(Value, Alignment) (((Value) + (Alignment) - 1) & > (~((Alignment) - 1))) > #define ALIGN_VALUE_LOW(Value, Alignment) ((Value) & (~((Alignment) - 1)= )) >=20 > diff --git a/IntelSiliconPkg/IntelVTdDxe/PciInfo.c > b/IntelSiliconPkg/IntelVTdDxe/PciInfo.c > index ea84317c9ce4..d5f096fadd5d 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/PciInfo.c > +++ b/IntelSiliconPkg/IntelVTdDxe/PciInfo.c > @@ -289,7 +289,7 @@ FindVtdIndexByPciDevice ( >=20 > if (mVtdUnitInformation[VtdIndex].ExtRootEntryTable !=3D 0) { > ExtRootEntry =3D > &mVtdUnitInformation[VtdIndex].ExtRootEntryTable[SourceId.Index.RootIndex > ]; > - ExtContextEntryTable =3D (VTD_EXT_CONTEXT_ENTRY *)(UINTN)LShiftU64 > (ExtRootEntry->Bits.LowerContextTablePointer, 12) ; > + ExtContextEntryTable =3D (VTD_EXT_CONTEXT_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(ExtRootEntry->Bits.LowerContextTablePointerL > o, ExtRootEntry->Bits.LowerContextTablePointerHi) ; > ThisExtContextEntry =3D > &ExtContextEntryTable[SourceId.Index.ContextIndex]; > if (ThisExtContextEntry->Bits.AddressWidth =3D=3D 0) { > continue; > @@ -298,7 +298,7 @@ FindVtdIndexByPciDevice ( > *ContextEntry =3D NULL; > } else { > RootEntry =3D > &mVtdUnitInformation[VtdIndex].RootEntryTable[SourceId.Index.RootIndex]; > - ContextEntryTable =3D (VTD_CONTEXT_ENTRY *)(UINTN)LShiftU64 > (RootEntry->Bits.ContextTablePointer, 12) ; > + ContextEntryTable =3D (VTD_CONTEXT_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(RootEntry->Bits.ContextTablePointerLo, > RootEntry->Bits.ContextTablePointerHi) ; > ThisContextEntry =3D > &ContextEntryTable[SourceId.Index.ContextIndex]; > if (ThisContextEntry->Bits.AddressWidth =3D=3D 0) { > continue; > diff --git a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > index 5af4a4627b69..961d7cad0ddf 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > +++ b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > @@ -120,12 +120,13 @@ CreateContextEntry ( >=20 > RootEntry =3D > &mVtdUnitInformation[VtdIndex].RootEntryTable[SourceId.Index.RootIndex]; > if (RootEntry->Bits.Present =3D=3D 0) { > - RootEntry->Bits.ContextTablePointer =3D RShiftU64 > ((UINT64)(UINTN)Buffer, 12); > + RootEntry->Bits.ContextTablePointerLo =3D (UINT32) RShiftU64 > ((UINT64)(UINTN)Buffer, 12); > + RootEntry->Bits.ContextTablePointerHi =3D (UINT32) RShiftU64 > ((UINT64)(UINTN)Buffer, 32); > RootEntry->Bits.Present =3D 1; > Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); > } >=20 > - ContextEntryTable =3D (VTD_CONTEXT_ENTRY > *)(UINTN)LShiftU64(RootEntry->Bits.ContextTablePointer, 12) ; > + ContextEntryTable =3D (VTD_CONTEXT_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(RootEntry->Bits.ContextTablePointerLo, > RootEntry->Bits.ContextTablePointerHi) ; > ContextEntry =3D &ContextEntryTable[SourceId.Index.ContextIndex]; > ContextEntry->Bits.TranslationType =3D 0; > ContextEntry->Bits.FaultProcessingDisable =3D 0; > @@ -227,7 +228,7 @@ CreateSecondLevelPagingEntryTable ( > } > DEBUG ((DEBUG_INFO," Lvl4(0x%x): Lvl3Start - 0x%x, Lvl3End - 0x%x\n= ", > Index4, Lvl3Start, Lvl3End)); >=20 > - Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)LShiftU64 > (Lvl4PtEntry[Index4].Bits.Address, 12); > + Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(Lvl4PtEntry[Index4].Bits.AddressLo, > Lvl4PtEntry[Index4].Bits.AddressHi); > for (Index3 =3D Lvl3Start; Index3 <=3D Lvl3End; Index3++) { > if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) { > Lvl3PtEntry[Index3].Uint64 =3D (UINT64)(UINTN)AllocateZeroPages = (1); > @@ -239,7 +240,7 @@ CreateSecondLevelPagingEntryTable ( > SetSecondLevelPagingEntryAttribute (&Lvl3PtEntry[Index3], > EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); > } >=20 > - Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)LShiftU64 > (Lvl3PtEntry[Index3].Bits.Address, 12); > + Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(Lvl3PtEntry[Index3].Bits.AddressLo, > Lvl3PtEntry[Index3].Bits.AddressHi); > for (Index2 =3D 0; Index2 < > SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index2++) { > Lvl2PtEntry[Index2].Uint64 =3D BaseAddress; > SetSecondLevelPagingEntryAttribute (&Lvl2PtEntry[Index2], > IoMmuAccess); > @@ -341,7 +342,7 @@ DumpDmarContextEntryTable ( > if (RootEntry[Index].Bits.Present =3D=3D 0) { > continue; > } > - ContextEntry =3D (VTD_CONTEXT_ENTRY *)(UINTN)LShiftU64 > (RootEntry[Index].Bits.ContextTablePointer, 12); > + ContextEntry =3D (VTD_CONTEXT_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(RootEntry[Index].Bits.ContextTablePointerLo, > RootEntry[Index].Bits.ContextTablePointerHi); > for (Index2 =3D 0; Index2 < VTD_CONTEXT_ENTRY_NUMBER; Index2++) { > if ((ContextEntry[Index2].Uint128.Uint64Lo !=3D 0) || > (ContextEntry[Index2].Uint128.Uint64Hi !=3D 0)) { > DEBUG ((DEBUG_INFO," ContextEntry(0x%02x) D%02xF%02x - > 0x%016lx %016lx\n", > @@ -350,7 +351,7 @@ DumpDmarContextEntryTable ( > if (ContextEntry[Index2].Bits.Present =3D=3D 0) { > continue; > } > - DumpSecondLevelPagingEntry ((VOID *)(UINTN)LShiftU64 > (ContextEntry[Index2].Bits.SecondLevelPageTranslationPointer, 12)); > + DumpSecondLevelPagingEntry ((VOID > *)(UINTN)VTD_64BITS_ADDRESS(ContextEntry[Index2].Bits.SecondLevelPageTra > nslationPointerLo, > ContextEntry[Index2].Bits.SecondLevelPageTranslationPointerHi)); > } > } > DEBUG ((DEBUG_INFO,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); > @@ -387,7 +388,7 @@ DumpSecondLevelPagingEntry ( > if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) { > continue; > } > - Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)LShiftU64 > (Lvl4PtEntry[Index4].Bits.Address, 12); > + Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(Lvl4PtEntry[Index4].Bits.AddressLo, > Lvl4PtEntry[Index4].Bits.AddressHi); > for (Index3 =3D 0; Index3 < > SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index3++) { > if (Lvl3PtEntry[Index3].Uint64 !=3D 0) { > DEBUG ((DEBUG_VERBOSE," Lvl3Pt Entry(0x%03x) - 0x%016lx\n", > Index3, Lvl3PtEntry[Index3].Uint64)); > @@ -396,7 +397,7 @@ DumpSecondLevelPagingEntry ( > continue; > } >=20 > - Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)LShiftU64 > (Lvl3PtEntry[Index3].Bits.Address, 12); > + Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(Lvl3PtEntry[Index3].Bits.AddressLo, > Lvl3PtEntry[Index3].Bits.AddressHi); > for (Index2 =3D 0; Index2 < > SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index2++) { > if (Lvl2PtEntry[Index2].Uint64 !=3D 0) { > DEBUG ((DEBUG_VERBOSE," Lvl2Pt Entry(0x%03x) - > 0x%016lx\n", Index2, Lvl2PtEntry[Index2].Uint64)); > @@ -405,7 +406,7 @@ DumpSecondLevelPagingEntry ( > continue; > } > if (Lvl2PtEntry[Index2].Bits.PageSize =3D=3D 0) { > - Lvl1PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY > *)(UINTN)LShiftU64 (Lvl2PtEntry[Index2].Bits.Address, 12); > + Lvl1PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(Lvl2PtEntry[Index2].Bits.AddressLo, > Lvl2PtEntry[Index2].Bits.AddressHi); > for (Index1 =3D 0; Index1 < > SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); Index1++) { > if (Lvl1PtEntry[Index1].Uint64 !=3D 0) { > DEBUG ((DEBUG_VERBOSE," Lvl1Pt Entry(0x%03x) - > 0x%016lx\n", Index1, Lvl1PtEntry[Index1].Uint64)); > @@ -878,12 +879,13 @@ SetAccessAttribute ( > DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x > B%02x D%02x F%02x) New\n", SecondLevelPagingEntry, Segment, > SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function)); > Pt =3D (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 1= 2); >=20 > - ExtContextEntry->Bits.SecondLevelPageTranslationPointer =3D Pt; > - ExtContextEntry->Bits.DomainIdentifier =3D GetPciDescriptor (VtdIn= dex, > Segment, SourceId); > + ExtContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UIN= T32) > Pt; > + ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UIN= T32) > RShiftU64(Pt, 20); > + ExtContextEntry->Bits.DomainIdentifier =3D (UINT16) GetPciDescript= or > (VtdIndex, Segment, SourceId); > ExtContextEntry->Bits.Present =3D 1; > DumpDmarExtContextEntryTable > (mVtdUnitInformation[VtdIndex].ExtRootEntryTable); > } else { > - SecondLevelPagingEntry =3D (VOID *)(UINTN)LShiftU64 > (ExtContextEntry->Bits.SecondLevelPageTranslationPointer, 12); > + SecondLevelPagingEntry =3D (VOID > *)(UINTN)VTD_64BITS_ADDRESS(ExtContextEntry->Bits.SecondLevelPageTransla > tionPointerLo, ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi)= ; > DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x > B%02x D%02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus= , > SourceId.Bits.Device, SourceId.Bits.Function)); > } > } else if (ContextEntry !=3D NULL) { > @@ -892,12 +894,13 @@ SetAccessAttribute ( > DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x > B%02x D%02x F%02x) New\n", SecondLevelPagingEntry, Segment, > SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function)); > Pt =3D (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 1= 2); >=20 > - ContextEntry->Bits.SecondLevelPageTranslationPointer =3D Pt; > - ContextEntry->Bits.DomainIdentifier =3D GetPciDescriptor (VtdIndex= , > Segment, SourceId); > + ContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UINT32= ) Pt; > + ContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UINT32= ) > RShiftU64(Pt, 20); > + ContextEntry->Bits.DomainIdentifier =3D (UINT16) GetPciDescriptor > (VtdIndex, Segment, SourceId); > ContextEntry->Bits.Present =3D 1; > DumpDmarContextEntryTable > (mVtdUnitInformation[VtdIndex].RootEntryTable); > } else { > - SecondLevelPagingEntry =3D (VOID *)(UINTN)LShiftU64 > (ContextEntry->Bits.SecondLevelPageTranslationPointer, 12); > + SecondLevelPagingEntry =3D (VOID > *)(UINTN)VTD_64BITS_ADDRESS(ContextEntry->Bits.SecondLevelPageTranslatio > nPointerLo, ContextEntry->Bits.SecondLevelPageTranslationPointerHi); > DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x > B%02x D%02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus= , > SourceId.Bits.Device, SourceId.Bits.Function)); > } > } > @@ -958,11 +961,13 @@ AlwaysEnablePageAttribute ( > SecondLevelPagingEntry =3D > mVtdUnitInformation[VtdIndex].FixedSecondLevelPagingEntry; > Pt =3D (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 12); > if (ExtContextEntry !=3D NULL) { > - ExtContextEntry->Bits.SecondLevelPageTranslationPointer =3D Pt; > + ExtContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UINT3= 2) > Pt; > + ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UINT3= 2) > RShiftU64(Pt, 20); > ExtContextEntry->Bits.DomainIdentifier =3D ((1 << > (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1= ); > ExtContextEntry->Bits.Present =3D 1; > } else if (ContextEntry !=3D NULL) { > - ContextEntry->Bits.SecondLevelPageTranslationPointer =3D Pt; > + ContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UINT32) = Pt; > + ContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UINT32) > RShiftU64(Pt, 20); > ContextEntry->Bits.DomainIdentifier =3D ((1 << > (UINT8)((UINTN)mVtdUnitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1= ); > ContextEntry->Bits.Present =3D 1; > } > diff --git a/IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c > b/IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c > index 0f54b97d566c..65ed16ed7b8e 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c > +++ b/IntelSiliconPkg/IntelVTdDxe/TranslationTableEx.c > @@ -67,14 +67,16 @@ CreateExtContextEntry ( >=20 > ExtRootEntry =3D > &mVtdUnitInformation[VtdIndex].ExtRootEntryTable[SourceId.Index.RootIndex > ]; > if (ExtRootEntry->Bits.LowerPresent =3D=3D 0) { > - ExtRootEntry->Bits.LowerContextTablePointer =3D RShiftU64 > ((UINT64)(UINTN)Buffer, 12); > + ExtRootEntry->Bits.LowerContextTablePointerLo =3D (UINT32) RShift= U64 > ((UINT64)(UINTN)Buffer, 12); > + ExtRootEntry->Bits.LowerContextTablePointerHi =3D (UINT32) RShift= U64 > ((UINT64)(UINTN)Buffer, 32); > ExtRootEntry->Bits.LowerPresent =3D 1; > - ExtRootEntry->Bits.UpperContextTablePointer =3D RShiftU64 > ((UINT64)(UINTN)Buffer, 12) + 1; > + ExtRootEntry->Bits.UpperContextTablePointerLo =3D (UINT32) RShift= U64 > ((UINT64)(UINTN)Buffer, 12) + 1; > + ExtRootEntry->Bits.UpperContextTablePointerHi =3D (UINT32) RShift= U64 > (RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1, 20); > ExtRootEntry->Bits.UpperPresent =3D 1; > Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); > } >=20 > - ExtContextEntryTable =3D (VTD_EXT_CONTEXT_ENTRY > *)(UINTN)LShiftU64(ExtRootEntry->Bits.LowerContextTablePointer, 12) ; > + ExtContextEntryTable =3D (VTD_EXT_CONTEXT_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(ExtRootEntry->Bits.LowerContextTablePointerL > o, ExtRootEntry->Bits.LowerContextTablePointerHi) ; > ExtContextEntry =3D &ExtContextEntryTable[SourceId.Index.ContextInde= x]; > ExtContextEntry->Bits.TranslationType =3D 0; > ExtContextEntry->Bits.FaultProcessingDisable =3D 0; > @@ -122,7 +124,7 @@ DumpDmarExtContextEntryTable ( > if (ExtRootEntry[Index].Bits.LowerPresent =3D=3D 0) { > continue; > } > - ExtContextEntry =3D (VTD_EXT_CONTEXT_ENTRY *)(UINTN)LShiftU64 > (ExtRootEntry[Index].Bits.LowerContextTablePointer, 12); > + ExtContextEntry =3D (VTD_EXT_CONTEXT_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(ExtRootEntry[Index].Bits.LowerContextTableP > ointerLo, ExtRootEntry[Index].Bits.LowerContextTablePointerHi); > for (Index2 =3D 0; Index2 < VTD_CONTEXT_ENTRY_NUMBER/2; Index2++) { > if ((ExtContextEntry[Index2].Uint256.Uint64_1 !=3D 0) || > (ExtContextEntry[Index2].Uint256.Uint64_2 !=3D 0) || > (ExtContextEntry[Index2].Uint256.Uint64_3 !=3D 0) || > (ExtContextEntry[Index2].Uint256.Uint64_4 !=3D 0)) { > @@ -137,7 +139,7 @@ DumpDmarExtContextEntryTable ( > if (ExtRootEntry[Index].Bits.UpperPresent =3D=3D 0) { > continue; > } > - ExtContextEntry =3D (VTD_EXT_CONTEXT_ENTRY *)(UINTN)LShiftU64 > (ExtRootEntry[Index].Bits.UpperContextTablePointer, 12); > + ExtContextEntry =3D (VTD_EXT_CONTEXT_ENTRY > *)(UINTN)VTD_64BITS_ADDRESS(ExtRootEntry[Index].Bits.UpperContextTableP > ointerLo, ExtRootEntry[Index].Bits.UpperContextTablePointerHi); > for (Index2 =3D 0; Index2 < VTD_CONTEXT_ENTRY_NUMBER/2; Index2++) { > if ((ExtContextEntry[Index2].Uint256.Uint64_1 !=3D 0) || > (ExtContextEntry[Index2].Uint256.Uint64_2 !=3D 0) || > (ExtContextEntry[Index2].Uint256.Uint64_3 !=3D 0) || > (ExtContextEntry[Index2].Uint256.Uint64_4 !=3D 0)) { > diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > index d19aea2cc184..f36e3dec0671 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > +++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > @@ -526,7 +526,7 @@ DumpVtdRegs ( > FrcdReg.Uint64[1] =3D MmioRead64 > (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 1= 6) > + (Index * 16) + R_FRCD_REG + sizeof(UINT64))); > DEBUG((DEBUG_INFO, " FRCD_REG[%d] - 0x%016lx %016lx\n", Index, > FrcdReg.Uint64[1], FrcdReg.Uint64[0])); > if (FrcdReg.Uint64[1] !=3D 0 || FrcdReg.Uint64[0] !=3D 0) { > - DEBUG((DEBUG_INFO, " Fault Info - 0x%016lx\n", > LShiftU64(FrcdReg.Bits.FI, 12))); > + DEBUG((DEBUG_INFO, " Fault Info - 0x%016lx\n", > VTD_64BITS_ADDRESS(FrcdReg.Bits.FILo, FrcdReg.Bits.FIHi))); > SourceId.Uint16 =3D (UINT16)FrcdReg.Bits.SID; > DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", > SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function)); > DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, > FrcdReg.Bits.T ? "read" : "write")); > -- > 2.7.0.windows.1