From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2350621DF808A for ; Mon, 28 Aug 2017 01:16:53 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP; 28 Aug 2017 01:19:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,440,1498546800"; d="scan'208";a="1008290657" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga003.jf.intel.com with ESMTP; 28 Aug 2017 01:19:31 -0700 Received: from fmsmsx121.amr.corp.intel.com (10.18.125.36) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 28 Aug 2017 01:19:31 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx121.amr.corp.intel.com (10.18.125.36) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 28 Aug 2017 01:19:31 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.39]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.168]) with mapi id 14.03.0319.002; Mon, 28 Aug 2017 16:19:29 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: Laszlo Ersek , "Dong, Eric" Thread-Topic: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Centralize mPhysicalAddressBits definition Thread-Index: AQHTH6CXKZxbUbAPPES9vk9lZmIof6KZbW6A Date: Mon, 28 Aug 2017 08:19:28 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A9A0C36@shsmsx102.ccr.corp.intel.com> References: <1503885256-174936-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1503885256-174936-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Centralize mPhysicalAddressBits definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 08:16:53 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Zeng, Star > Sent: Monday, August 28, 2017 9:54 AM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Yao, Jiewen ; > Laszlo Ersek ; Dong, Eric > Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Centralize > mPhysicalAddressBits definition >=20 > Originally (before 714c2603018a99a514c42c2b511c821f30ba9cdf), > mPhysicalAddressBits was only defined in X64 PageTbl.c, after > 714c2603018a99a514c42c2b511c821f30ba9cdf, mPhysicalAddressBits is > also defined in Ia32 PageTbl.c, then mPhysicalAddressBits is used in > ConvertMemoryPageAttributes() for address check. >=20 > This patch is to centralize mPhysicalAddressBits definition to > PiSmmCpuDxeSmm.c from Ia32 and X64 PageTbl.c. >=20 > Cc: Jiewen Yao > Cc: Laszlo Ersek > Cc: Eric Dong > Suggested-by: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 2 -- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 2 ++ > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 1 - > 3 files changed, 2 insertions(+), 3 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > index e88b42d73343..f295c2ebf228 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > @@ -16,8 +16,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, > EITHER EXPRESS OR IMPLIED. >=20 > #include "PiSmmCpuDxeSmm.h" >=20 > -UINT8 mPhysicalAddressBits; > - > /** > Create PageTable for SMM use. >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > index 8e7964271125..282d2e69817c 100755 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > @@ -114,6 +114,8 @@ SPIN_LOCK > *mConfigSmmCodeAccessCheckLock =3D NULL; > EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; > UINTN mSmmCpuSmramRangeCount; >=20 > +UINT8 mPhysicalAddressBits; > + > /** > Initialize IDT to setup exception handlers for SMM. >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 32385faae470..3dde80f9bad6 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -21,7 +21,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, > EITHER EXPRESS OR IMPLIED. >=20 > LIST_ENTRY mPagePool =3D > INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); > BOOLEAN m1GPageTableSupport =3D FALSE; > -UINT8 mPhysicalAddressBits; > BOOLEAN mCpuSmmStaticPageTable; >=20 > /** > -- > 2.7.0.windows.1