From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 70F352095BB9A for ; Tue, 5 Sep 2017 21:01:35 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP; 05 Sep 2017 21:04:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,482,1498546800"; d="scan'208";a="125944540" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga004.jf.intel.com with ESMTP; 05 Sep 2017 21:04:25 -0700 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 5 Sep 2017 21:04:24 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX153.amr.corp.intel.com (10.18.125.6) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 5 Sep 2017 21:04:24 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.39]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Wed, 6 Sep 2017 12:04:23 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH 1/2] IntelSiliconPkg/Vtd: Support CSM usage. Thread-Index: AQHTJrXWRkAdpbLPY0Ksu+1k3lF57qKnPOXw Date: Wed, 6 Sep 2017 04:04:22 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A9A8391@shsmsx102.ccr.corp.intel.com> References: <1504582173-9088-1-git-send-email-jiewen.yao@intel.com> <1504582173-9088-2-git-send-email-jiewen.yao@intel.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B93A9C1@shsmsx102.ccr.corp.intel.com> In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB0483103B93A9C1@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 1/2] IntelSiliconPkg/Vtd: Support CSM usage. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Sep 2017 04:01:36 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Good suggestion. It can make error message more readable. > -----Original Message----- > From: Zeng, Star > Sent: Wednesday, September 6, 2017 10:14 AM > To: Yao, Jiewen ; edk2-devel@lists.01.org > Cc: Zeng, Star > Subject: RE: [PATCH 1/2] IntelSiliconPkg/Vtd: Support CSM usage. >=20 > How about we also enhance the debug message like below? >=20 > if (HasError) { > DEBUG((DEBUG_INFO, "#### ERROR ####\n")); > DumpVtdRegs (Num); > DEBUG((DEBUG_INFO, "#### ERROR ####\n")); > } >=20 > -> >=20 > if (HasError) { > DEBUG((DEBUG_INFO, "\n#### ERROR ####\n")); > DumpVtdRegs (Num); > DEBUG((DEBUG_INFO, "#### ERROR ####\n\n")); > } >=20 > Then the error message could be at a separated block for easy understandi= ng. >=20 >=20 > Thanks, > Star > -----Original Message----- > From: Yao, Jiewen > Sent: Tuesday, September 5, 2017 11:30 AM > To: edk2-devel@lists.01.org > Cc: Zeng, Star > Subject: [PATCH 1/2] IntelSiliconPkg/Vtd: Support CSM usage. >=20 > Remove zero address check in IoMmuMap. > The reason is that a CSM legacy driver may use legacy memory for DMA. > As such, the legacyBios need allow below 1M to the legacy device. >=20 > This patch also fixed some typo. >=20 > Cc: Star Zeng > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > --- > IntelSiliconPkg/IntelVTdDxe/BmDma.c | 8 ++++---- > IntelSiliconPkg/IntelVTdDxe/TranslationTable.c | 2 +- > 2 files changed, 5 insertions(+), 5 deletions(-) >=20 > diff --git a/IntelSiliconPkg/IntelVTdDxe/BmDma.c > b/IntelSiliconPkg/IntelVTdDxe/BmDma.c > index 5dcee00..7a5f361 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/BmDma.c > +++ b/IntelSiliconPkg/IntelVTdDxe/BmDma.c > @@ -77,14 +77,14 @@ IoMmuMap ( > EFI_PHYSICAL_ADDRESS DmaMemoryTop; > BOOLEAN NeedRemap; >=20 > - DEBUG ((DEBUG_VERBOSE, "IoMmuMap: =3D=3D> 0x%08x - 0x%08x (%x)\n", > HostAddress, NumberOfBytes, Operation)); > - > - if (HostAddress =3D=3D NULL || NumberOfBytes =3D=3D NULL || DeviceAddr= ess =3D=3D > NULL || > + if (NumberOfBytes =3D=3D NULL || DeviceAddress =3D=3D NULL || > Mapping =3D=3D NULL) { > DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_INVALID_PARAMETER)); > return EFI_INVALID_PARAMETER; > } >=20 > + DEBUG ((DEBUG_VERBOSE, "IoMmuMap: =3D=3D> 0x%08x - 0x%08x (%x)\n", > + HostAddress, *NumberOfBytes, Operation)); > + > // > // Make sure that Operation is valid > // > @@ -135,7 +135,7 @@ IoMmuMap ( > if (NeedRemap) { > // > // Common Buffer operations can not be remapped. If the common > buffer > - // if above 4GB, then it is not possible to generate a mapping, so= return > + // is above 4GB, then it is not possible to generate a mapping, > + so return > // an error. > // > DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_UNSUPPORTED)); diff > --git a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > index cd3111c..ccecc95 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > +++ b/IntelSiliconPkg/IntelVTdDxe/TranslationTable.c > @@ -891,7 +891,7 @@ SetAccessAttribute ( >=20 > SecondLevelPagingEntry =3D NULL; >=20 > - DEBUG ((DEBUG_INFO,"SetAccessAttribute (S%04x B%02x D%02x F%02x) > (0x%016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Dev= ice, > SourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess)); > + DEBUG ((DEBUG_VERBOSE,"SetAccessAttribute (S%04x B%02x D%02x F%02x) > + (0x%016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, > + SourceId.Bits.Device, SourceId.Bits.Function, BaseAddress, > + (UINTN)Length, IoMmuAccess)); >=20 > VtdIndex =3D FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEn= try, > &ContextEntry); > if (VtdIndex =3D=3D (UINTN)-1) { > -- > 2.7.4.windows.1