From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 437AF21E87967 for ; Wed, 13 Sep 2017 23:12:17 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Sep 2017 23:15:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,391,1500966000"; d="scan'208,217";a="1218617599" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga002.fm.intel.com with ESMTP; 13 Sep 2017 23:15:15 -0700 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Sep 2017 23:15:15 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Sep 2017 23:15:14 -0700 Received: from shsmsx151.ccr.corp.intel.com ([169.254.3.98]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.117]) with mapi id 14.03.0319.002; Thu, 14 Sep 2017 14:15:12 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR Thread-Index: AQHTLRtRVkQs2EKZx0KztTSRjCZOgKKz4WRQ//9+lwCAAIY6IA== Date: Thu, 14 Sep 2017 06:15:12 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A9B2498@SHSMSX151.ccr.corp.intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> <1504883034-22060-5-git-send-email-jiewen.yao@intel.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B952715@SHSMSX151.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C503A9B245E@SHSMSX151.ccr.corp.intel.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B9527F3@SHSMSX151.ccr.corp.intel.com> In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB0483103B9527F3@SHSMSX151.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Sep 2017 06:12:17 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Yes, I think the usage model is: Any DMA buffer MUST be requested explicitl= y. We do not want to allow a driver calling AllocatePage(), then start to use = the memory as DMA. It can help: 1) In case that the DMA buffer address is not identical. 2) DMA protection. Thank you Yao Jiewen From: Zeng, Star Sent: Thursday, September 14, 2017 2:10 PM To: Yao, Jiewen ; edk2-devel@lists.01.org Cc: Zeng, Star Subject: RE: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR Then, if there is a driver wants to do DMA at early DXE, it must need a PEI= M to allocate the DMA buffers in PEI and transfer them to DXE by HOB. Is that what we want? I want to confirm that. Thanks, Star -----Original Message----- From: Yao, Jiewen Sent: Thursday, September 14, 2017 2:03 PM To: Zeng, Star >; edk2-deve= l@lists.01.org Subject: RE: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR I did consider that before. I do not disable at EndOfPei purposely that because I want to make sure tha= t the DMA protect is still available in early DXE phase, just in case there= is bug in other module which forgets disabling BME. Later it is VTdDxe driver that disable PME, *after* it sets up translation = table. As such, the DMA protection is always there. Thank you Yao Jiewen > -----Original Message----- > From: Zeng, Star > Sent: Thursday, September 14, 2017 1:36 PM > To: Yao, Jiewen >; edk2= -devel@lists.01.org > Cc: Zeng, Star > > Subject: RE: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR > > A minor comment. > > Should or need IntelVTdPmrPei disable PMR at endofpei? > > > Thanks, > Star > -----Original Message----- > From: Yao, Jiewen > Sent: Friday, September 8, 2017 11:04 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star > > Subject: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR > > When VTd translation is enabled, PMR can be disable. > Or the DMA will be blocked by PMR. > > Cc: Star Zeng > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jiewen Yao > > --- > IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 51 +++++++++++++++++++- > 1 file changed, 50 insertions(+), 1 deletion(-) > > diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > index 7402d81..1404af7 100644 > --- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > +++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c > @@ -196,6 +196,39 @@ PrepareVtdConfig ( } > > /** > + Disable PMR in all VTd engine. > +**/ > +VOID > +DisablePmr ( > + VOID > + ) > +{ > + UINT32 Reg32; > + VTD_CAP_REG CapReg; > + UINTN Index; > + > + DEBUG ((DEBUG_INFO,"DisablePmr\n")); for (Index =3D 0; Index < > + mVtdUnitNumber; Index++) { > + CapReg.Uint64 =3D MmioRead64 > (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG); > + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { > + continue ; > + } > + > + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress > + + > R_PMEN_ENABLE_REG); > + if ((Reg32 & BIT0) !=3D 0) { > + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + > R_PMEN_ENABLE_REG, 0x0); > + do { > + Reg32 =3D MmioRead32 > (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG); > + } while((Reg32 & BIT0) !=3D 0); > + DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index)); > + } else { > + DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index)); > + } > + } > + return ; > +} > + > +/** > Enable DMAR translation. > > @retval EFI_SUCCESS DMAR translation is enabled. > @@ -259,6 +292,11 @@ EnableDmar ( > DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index)); > } > > + // > + // Need disable PMR, since we already setup translation table. > + // > + DisablePmr (); > + > mVtdEnabled =3D TRUE; > > return EFI_SUCCESS; > @@ -502,7 +540,7 @@ DumpVtdIfError ( > for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { > FrcdReg.Uint64[0] =3D MmioRead64 > (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) > + (Index * 16) + R_FRCD_REG)); > FrcdReg.Uint64[1] =3D MmioRead64 > (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) > + (Index * 16) + R_FRCD_REG + sizeof(UINT64))); > - if ((FrcdReg.Uint64[0] !=3D 0) || (FrcdReg.Uint64[1] !=3D 0)) { > + if (FrcdReg.Bits.F !=3D 0) { > HasError =3D TRUE; > } > } > @@ -511,6 +549,17 @@ DumpVtdIfError ( > DEBUG((DEBUG_INFO, "\n#### ERROR ####\n")); > DumpVtdRegs (Num); > DEBUG((DEBUG_INFO, "#### ERROR ####\n\n")); > + // > + // Clear > + // > + for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { > + FrcdReg.Uint64[1] =3D MmioRead64 > (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) > + (Index * 16) + R_FRCD_REG + sizeof(UINT64))); > + if (FrcdReg.Bits.F !=3D 0) { > + FrcdReg.Bits.F =3D 0; > + MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + > ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), > FrcdReg.Uint64[1]); > + } > + MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + > R_FSTS_REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + > R_FSTS_REG)); > + } > } > } > } > -- > 2.7.4.windows.1