From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 159FC21EC8CF3 for ; Wed, 27 Sep 2017 18:56:50 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 27 Sep 2017 19:00:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,447,1500966000"; d="scan'208";a="1224597580" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga002.fm.intel.com with ESMTP; 27 Sep 2017 19:00:04 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 27 Sep 2017 19:00:04 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 27 Sep 2017 19:00:04 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.98]) with mapi id 14.03.0319.002; Thu, 28 Sep 2017 10:00:02 +0800 From: "Yao, Jiewen" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: Ruiyu Ni , Sean Brogan , "Kinney, Michael D" Thread-Topic: [PATCH] MdeModulePkg/PciBusDxe: Enable Bus Master on P2P bridges on demand Thread-Index: AQHTHXXc0z1S1ge2j0mnlQhOBPtvxaLJwAcw Date: Thu, 28 Sep 2017 02:00:01 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503A9C726E@shsmsx102.ccr.corp.intel.com> References: <20170825074323.390468-1-ruiyu.ni@intel.com> In-Reply-To: <20170825074323.390468-1-ruiyu.ni@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/PciBusDxe: Enable Bus Master on P2P bridges on demand X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Sep 2017 01:56:51 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Ni, Ruiyu > Sent: Friday, August 25, 2017 3:43 PM > To: edk2-devel@lists.01.org > Cc: Ruiyu Ni ; Sean Brogan > ; Yao, Jiewen ; Kinney, > Michael D > Subject: [PATCH] MdeModulePkg/PciBusDxe: Enable Bus Master on P2P bridges > on demand >=20 > From: Ruiyu Ni >=20 > The patch dynamically enables Bus Master on P2P bridges only > when requested by a device driver through PciIo.Attribute() to enable > the Bus Master. >=20 > Signed-off-by: Sean Brogan > Signed-off-by: Ruiyu Ni > Cc: Jiewen Yao > Cc: Michael D Kinney > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 16 > +++++++++++++--- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 18 > +++++++++++++++--- > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++---- > 3 files changed, 32 insertions(+), 10 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > index c0227fa2b6..359b9ded6d 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > @@ -1,7 +1,7 @@ > /** @file > Supporting functions implementaion for PCI devices management. >=20 > -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
> +Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the BS= D > License > which accompanies this distribution. The full text of the license may b= e found > at > @@ -711,7 +711,12 @@ StartPciDevicesOnBridge ( > 0, > &Supports > ); > - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > + // > + // By default every bridge's IO and MMIO spaces are enabled. > + // Bridge's Bus Master will be enabled when any device behind it > requests > + // to enable Bus Master. > + // > + Supports &=3D (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | > EFI_PCI_IO_ATTRIBUTE_MEMORY); > PciIoDevice->PciIo.Attributes ( > &(PciIoDevice->PciIo), > EfiPciIoAttributeOperationEnable, > @@ -763,7 +768,12 @@ StartPciDevicesOnBridge ( > 0, > &Supports > ); > - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > + // > + // By default every bridge's IO and MMIO spaces are enabled. > + // Bridge's Bus Master will be enabled when any device behind it > requests > + // to enable Bus Master. > + // > + Supports &=3D (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | > EFI_PCI_IO_ATTRIBUTE_MEMORY); > PciIoDevice->PciIo.Attributes ( > &(PciIoDevice->PciIo), > EfiPciIoAttributeOperationEnable, > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > index 81171c82d9..f73756a31e 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > @@ -1218,11 +1218,12 @@ DetermineDeviceAttribute ( > return Status; > } > // > - // Assume the PCI Root Bridge supports DAC > + // Assume the PCI Root Bridge supports DAC and Bus Master. > // > PciIoDevice->Supports |=3D > (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | > EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | > - > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE); > + > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | > + EFI_PCI_IO_ATTRIBUTE_BUS_MASTER); >=20 > } else { >=20 > @@ -1233,9 +1234,16 @@ DetermineDeviceAttribute ( > // > Command =3D EFI_PCI_COMMAND_IO_SPACE | > EFI_PCI_COMMAND_MEMORY_SPACE | > - EFI_PCI_COMMAND_BUS_MASTER | > EFI_PCI_COMMAND_VGA_PALETTE_SNOOP; >=20 > + // > + // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus= Master > capable. > + // So only test the Bus Master capability for PCI devices. > + // > + if (!IS_PCI_BRIDGE(&PciIoDevice->Pci)) { > + Command |=3D EFI_PCI_COMMAND_BUS_MASTER; > + } > + > BridgeControl =3D EFI_PCI_BRIDGE_CONTROL_ISA | > EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16; >=20 > // > @@ -1245,7 +1253,11 @@ DetermineDeviceAttribute ( >=20 > // > // Set the supported attributes for specified PCI device > + // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus= Master > capable. > // > + if (IS_PCI_BRIDGE(&PciIoDevice->Pci)) { > + Command |=3D EFI_PCI_COMMAND_BUS_MASTER; > + } > PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, > EFI_SET_SUPPORTS); >=20 > // > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > index cc7125e4fc..659f480d71 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > @@ -1348,7 +1348,8 @@ ModifyRootBridgeAttributes ( > // > Attributes &=3D ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | > EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | > - EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE); > + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | > + EFI_PCI_IO_ATTRIBUTE_BUS_MASTER); >=20 > // > // Record the new attribute of the Root Bridge > @@ -1726,12 +1727,11 @@ PciIoAttributes ( > } > // > // The upstream bridge should be also set to revelant attribute > - // expect for IO, Mem and BusMaster > + // expect for IO and Mem > // > UpStreamAttributes =3D Attributes & > (~(EFI_PCI_IO_ATTRIBUTE_IO | > - EFI_PCI_IO_ATTRIBUTE_MEMORY | > - EFI_PCI_IO_ATTRIBUTE_BUS_MASTER > + EFI_PCI_IO_ATTRIBUTE_MEMORY > ) > ); > UpStreamBridge =3D PciIoDevice->Parent; > -- > 2.12.2.windows.2