From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D1E8420359A90 for ; Wed, 22 Nov 2017 00:11:33 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Nov 2017 00:15:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,436,1505804400"; d="scan'208";a="4666768" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga004.fm.intel.com with ESMTP; 22 Nov 2017 00:15:35 -0800 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 22 Nov 2017 00:15:35 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 22 Nov 2017 00:15:35 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Wed, 22 Nov 2017 16:15:32 +0800 From: "Yao, Jiewen" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: Michael Turner , "Kinney, Michael D" Thread-Topic: [PATCH 2/2] MdeModulePkg/PciBus: Revert "Enable BM on P2P bridges on demand" Thread-Index: AQHTYax6/eULc0P1RkqHsurCQPJM4KMgEMDQ Date: Wed, 22 Nov 2017 08:15:31 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA28014@shsmsx102.ccr.corp.intel.com> References: <20171120030532.7548-1-ruiyu.ni@intel.com> <20171120030532.7548-3-ruiyu.ni@intel.com> In-Reply-To: <20171120030532.7548-3-ruiyu.ni@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWIzMjQyOWQtYzE3Ny00NzA4LWIxY2QtNTg1ZDRiNmY4YWY2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJkR1BPUUtxeVBydVd0cFdyS1JxVE5PSEIxSnE0aXZzc2FyTFBpaGxXMjkxYTJGY2wwSUxrcVwvV01SS1AzdWlndyJ9 x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] MdeModulePkg/PciBus: Revert "Enable BM on P2P bridges on demand" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Nov 2017 08:11:34 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Ni, Ruiyu > Sent: Monday, November 20, 2017 11:06 AM > To: edk2-devel@lists.01.org > Cc: Ni, Ruiyu ; Michael Turner > ; Kinney, Michael D > ; Yao, Jiewen > Subject: [PATCH 2/2] MdeModulePkg/PciBus: Revert "Enable BM on P2P bridge= s > on demand" >=20 > This reverts commit 5db417ed2522367290c365831f9d6628d31c346c. > "MdeModulePkg/PciBusDxe: Enable Bus Master on P2P bridges on demand" >=20 > We met some compatibility issues when doing Windows S4 resume. > Reverting the BME disabling patches to fix the S4 resume issue. >=20 > Signed-off-by: Ruiyu Ni > Signed-off-by: Michael Turner > Cc: Michael D Kinney > Cc: Jiewen Yao > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 16 > +++------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 18 > +++--------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 8 ++++---- > 3 files changed, 10 insertions(+), 32 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > index 97bb971a59..e76c8f0046 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > @@ -1,7 +1,7 @@ > /** @file > Supporting functions implementaion for PCI devices management. >=20 > -Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the BS= D > License > which accompanies this distribution. The full text of the license may b= e found > at > @@ -711,12 +711,7 @@ StartPciDevicesOnBridge ( > 0, > &Supports > ); > - // > - // By default every bridge's IO and MMIO spaces are enabled. > - // Bridge's Bus Master will be enabled when any device behind it > requests > - // to enable Bus Master. > - // > - Supports &=3D (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | > EFI_PCI_IO_ATTRIBUTE_MEMORY); > + Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > PciIoDevice->PciIo.Attributes ( > &(PciIoDevice->PciIo), > EfiPciIoAttributeOperationEnable, > @@ -768,12 +763,7 @@ StartPciDevicesOnBridge ( > 0, > &Supports > ); > - // > - // By default every bridge's IO and MMIO spaces are enabled. > - // Bridge's Bus Master will be enabled when any device behind it > requests > - // to enable Bus Master. > - // > - Supports &=3D (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | > EFI_PCI_IO_ATTRIBUTE_MEMORY); > + Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; > PciIoDevice->PciIo.Attributes ( > &(PciIoDevice->PciIo), > EfiPciIoAttributeOperationEnable, > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > index f73756a31e..81171c82d9 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > @@ -1218,12 +1218,11 @@ DetermineDeviceAttribute ( > return Status; > } > // > - // Assume the PCI Root Bridge supports DAC and Bus Master. > + // Assume the PCI Root Bridge supports DAC > // > PciIoDevice->Supports |=3D > (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | > EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | > - > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | > - EFI_PCI_IO_ATTRIBUTE_BUS_MASTER); > + > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE); >=20 > } else { >=20 > @@ -1234,16 +1233,9 @@ DetermineDeviceAttribute ( > // > Command =3D EFI_PCI_COMMAND_IO_SPACE | > EFI_PCI_COMMAND_MEMORY_SPACE | > + EFI_PCI_COMMAND_BUS_MASTER | > EFI_PCI_COMMAND_VGA_PALETTE_SNOOP; >=20 > - // > - // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus= Master > capable. > - // So only test the Bus Master capability for PCI devices. > - // > - if (!IS_PCI_BRIDGE(&PciIoDevice->Pci)) { > - Command |=3D EFI_PCI_COMMAND_BUS_MASTER; > - } > - > BridgeControl =3D EFI_PCI_BRIDGE_CONTROL_ISA | > EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16; >=20 > // > @@ -1253,11 +1245,7 @@ DetermineDeviceAttribute ( >=20 > // > // Set the supported attributes for specified PCI device > - // Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus= Master > capable. > // > - if (IS_PCI_BRIDGE(&PciIoDevice->Pci)) { > - Command |=3D EFI_PCI_COMMAND_BUS_MASTER; > - } > PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, > EFI_SET_SUPPORTS); >=20 > // > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > index 659f480d71..cc7125e4fc 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > @@ -1348,8 +1348,7 @@ ModifyRootBridgeAttributes ( > // > Attributes &=3D ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE | > EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM | > - EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE | > - EFI_PCI_IO_ATTRIBUTE_BUS_MASTER); > + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE); >=20 > // > // Record the new attribute of the Root Bridge > @@ -1727,11 +1726,12 @@ PciIoAttributes ( > } > // > // The upstream bridge should be also set to revelant attribute > - // expect for IO and Mem > + // expect for IO, Mem and BusMaster > // > UpStreamAttributes =3D Attributes & > (~(EFI_PCI_IO_ATTRIBUTE_IO | > - EFI_PCI_IO_ATTRIBUTE_MEMORY > + EFI_PCI_IO_ATTRIBUTE_MEMORY | > + EFI_PCI_IO_ATTRIBUTE_BUS_MASTER > ) > ); > UpStreamBridge =3D PciIoDevice->Parent; > -- > 2.15.0.gvfs.1.preview.4