* [PATCH v2 0/8] Implement stack guard feature
@ 2017-11-22 8:45 Jian J Wang
2017-11-22 8:45 ` [PATCH v2 1/8] MdeModulePkg/metafile: Add PCD PcdCpuStackGuard Jian J Wang
` (8 more replies)
0 siblings, 9 replies; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel
Stack guard feature makes use of paging mechanism to monitor if there's a
stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added to
enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and
PcdCpuKnownGoodStackSize are introduced to configure the required exceptions
and stack size.
If this feature is enabled, DxeIpl will setup page tables and set page where
the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page
Fault exception will be triggered.
In order to make sure exception handler works normally even when the stack
is corrupted, stack switching is implemented in exception library.
Due to the mechanism behind Stack Guard, this feature is only avaiable for
UEFI drivers (memory avaiable). That also means it doesn't support NT32
emulated platform (paging not supported).
Validation works include:
a. OVMF emulated platform: boot to shell (IA32/X64)
b. Intel real platform: boot to shell (IA32/X64)
Jian J Wang (8):
MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
MdePkg/BaseLib: Add stack switch related definitions for IA32
MdeModulePkg/DxeIpl: Enable paging for Stack Guard
UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch
UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data
UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
UefiCpuPkg/CpuDxe: Initialize stack switch for MP
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +-
MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +
MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 +
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++-
.../Include/Library/CpuExceptionHandlerLib.h | 18 +
MdeModulePkg/MdeModulePkg.dec | 7 +
MdeModulePkg/MdeModulePkg.uni | 7 +
MdePkg/Include/Library/BaseLib.h | 115 ++++++
MdePkg/Library/BaseLib/BaseLib.inf | 3 +
MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++
MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++
UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
UefiCpuPkg/CpuDxe/CpuMp.c | 168 +++++++++
UefiCpuPkg/CpuDxe/CpuMp.h | 12 +
.../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
.../DxeCpuExceptionHandlerLib.inf | 6 +
.../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
.../Ia32/ArchExceptionHandler.c | 167 +++++++++
.../Ia32/ArchInterruptDefs.h | 8 +
.../Ia32/ExceptionTssEntryAsm.nasm | 398 +++++++++++++++++++++
.../PeiCpuExceptionHandlerLib.inf | 1 +
.../SecPeiCpuExceptionHandlerLib.inf | 1 +
.../SmmCpuExceptionHandlerLib.inf | 1 +
.../X64/ArchExceptionHandler.c | 133 +++++++
.../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +
UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +
UefiCpuPkg/UefiCpuPkg.dec | 12 +
28 files changed, 1304 insertions(+), 16 deletions(-)
create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
--
2.14.1.windows.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 1/8] MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-22 8:45 ` [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API Jian J Wang
` (7 subsequent siblings)
8 siblings, 0 replies; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Star Zeng, Eric Dong
PcdCpuStackGuard is introduced to enable/disable Stack Guard feature.
Its value is FALSE by default.
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
MdeModulePkg/MdeModulePkg.dec | 7 +++++++
MdeModulePkg/MdeModulePkg.uni | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 856d67aceb..b3831a21ad 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -949,6 +949,13 @@
# @Prompt The Heap Guard feature mask
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask|0x0|UINT8|0x30001054
+ ## Indicates if UEFI Stack Guard will be enabled.
+ # If enabled, stack overflow in UEFI can be caught, preventing chaotic consequences.<BR><BR>
+ # TRUE - UEFI Stack Guard will be enabled.<BR>
+ # FALSE - UEFI Stack Guard will be disabled.<BR>
+ # @Prompt Enable UEFI Stack Guard.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE|BOOLEAN|0x30001055
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
## Dynamic type PCD can be registered callback function for Pcd setting action.
# PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum number of callback function
diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni
index 588905a9a1..43dd5103be 100644
--- a/MdeModulePkg/MdeModulePkg.uni
+++ b/MdeModulePkg/MdeModulePkg.uni
@@ -1204,3 +1204,10 @@
" 0 - The returned pool is adjacent to the bottom guard page.<BR>\n"
" 1 - The returned pool is adjacent to the top guard page.<BR>"
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdCpuStackGuard_PROMPT #language en-US "Enable UEFI Stack Guard"
+
+#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdCpuStackGuard_HELP #language en-US "Indicates if UEFI Stack Guard will be enabled.\n"
+ " If enabled, stack overflow in UEFI can be caught, preventing chaotic consequences.<BR><BR>\n"
+ " TRUE - UEFI Stack Guard will be enabled.<BR>\n"
+ " FALSE - UEFI Stack Guard will be disabled.<BR>"
+
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
2017-11-22 8:45 ` [PATCH v2 1/8] MdeModulePkg/metafile: Add PCD PcdCpuStackGuard Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-23 4:07 ` Yao, Jiewen
2017-11-22 8:45 ` [PATCH v2 3/8] MdePkg/BaseLib: Add stack switch related definitions for IA32 Jian J Wang
` (6 subsequent siblings)
8 siblings, 1 reply; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Star Zeng, Eric Dong, Jiewen Yao
> v2:
> Add prototype definition of InitializeCpuExceptionStackSwitchHandlers()
A new API InitializeCpuExceptionStackSwitchHandlers() is introduced to support
initializing exception handlers being able to switch stack. StackSwitchData is
arch dependent and required by IA32 processor to convey resources reserved in
advance. This is necessary because the CpuExceptionHandlerLib will be linked
in different phases, in which there's no common way to reserve resources.
EFI_STATUS
EFIAPI
InitializeCpuExceptionStackSwitchHandlers (
IN VOID *StackSwitchData OPTIONAL
);
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
index 6cd8230127..68de4850e1 100644
--- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
+++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
@@ -41,6 +41,24 @@ InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
);
+/**
+ Setup separate stack for given exceptions. StackSwitchData is optional and its
+ content depends one the specific arch of CPU.
+
+ @param[in] StackSwitchData Pointer to data required for setuping up
+ stack switch.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionStackSwitchHandlers (
+ IN VOID *StackSwitchData OPTIONAL
+ );
+
/**
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 3/8] MdePkg/BaseLib: Add stack switch related definitions for IA32
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
2017-11-22 8:45 ` [PATCH v2 1/8] MdeModulePkg/metafile: Add PCD PcdCpuStackGuard Jian J Wang
2017-11-22 8:45 ` [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-22 8:45 ` [PATCH v2 4/8] MdeModulePkg/DxeIpl: Enable paging for Stack Guard Jian J Wang
` (5 subsequent siblings)
8 siblings, 0 replies; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Liming Gao, Jiewen Yao
> v2:
> Add new definitions required by stack switch in IA32
The new definitions include two structures
IA32_TASK_STATE_SEGMENT
IA32_TSS_DESCRIPTOR
and one API
VOID
EFIAPI
AsmWriteTr (
IN UINT16 Selector
);
They're needed to setup task gate and interrupt stack table for stack switch.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
MdePkg/Include/Library/BaseLib.h | 115 +++++++++++++++++++++++++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 3 +
MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++++++++++
MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++++++++++
4 files changed, 191 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d33c3b6b38..371109ad8f 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -6663,6 +6663,70 @@ typedef union {
UINT64 Uint64;
} IA32_IDT_GATE_DESCRIPTOR;
+#pragma pack (1)
+//
+// IA32 Task-State Segment Definition
+//
+typedef struct {
+ UINT16 PreviousTaskLink;
+ UINT16 Reserved_2;
+ UINT32 ESP0;
+ UINT16 SS0;
+ UINT16 Reserved_10;
+ UINT32 ESP1;
+ UINT16 SS1;
+ UINT16 Reserved_18;
+ UINT32 ESP2;
+ UINT16 SS2;
+ UINT16 Reserved_26;
+ UINT32 CR3;
+ UINT32 EIP;
+ UINT32 EFLAGS;
+ UINT32 EAX;
+ UINT32 ECX;
+ UINT32 EDX;
+ UINT32 EBX;
+ UINT32 ESP;
+ UINT32 EBP;
+ UINT32 ESI;
+ UINT32 EDI;
+ UINT16 ES;
+ UINT16 Reserved_74;
+ UINT16 CS;
+ UINT16 Reserved_78;
+ UINT16 SS;
+ UINT16 Reserved_82;
+ UINT16 DS;
+ UINT16 Reserved_86;
+ UINT16 FS;
+ UINT16 Reserved_90;
+ UINT16 GS;
+ UINT16 Reserved_94;
+ UINT16 LDTSegmentSelector;
+ UINT16 Reserved_98;
+ UINT16 T;
+ UINT16 IOMapBaseAddress;
+} IA32_TASK_STATE_SEGMENT;
+
+typedef union {
+ struct {
+ UINT32 LimitLow:16; ///< Segment Limit 15..00
+ UINT32 BaseLow:16; ///< Base Address 15..00
+ UINT32 BaseMid:8; ///< Base Address 23..16
+ UINT32 Type:4; ///< Type (1 0 B 1)
+ UINT32 Reserved_43:1; ///< 0
+ UINT32 DPL:2; ///< Descriptor Privilege Level
+ UINT32 P:1; ///< Segment Present
+ UINT32 LimitHigh:4; ///< Segment Limit 19..16
+ UINT32 AVL:1; ///< Available for use by system software
+ UINT32 Reserved_52:2; ///< 0 0
+ UINT32 G:1; ///< Granularity
+ UINT32 BaseHigh:8; ///< Base Address 31..24
+ } Bits;
+ UINT64 Uint64;
+} IA32_TSS_DESCRIPTOR;
+#pragma pack ()
+
#endif
#if defined (MDE_CPU_X64)
@@ -6685,6 +6749,46 @@ typedef union {
} Uint128;
} IA32_IDT_GATE_DESCRIPTOR;
+#pragma pack (1)
+//
+// IA32 Task-State Segment Definition
+//
+typedef struct {
+ UINT32 Reserved_0;
+ UINT64 RSP0;
+ UINT64 RSP1;
+ UINT64 RSP2;
+ UINT64 Reserved_28;
+ UINT64 IST[7];
+ UINT64 Reserved_92;
+ UINT16 Reserved_100;
+ UINT16 IOMapBaseAddress;
+} IA32_TASK_STATE_SEGMENT;
+
+typedef union {
+ struct {
+ UINT32 LimitLow:16; ///< Segment Limit 15..00
+ UINT32 BaseLow:16; ///< Base Address 15..00
+ UINT32 BaseMidl:8; ///< Base Address 23..16
+ UINT32 Type:4; ///< Type (1 0 B 1)
+ UINT32 Reserved_43:1; ///< 0
+ UINT32 DPL:2; ///< Descriptor Privilege Level
+ UINT32 P:1; ///< Segment Present
+ UINT32 LimitHigh:4; ///< Segment Limit 19..16
+ UINT32 AVL:1; ///< Available for use by system software
+ UINT32 Reserved_52:2; ///< 0 0
+ UINT32 G:1; ///< Granularity
+ UINT32 BaseMidh:8; ///< Base Address 31..24
+ UINT32 BaseHigh:32; ///< Base Address 63..32
+ UINT32 Reserved_96:32; ///< Reserved
+ } Bits;
+ struct {
+ UINT64 Uint64;
+ UINT64 Uint64_1;
+ } Uint128;
+} IA32_TSS_DESCRIPTOR;
+#pragma pack ()
+
#endif
///
@@ -8950,6 +9054,17 @@ AsmRdRand64 (
OUT UINT64 *Rand
);
+/**
+ Load given selector into TR register
+
+ @param[in] Selector Task segment selector
+**/
+VOID
+EFIAPI
+AsmWriteTr (
+ IN UINT16 Selector
+ );
+
#endif
#endif
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 320ac457ea..fbfb0063b7 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -67,6 +67,8 @@
BaseLibInternals.h
[Sources.Ia32]
+ Ia32/WriteTr.nasm
+
Ia32/Wbinvd.c | MSFT
Ia32/WriteMm7.c | MSFT
Ia32/WriteMm6.c | MSFT
@@ -447,6 +449,7 @@
X64/EnableCache.asm
X64/DisableCache.nasm
X64/DisableCache.asm
+ X64/WriteTr.nasm
X64/CpuBreakpoint.c | MSFT
X64/WriteMsr64.c | MSFT
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm b/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
new file mode 100644
index 0000000000..cde5a3a423
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
@@ -0,0 +1,36 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; WriteTr.nasm
+;
+; Abstract:
+;
+; Write TR register
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; AsmWriteTr (
+; UINT16 Selector
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteTr)
+ASM_PFX(AsmWriteTr):
+ mov eax, [esp+4]
+ ltr ax
+ ret
+
diff --git a/MdePkg/Library/BaseLib/X64/WriteTr.nasm b/MdePkg/Library/BaseLib/X64/WriteTr.nasm
new file mode 100644
index 0000000000..3bf1500c36
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/WriteTr.nasm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; WriteTr.nasm
+;
+; Abstract:
+;
+; Write TR register
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; AsmWriteTr (
+; UINT16 Selector
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteTr)
+ASM_PFX(AsmWriteTr):
+ mov eax, ecx
+ ltr ax
+ ret
+
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 4/8] MdeModulePkg/DxeIpl: Enable paging for Stack Guard
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
` (2 preceding siblings ...)
2017-11-22 8:45 ` [PATCH v2 3/8] MdePkg/BaseLib: Add stack switch related definitions for IA32 Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-22 8:45 ` [PATCH v2 5/8] UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch Jian J Wang
` (4 subsequent siblings)
8 siblings, 0 replies; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Star Zeng, Eric Dong, Jiewen Yao
Stack guard feature makes use of paging mechanism to monitor if there's a
stack overflow occurred during boot.
This patch will check setting of PCD PcdCpuStackGuard. If it's TRUE, DxeIpl
will setup page table and set the page at which the stack base locates to be
NOT PRESENT. If stack is used up and memory access cross into the last page
of it, #PF exception will be triggered.
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 ++-
MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 ++
MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 +
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++++++++++++++++++------
4 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index a1b8748432..ba1d9c6b05 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -49,7 +49,7 @@
[Sources.X64]
X64/VirtualMemory.h
X64/VirtualMemory.c
- X64/DxeLoadFunc.c
+ X64/DxeLoadFunc.c
[Sources.IPF]
Ipf/DxeLoadFunc.c
@@ -117,6 +117,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES
[Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIMES_CONSUMES
@@ -132,7 +133,7 @@
#
# [Hob]
# MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # MEMORY_ALLOCATION_MODULE for DxeCore
-# MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # New Stack HoB
+# MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # New Stack HoB
# MEMORY_ALLOCATION ## SOMETIMES_PRODUCES # Old Stack HOB
#
# [Hob.IPF]
diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
index 5649265367..441096ad0f 100644
--- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
@@ -235,6 +235,10 @@ ToBuildPageTable (
return TRUE;
}
+ if (PcdGetBool (PcdCpuStackGuard)) {
+ return TRUE;
+ }
+
if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable ()) {
return TRUE;
}
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
index f613221b81..b75a4489bf 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
@@ -95,6 +95,7 @@ HandOffToDxeCore (
// for the DxeIpl and the DxeCore are both X64.
//
ASSERT (PcdGetBool (PcdSetNxForStack) == FALSE);
+ ASSERT (PcdGetBool (PcdCpuStackGuard) == FALSE);
}
//
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 29b6205e88..a2466b7766 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -117,6 +117,39 @@ EnableExecuteDisableBit (
AsmWriteMsr64 (0xC0000080, MsrRegisters);
}
+/**
+ The function will check if page table entry should be splitted to smaller
+ granularity.
+
+ @retval TRUE Page table should be created.
+ @retval FALSE Page table should not be created.
+**/
+BOOLEAN
+ToSplitPageTable (
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN UINTN Size,
+ IN EFI_PHYSICAL_ADDRESS StackBase,
+ IN UINTN StackSize
+ )
+{
+ if (IsNullDetectionEnabled () && Address == 0) {
+ return TRUE;
+ }
+
+ if (PcdGetBool (PcdCpuStackGuard)) {
+ if (StackBase >= Address && StackBase < (Address + Size)) {
+ return TRUE;
+ }
+ }
+
+ if (PcdGetBool (PcdSetNxForStack)) {
+ if ((Address < StackBase + StackSize) && ((Address + Size) > StackBase)) {
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
/**
Split 2M page to 4K.
@@ -160,7 +193,8 @@ Split2MPageTo4K (
PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;
PageTableEntry->Bits.ReadWrite = 1;
- if (IsNullDetectionEnabled () && PhysicalAddress4K == 0) {
+ if ((IsNullDetectionEnabled () && PhysicalAddress4K == 0) ||
+ (PcdGetBool (PcdCpuStackGuard) && PhysicalAddress4K == StackBase)) {
PageTableEntry->Bits.Present = 0;
} else {
PageTableEntry->Bits.Present = 1;
@@ -214,10 +248,7 @@ Split1GPageTo2M (
PhysicalAddress2M = PhysicalAddress;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {
- if ((IsNullDetectionEnabled () && PhysicalAddress2M == 0)
- || (PcdGetBool (PcdSetNxForStack)
- && (PhysicalAddress2M < StackBase + StackSize)
- && ((PhysicalAddress2M + SIZE_2MB) > StackBase))) {
+ if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSize)) {
//
// Need to split this 2M page that covers NULL or stack range.
//
@@ -359,10 +390,7 @@ CreateIdentityMappingPageTables (
PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
- if ((IsNullDetectionEnabled () && PageAddress == 0)
- || (PcdGetBool (PcdSetNxForStack)
- && (PageAddress < StackBase + StackSize)
- && ((PageAddress + SIZE_1GB) > StackBase))) {
+ if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize)) {
Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize);
} else {
//
@@ -391,10 +419,7 @@ CreateIdentityMappingPageTables (
PageDirectoryPointerEntry->Bits.Present = 1;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
- if ((IsNullDetectionEnabled () && PageAddress == 0)
- || (PcdGetBool (PcdSetNxForStack)
- && (PageAddress < StackBase + StackSize)
- && ((PageAddress + SIZE_2MB) > StackBase))) {
+ if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSize)) {
//
// Need to split this 2M page that covers NULL or stack range.
//
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 5/8] UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
` (3 preceding siblings ...)
2017-11-22 8:45 ` [PATCH v2 4/8] MdeModulePkg/DxeIpl: Enable paging for Stack Guard Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-22 8:45 ` [PATCH v2 6/8] UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data Jian J Wang
` (3 subsequent siblings)
8 siblings, 0 replies; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Eric Dong, Laszlo Ersek, Jiewen Yao
> v2:
> Add two new PCDs to configure exception stack switch.
Stack switch is required by Stack Guard feature. Following two PCDs are
introduced to simplify the resource allocation for initializing stack switch.
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
PcdCpuStackSwitchExceptionList is used to specify which exception will
have separate stack for its handler. For Stack Guard feature, #PF must
be specified at least.
PcdCpuKnownGoodStackSize is used to specify the size of good stack for an
exception handler. Cpu driver or other drivers should use this PCD to reserve
stack memory for exceptions specified above PCD.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
UefiCpuPkg/UefiCpuPkg.dec | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 3bd8740c98..b87e20fb38 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -144,6 +144,18 @@
# @Prompt Lock SMM Feature Control MSR.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
+[PcdsFixedAtBuild]
+ ## List of exception vectors which need switching stack.
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.
+ # By default exception #DD(8), #PF(14) are supported.
+ # @Prompt Specify exception vectors which need switching stack.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
+
+ ## Size of good stack for an exception.
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.
+ # @Prompt Specify size of good stack of exception which need switching stack.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
# @Prompt Configure base address of CPU Local APIC
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 6/8] UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
` (4 preceding siblings ...)
2017-11-22 8:45 ` [PATCH v2 5/8] UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-22 8:45 ` [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support Jian J Wang
` (2 subsequent siblings)
8 siblings, 0 replies; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Eric Dong, Laszlo Ersek, Jiewen Yao
> v2:
> Add code to save/restore GDTR, IDTR and TR for AP.
In current implementation of CPU MP, AP is initialized with data copied from
BSP. Stack switch required by Stack Guard feature needs different GDT, IDT
table and task gates for each logic processor. This patch adds GDTR, IDTR and
TR into structure CPU_VOLATILE_REGISTERS and save/restore methods. This will
make sure that any changes to GDT, IDT and task gate for an AP will be kept
from overwritten by BSP settings.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +++++++++++++++++
UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 61b14c9843..0c2058a7b0 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -195,6 +195,10 @@ SaveVolatileRegisters (
VolatileRegisters->Dr6 = AsmReadDr6 ();
VolatileRegisters->Dr7 = AsmReadDr7 ();
}
+
+ AsmReadGdtr (&VolatileRegisters->Gdtr);
+ AsmReadIdtr (&VolatileRegisters->Idtr);
+ VolatileRegisters->Tr = AsmReadTr ();
}
/**
@@ -211,6 +215,7 @@ RestoreVolatileRegisters (
)
{
CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ IA32_TSS_DESCRIPTOR *Tss;
AsmWriteCr0 (VolatileRegisters->Cr0);
AsmWriteCr3 (VolatileRegisters->Cr3);
@@ -231,6 +236,18 @@ RestoreVolatileRegisters (
AsmWriteDr7 (VolatileRegisters->Dr7);
}
}
+
+ AsmWriteGdtr (&VolatileRegisters->Gdtr);
+ AsmWriteIdtr (&VolatileRegisters->Idtr);
+ if (VolatileRegisters->Tr != 0 &&
+ VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {
+ Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
+ VolatileRegisters->Tr);
+ if (Tss->Bits.P == 1) {
+ Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case
+ AsmWriteTr (VolatileRegisters->Tr);
+ }
+ }
}
/**
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index d13d5c06f5..685e96cbac 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -102,6 +102,9 @@ typedef struct {
UINTN Dr3;
UINTN Dr6;
UINTN Dr7;
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ UINT16 Tr;
} CPU_VOLATILE_REGISTERS;
//
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
` (5 preceding siblings ...)
2017-11-22 8:45 ` [PATCH v2 6/8] UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-23 5:50 ` Yao, Jiewen
2017-11-25 13:35 ` 答复: " Fan Jeff
2017-11-22 8:45 ` [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP Jian J Wang
2017-11-23 3:47 ` [PATCH v2 0/8] Implement stack guard feature Yao, Jiewen
8 siblings, 2 replies; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Star Zeng, Eric Dong, Jiewen Yao, Michael Kinney
> v2:
> a. Move common TSS structure and API definitions to BaseLib.h
> b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to setup stack
> switch. This can avoid allocating memory for it in this library.
> c. Add globals to reserve memory for stack switch initialized in early
> phase of DXE core.
> d. Remove the filter code used to exclude boot modes which doesn't support
> memory allocation because those memory can passed in by parameter now.
> e. Remove the nasm macro to define exception handler one by one and add a
> function to return the start address of each handler.
If Stack Guard is enabled and there's really a stack overflow happened during
boot, a Page Fault exception will be triggered. Because the stack is out of
usage, the exception handler, which shares the stack with normal UEFI driver,
cannot be executed and cannot dump the processor information.
Without those information, it's very difficult for the BIOS developers locate
the root cause of stack overflow. And without a workable stack, the developer
cannot event use single step to debug the UEFI driver with JTAG debugger.
In order to make sure the exception handler to execute normally after stack
overflow. We need separate stacks for exception handlers in case of unusable
stack.
IA processor allows to switch to a new stack during handling interrupt and
exception. But X64 and IA32 provides different ways to make it. X64 provides
interrupt stack table (IST) to allow maximum 7 different exceptions to have
new stack for its handler. IA32 doesn't have IST mechanism and can only use
task gate to do it since task switch allows to load a new stack through its
task-state segment (TSS).
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
.../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
.../DxeCpuExceptionHandlerLib.inf | 6 +
.../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
.../Ia32/ArchExceptionHandler.c | 167 +++++++++
.../Ia32/ArchInterruptDefs.h | 8 +
.../Ia32/ExceptionTssEntryAsm.nasm | 398 +++++++++++++++++++++
.../PeiCpuExceptionHandlerLib.inf | 1 +
.../SecPeiCpuExceptionHandlerLib.inf | 1 +
.../SmmCpuExceptionHandlerLib.inf | 1 +
.../X64/ArchExceptionHandler.c | 133 +++++++
.../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
11 files changed, 820 insertions(+), 1 deletion(-)
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 740a58828b..30334105d2 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -48,6 +48,32 @@
0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c, 0x83 } \
}
+#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
+ FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
+
+#define CPU_STACK_SWITCH_EXCEPTION_LIST \
+ FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
+
+#define CPU_KNOWN_GOOD_STACK_SIZE \
+ FixedPcdGet32 (PcdCpuKnownGoodStackSize)
+
+#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)
+
+#define IA32_GDT_TYPE_TSS 0x9
+#define IA32_GDT_ALIGNMENT 8
+
+typedef struct {
+ UINTN StackTop;
+ UINTN StackSize;
+ UINT8 *Exceptions;
+ UINTN ExceptionNumber;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_SEGMENT_DESCRIPTOR *GdtTable;
+ UINTN GdtSize;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+} EXCEPTION_STACK_SWITCH_DATA;
+
//
// Record exception handler information
//
@@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
);
+/**
+ Setup separate stack for specific exceptions.
+
+ @param[in] IdtTable IDT table base.
+**/
+EFI_STATUS
+EFIAPI
+ArchSetupExcpetionStack (
+ IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
+ );
+
+/**
+ Return address map of exception handler template so that C code can generate
+ exception tables. The template is only for exceptions using task gate instead
+ of interrupt gate.
+
+ @param AddressMap Pointer to a buffer where the address map is returned.
+**/
+VOID
+EFIAPI
+AsmGetTssTemplateMap (
+ OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+ );
+
#endif
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index f4a8d01c80..58e55a8a2e 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
@@ -47,6 +48,11 @@
PeiDxeSmmCpuException.c
DxeException.c
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index 31febec976..c0b2c615aa 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -25,6 +25,10 @@ UINTN mEnabledInterruptNum = 0;
EXCEPTION_HANDLER_DATA mExceptionHandlerData;
+UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
+ CPU_KNOWN_GOOD_STACK_SIZE] = {0};
+UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
+
/**
Common exception handler.
@@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
+ EFI_STATUS Status;
+ EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
+ IA32_DESCRIPTOR Idtr;
+ IA32_DESCRIPTOR Gdtr;
+
mExceptionHandlerData.ReservedVectors = mReservedVectorsData;
mExceptionHandlerData.ExternalInterruptHandler = mExternalInterruptHandlerTable;
InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
- return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData);
+ Status = InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData);
+ if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
+ AsmReadIdtr (&Idtr);
+ AsmReadGdtr (&Gdtr);
+
+ StackSwitchData.StackTop = (UINTN)mNewStack;
+ StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
+ StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
+ StackSwitchData.ExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;
+ StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
+ StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
+ StackSwitchData.GdtSize = sizeof (mNewGdt);
+ StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt + Gdtr.Limit + 1);
+ StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt + Gdtr.Limit + 1 +
+ CPU_TSS_DESC_SIZE);
+ Status = InitializeCpuExceptionStackSwitchHandlers (
+ &StackSwitchData
+ );
+ }
+ return Status;
}
/**
@@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
{
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);
}
+
+/**
+ Setup separate stack for given exceptions. This is required by
+ PcdCpuStackGuard feature.
+
+ Note: For IA32 processor, StackSwitchData is a required parameter.
+
+ @param[in] StackSwitchData Pointer to data required for setuping up
+ stack switch.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionStackSwitchHandlers (
+ IN VOID *StackSwitchData OPTIONAL
+ )
+{
+ return ArchSetupExcpetionStack (StackSwitchData);
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index f2c39eb193..0aaf794795 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
SystemContext.SystemContextIa32->ExceptionData = ReservedVectors[ExceptionType].ExceptionData;
}
+/**
+ Setup separate stack for given exceptions.
+
+ @param[in] StackSwitchData Pointer to data required for setuping up
+ stack switch.
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.
+
+**/
+EFI_STATUS
+EFIAPI
+ArchSetupExcpetionStack (
+ IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
+ )
+{
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+ UINTN StackTop;
+ UINTN Index;
+ UINTN Vector;
+ UINTN TssBase;
+ UINTN GdtSize;
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
+
+ if (StackSwitchData == NULL ||
+ StackSwitchData->StackTop == 0 ||
+ StackSwitchData->StackSize == 0 ||
+ StackSwitchData->Exceptions == NULL ||
+ StackSwitchData->ExceptionNumber == 0 ||
+ StackSwitchData->GdtTable == NULL ||
+ StackSwitchData->IdtTable == NULL ||
+ StackSwitchData->TssDesc == NULL ||
+ StackSwitchData->Tss == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // The caller is responsible for that the GDT table, no matter the existing
+ // one or newly allocated, has enough space to hold descriptors for exception
+ // task-state segments.
+ //
+ if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc >=
+ ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GdtSize = (UINTN)StackSwitchData->TssDesc -
+ (UINTN)(StackSwitchData->GdtTable) +
+ sizeof (IA32_TSS_DESCRIPTOR) *
+ (StackSwitchData->ExceptionNumber + 1);
+ if (GdtSize > StackSwitchData->GdtSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize new GDT table and/or IDT table, if any
+ //
+ AsmReadIdtr (&Idtr);
+ AsmReadGdtr (&Gdtr);
+ if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
+ CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
+ Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
+ Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
+ }
+
+ if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
+ Idtr.Base = (UINTN)StackSwitchData->IdtTable;
+ }
+
+ //
+ // Fixup current task descriptor. Task-state segment for current task will
+ // be filled by processor during task switching.
+ //
+ TssDesc = StackSwitchData->TssDesc;
+ Tss = StackSwitchData->Tss;
+
+ TssBase = (UINTN)Tss;
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
+
+ //
+ // Fixup exception task descriptor and task-state segment
+ //
+ AsmGetTssTemplateMap (&TemplateMap);
+ StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
+ StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
+ IdtTable = StackSwitchData->IdtTable;
+ for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
+ TssDesc += 1;
+ Tss += 1;
+
+ //
+ // Fixup TSS descriptor
+ //
+ TssBase = (UINTN)Tss;
+
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
+
+ //
+ // Fixup TSS
+ //
+ Vector = StackSwitchData->Exceptions[Index];
+ Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
+ + Vector * TemplateMap.ExceptionStubHeaderSize);
+ Tss->EFLAGS = 0x2;
+ Tss->ESP = StackTop;
+ Tss->CR3 = AsmReadCr3 ();
+ Tss->ES = AsmReadEs ();
+ Tss->CS = AsmReadCs ();
+ Tss->SS = AsmReadSs ();
+ Tss->DS = AsmReadDs ();
+ Tss->FS = AsmReadFs ();
+ Tss->GS = AsmReadGs ();
+
+ StackTop -= StackSwitchData->StackSize;
+
+ //
+ // Update IDT to use Task Gate for given exception
+ //
+ IdtTable[Vector].Bits.OffsetLow = 0;
+ IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc - Gdtr.Base);
+ IdtTable[Vector].Bits.Reserved_0 = 0;
+ IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
+ IdtTable[Vector].Bits.OffsetHigh = 0;
+ }
+
+ //
+ // Publish GDT
+ //
+ AsmWriteGdtr (&Gdtr);
+
+ //
+ // Load current task
+ //
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
+
+ //
+ // Publish IDT
+ //
+ AsmWriteIdtr (&Idtr);
+
+ return EFI_SUCCESS;
+}
+
/**
Display processor context.
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
index a8d3556a80..d9ded5977f 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
@@ -41,4 +41,12 @@ typedef struct {
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA;
+#define CPU_TSS_DESC_SIZE \
+ (sizeof (IA32_TSS_DESCRIPTOR) * \
+ (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
+
+#define CPU_TSS_SIZE \
+ (sizeof (IA32_TASK_STATE_SEGMENT) * \
+ (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
+
#endif
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
new file mode 100644
index 0000000000..62bcedea1a
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
@@ -0,0 +1,398 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; ExceptionTssEntryAsm.Asm
+;
+; Abstract:
+;
+; IA32 CPU Exception Handler with Separate Stack
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+;
+; IA32 TSS Memory Layout Description
+;
+struc IA32_TSS
+ resw 1
+ resw 1
+ .ESP0: resd 1
+ .SS0: resw 1
+ resw 1
+ .ESP1: resd 1
+ .SS1: resw 1
+ resw 1
+ .ESP2: resd 1
+ .SS2: resw 1
+ resw 1
+ ._CR3: resd 1
+ .EIP: resd 1
+ .EFLAGS: resd 1
+ ._EAX: resd 1
+ ._ECX: resd 1
+ ._EDX: resd 1
+ ._EBX: resd 1
+ ._ESP: resd 1
+ ._EBP: resd 1
+ ._ESI: resd 1
+ ._EDI: resd 1
+ ._ES: resw 1
+ resw 1
+ ._CS: resw 1
+ resw 1
+ ._SS: resw 1
+ resw 1
+ ._DS: resw 1
+ resw 1
+ ._FS: resw 1
+ resw 1
+ ._GS: resw 1
+ resw 1
+ .LDT: resw 1
+ resw 1
+ resw 1
+ resw 1
+endstruc
+
+;
+; CommonExceptionHandler()
+;
+extern ASM_PFX(CommonExceptionHandler)
+
+SECTION .data
+
+SECTION .text
+
+ALIGN 8
+
+;
+; Exception handler stub table
+;
+AsmExceptionEntryBegin:
+%assign Vector 0
+%rep 32
+
+DoIret%[Vector]:
+ iretd
+ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
+ db 0x6a ; push #VectorNum
+ db %[Vector]
+ mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
+ call eax
+ mov esp, eax ; Restore stack top
+ jmp DoIret%[Vector]
+
+%assign Vector Vector+1
+%endrep
+AsmExceptionEntryEnd:
+
+;
+; Common part of exception handler
+;
+global ASM_PFX(CommonTaskSwtichEntryPoint)
+ASM_PFX(CommonTaskSwtichEntryPoint):
+ ;
+ ; Stack:
+ ; +---------------------+ <-- EBP - 8
+ ; + TSS Base +
+ ; +---------------------+ <-- EBP - 4
+ ; + CPUID.EDX +
+ ; +---------------------+ <-- EBP
+ ; + EIP +
+ ; +---------------------+ <-- EBP + 4
+ ; + Vector Number +
+ ; +---------------------+ <-- EBP + 8
+ ; + Error Code +
+ ; +---------------------+
+ ;
+
+ mov ebp, esp ; Stack frame
+
+; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
+ mov eax, 1
+ cpuid
+ push edx
+
+; Get TSS base of interrupted task through PreviousTaskLink field in
+; current TSS base
+ sub esp, 8
+ sgdt [esp + 2]
+ mov eax, [esp + 4] ; GDT base
+ add esp, 8
+
+ xor ebx, ebx
+ str bx ; Current TR
+
+ mov ecx, [eax + ebx + 2]
+ shl ecx, 8
+ mov cl, [eax + ebx + 7]
+ ror ecx, 8 ; ecx = Current TSS base
+ push ecx ; keep it in stack for later use
+
+ movzx ebx, word [ecx] ; Previous Task Link
+ mov ecx, [eax + ebx + 2]
+ shl ecx, 8
+ mov cl, [eax + ebx + 7]
+ ror ecx, 8 ; ecx = Previous TSS base
+
+;
+; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
+; is 16-byte aligned
+;
+ and esp, 0xfffffff0
+ sub esp, 12
+
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ push dword [ecx + IA32_TSS._EAX]
+ push dword [ecx + IA32_TSS._ECX]
+ push dword [ecx + IA32_TSS._EDX]
+ push dword [ecx + IA32_TSS._EBX]
+ push dword [ecx + IA32_TSS._ESP]
+ push dword [ecx + IA32_TSS._EBP]
+ push dword [ecx + IA32_TSS._ESI]
+ push dword [ecx + IA32_TSS._EDI]
+
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+ movzx eax, word [ecx + IA32_TSS._SS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._CS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._DS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._ES]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._FS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._GS]
+ push eax
+
+;; UINT32 Eip;
+ push dword [ecx + IA32_TSS.EIP]
+
+;; UINT32 Gdtr[2], Idtr[2];
+ sub esp, 8
+ sidt [esp]
+ mov eax, [esp + 2]
+ xchg eax, [esp]
+ and eax, 0xFFFF
+ mov [esp+4], eax
+
+ sub esp, 8
+ sgdt [esp]
+ mov eax, [esp + 2]
+ xchg eax, [esp]
+ and eax, 0xFFFF
+ mov [esp+4], eax
+
+;; UINT32 Ldtr, Tr;
+ mov eax, ebx ; ebx still keeps selector of interrupted task
+ push eax
+ movzx eax, word [ecx + IA32_TSS.LDT]
+ push eax
+
+;; UINT32 EFlags;
+ push dword [ecx + IA32_TSS.EFLAGS]
+
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ mov eax, cr4
+ push eax ; push cr4 firstly
+
+ mov edx, [ebp - 4] ; cpuid.edx
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
+ jz .1
+ or eax, BIT9 ; Set CR4.OSFXSR
+.1:
+ test edx, BIT2 ; Test for Debugging Extensions support
+ jz .2
+ or eax, BIT3 ; Set CR4.DE
+.2:
+ mov cr4, eax
+
+ mov eax, cr3
+ push eax
+ mov eax, cr2
+ push eax
+ xor eax, eax
+ push eax
+ mov eax, cr0
+ push eax
+
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+ mov eax, dr7
+ push eax
+ mov eax, dr6
+ push eax
+ mov eax, dr3
+ push eax
+ mov eax, dr2
+ push eax
+ mov eax, dr1
+ push eax
+ mov eax, dr0
+ push eax
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
+;; when executing fxsave/fxrstor instruction
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
+ ; edx still contains result from CPUID above
+ jz .3
+ clts
+ sub esp, 512
+ mov edi, esp
+ db 0xf, 0xae, 0x7 ;fxsave [edi]
+.3:
+
+;; UINT32 ExceptionData;
+ push dword [ebp + 8]
+
+;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
+ cld
+
+;; call into exception handler
+ mov esi, ecx ; Keep TSS base to avoid overwrite
+ mov eax, ASM_PFX(CommonExceptionHandler)
+
+;; Prepare parameter and call
+ mov edx, esp
+ push edx ; EFI_SYSTEM_CONTEXT
+ push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
+
+ ;
+ ; Call External Exception Handler
+ ;
+ call eax
+ add esp, 8 ; Restore stack before calling
+ mov ecx, esi ; Restore TSS base
+
+;; UINT32 ExceptionData;
+ add esp, 4
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+ mov edx, [ebp - 4] ; cpuid.edx
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
+ jz .4
+ mov esi, esp
+ db 0xf, 0xae, 0xe ; fxrstor [esi]
+.4:
+ add esp, 512
+
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+;; Skip restoration of DRx registers to support debuggers
+;; that set breakpoints in interrupt/exception context
+ add esp, 4 * 6
+
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ pop eax
+ mov cr0, eax
+ add esp, 4 ; not for Cr1
+ pop eax
+ mov cr2, eax
+ pop eax
+ mov dword [ecx + IA32_TSS._CR3], eax
+ pop eax
+ mov cr4, eax
+
+;; UINT32 EFlags;
+ pop dword [ecx + IA32_TSS.EFLAGS]
+ mov ebx, dword [ecx + IA32_TSS.EFLAGS]
+ btr ebx, 9 ; Do 'cli'
+ mov dword [ecx + IA32_TSS.EFLAGS], ebx
+
+;; UINT32 Ldtr, Tr;
+;; UINT32 Gdtr[2], Idtr[2];
+;; Best not let anyone mess with these particular registers...
+ add esp, 24
+
+;; UINT32 Eip;
+ pop dword [ecx + IA32_TSS.EIP]
+
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+;; NOTE - modified segment registers could hang the debugger... We
+;; could attempt to insulate ourselves against this possibility,
+;; but that poses risks as well.
+;;
+ pop eax
+o16 mov [ecx + IA32_TSS._GS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._FS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._ES], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._DS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._CS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._SS], ax
+
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ pop dword [ecx + IA32_TSS._EDI]
+ pop dword [ecx + IA32_TSS._ESI]
+ add esp, 4 ; not for ebp
+ add esp, 4 ; not for esp
+ pop dword [ecx + IA32_TSS._EBX]
+ pop dword [ecx + IA32_TSS._EDX]
+ pop dword [ecx + IA32_TSS._ECX]
+ pop dword [ecx + IA32_TSS._EAX]
+
+; Set single step DB# to allow debugger to able to go back to the EIP
+; where the exception is triggered.
+
+;; Create return context for iretd in stub function
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
+ mov ebx, dword [ecx + IA32_TSS.EIP]
+ mov [eax - 0xc], ebx ; create EIP in old stack
+ movzx ebx, word [ecx + IA32_TSS._CS]
+ mov [eax - 0x8], ebx ; create CS in old stack
+ mov ebx, dword [ecx + IA32_TSS.EFLAGS]
+ bts ebx, 8
+ mov [eax - 0x4], ebx ; create eflags in old stack
+ mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
+ sub eax, 0xc ; minus 12 byte
+ mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
+
+;; Replace the EIP of interrupted task with stub function
+ mov eax, ASM_PFX(SingleStepStubFunction)
+ mov dword [ecx + IA32_TSS.EIP], eax
+
+ mov ecx, [ebp - 8] ; Get current TSS base
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack top
+ mov esp, ebp
+
+ ret
+
+global ASM_PFX(SingleStepStubFunction)
+ASM_PFX(SingleStepStubFunction):
+;
+; we need clean TS bit in CR0 to execute
+; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
+;
+ clts
+ iretd
+
+global ASM_PFX(AsmGetTssTemplateMap)
+ASM_PFX(AsmGetTssTemplateMap):
+ push ebp ; C prolog
+ mov ebp, esp
+ pushad
+
+ mov ebx, dword [ebp + 0x8]
+ mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
+ mov dword [ebx + 0x4], (AsmExceptionEntryEnd - AsmExceptionEntryBegin) / 32
+ mov dword [ebx + 0x8], 0
+
+ popad
+ pop ebp
+ ret
+
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
index 75443288a9..4c0d435136 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index d70a99c100..e5c03c16c9 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
index 634ffcb21d..56b875b7c8 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index 65f0cff680..214aafcc13 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
SystemContext.SystemContextX64->ExceptionData = ReservedVectors[ExceptionType].ExceptionData;
}
+/**
+ Setup separate stack for given exceptions.
+
+ @param[in] StackSwitchData Pointer to data required for setuping up
+ stack switch.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.
+
+**/
+EFI_STATUS
+EFIAPI
+ArchSetupExcpetionStack (
+ IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
+ )
+{
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+ UINTN StackTop;
+ UINTN Index;
+ UINTN TssBase;
+ UINTN GdtSize;
+
+ if (StackSwitchData == NULL ||
+ StackSwitchData->StackTop == 0 ||
+ StackSwitchData->StackSize == 0 ||
+ StackSwitchData->Exceptions == NULL ||
+ StackSwitchData->ExceptionNumber == 0 ||
+ StackSwitchData->GdtTable == NULL ||
+ StackSwitchData->IdtTable == NULL ||
+ StackSwitchData->TssDesc == NULL ||
+ StackSwitchData->Tss == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // The caller is responsible for that the GDT table, no matter the existing
+ // one or newly allocated, has enough space to hold descriptors for exception
+ // task-state segments.
+ //
+ if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc >=
+ ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GdtSize = (UINTN)StackSwitchData->TssDesc -
+ (UINTN)(StackSwitchData->GdtTable) +
+ sizeof (IA32_TSS_DESCRIPTOR);
+ if (GdtSize > StackSwitchData->GdtSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize new GDT table and/or IDT table, if any
+ //
+ AsmReadIdtr (&Idtr);
+ AsmReadGdtr (&Gdtr);
+ if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
+ CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
+ Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
+ Gdtr.Limit = (UINT16)GdtSize - 1;
+ }
+
+ if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
+ Idtr.Base = (UINTN)StackSwitchData->IdtTable;
+ }
+
+ //
+ // Fixup current task descriptor. Task-state segment for current task will
+ // be filled by processor during task switching.
+ //
+ TssDesc = StackSwitchData->TssDesc;
+ Tss = StackSwitchData->Tss;
+
+ TssBase = (UINTN)Tss;
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
+ TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
+
+ //
+ // Fixup exception task descriptor and task-state segment
+ //
+ StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
+ StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
+ IdtTable = StackSwitchData->IdtTable;
+ for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
+ //
+ // Fixup IST
+ //
+ Tss->IST[Index] = StackTop;
+ StackTop -= StackSwitchData->StackSize;
+
+ //
+ // Set the IST field to enable corresponding IST
+ //
+ IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 = (UINT8)(Index + 1);
+ }
+
+ //
+ // Publish GDT
+ //
+ AsmWriteGdtr (&Gdtr);
+
+ //
+ // Load current task
+ //
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
+
+ //
+ // Publish IDT
+ //
+ AsmWriteIdtr (&Idtr);
+
+ return EFI_SUCCESS;
+}
+
/**
Display CPU information.
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
index 906480134a..c88be46286 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
@@ -43,4 +43,7 @@ typedef struct {
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA;
+#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
+#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
+
#endif
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
` (6 preceding siblings ...)
2017-11-22 8:45 ` [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support Jian J Wang
@ 2017-11-22 8:45 ` Jian J Wang
2017-11-23 4:13 ` Yao, Jiewen
2017-11-23 3:47 ` [PATCH v2 0/8] Implement stack guard feature Yao, Jiewen
8 siblings, 1 reply; 35+ messages in thread
From: Jian J Wang @ 2017-11-22 8:45 UTC (permalink / raw)
To: edk2-devel; +Cc: Eric Dong, Laszlo Ersek, Jiewen Yao, Michael Kinney
> v2:
> Add code to reserve resources and initialize AP exception with stack
> switch besides BSP, if PcdCpuStackGuard is enabled.
In current MP implementation, BSP and AP shares the same exception
configuration. Stack switch required by Stack Guard feature needs that BSP
and AP have their own configuration. This patch adds code to ask BSP and AP
to do exception handler initialization separately.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
UefiCpuPkg/CpuDxe/CpuMp.c | 168 +++++++++++++++++++++++++++++++++++++++++++
UefiCpuPkg/CpuDxe/CpuMp.h | 12 ++++
3 files changed, 183 insertions(+)
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 3e8d196739..02f86b774c 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -81,6 +81,9 @@
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ## CONSUMES
[Depex]
TRUE
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
index b3c0178d07..6b2ceacb39 100644
--- a/UefiCpuPkg/CpuDxe/CpuMp.c
+++ b/UefiCpuPkg/CpuDxe/CpuMp.c
@@ -601,6 +601,169 @@ CollectBistDataFromHob (
}
}
+/**
+ Get GDT register content.
+
+ This function is mainly for AP purpose because AP may have different GDT
+ table than BSP.
+
+**/
+VOID
+EFIAPI
+GetGdtr (
+ IN OUT VOID *Buffer
+ )
+{
+ AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
+}
+
+/**
+ Initializes CPU exceptions handlers for the sake of stack switch requirement.
+
+ This function is a wrapper of InitializeCpuExceptionStackSwitchHandlers.
+ It's mainly for AP purpose because of EFI_AP_PROCEDURE API requirement.
+
+**/
+VOID
+EFIAPI
+InitializeExceptionStackSwitchHandlers (
+ IN OUT VOID *Buffer
+ )
+{
+ EXCEPTION_STACK_SWITCH_DATA *EssData;
+ IA32_DESCRIPTOR Idtr;
+ EFI_STATUS Status;
+
+ EssData = Buffer;
+ //
+ // We don't plan to replace IDT table with a new one, and we don't assume
+ // the AP's IDT is the same as BSP's IDT either.
+ //
+ AsmReadIdtr (&Idtr);
+ EssData->IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
+ Status = InitializeCpuExceptionStackSwitchHandlers (EssData);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Initializes MP exceptions handlers for the sake of stack switch requirement.
+
+ This function will allocate required resources for stack switch and pass
+ them through EXCEPTION_STACK_SWITCH_DATA to each logic processor.
+
+**/
+VOID
+InitializeMpExceptionStackSwitchHandlers (
+ VOID
+ )
+{
+ UINTN Index;
+ UINTN Bsp;
+ UINTN ExceptionNumber;
+ UINTN NewGdtSize;
+ UINTN NewStackSize;
+ IA32_DESCRIPTOR Gdtr;
+ EXCEPTION_STACK_SWITCH_DATA EssData;
+ UINT8 *GdtBuffer;
+ UINT8 *StackTop;
+
+ if (!PcdGetBool (PcdCpuStackGuard)) {
+ return;
+ }
+
+ ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
+ NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;
+
+ StackTop = AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors);
+ ASSERT (StackTop != NULL);
+ StackTop += NewStackSize * mNumberOfProcessors;
+
+ EssData.Exceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
+ EssData.ExceptionNumber = ExceptionNumber;
+ EssData.StackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
+
+ MpInitLibWhoAmI (&Bsp);
+ for (Index = 0; Index < mNumberOfProcessors; ++Index) {
+ //
+ // To support stack switch, we need to re-construct GDT but not IDT.
+ //
+ if (Index == Bsp) {
+ GetGdtr (&Gdtr);
+ } else {
+ //
+ // AP might have different size of GDT from BSP.
+ //
+ MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL);
+ }
+
+ //
+ // X64 needs only one TSS of current task working for all exceptions
+ // because of its IST feature. IA32 needs one TSS for each exception
+ // in addition to current task. Since AP is not supposed to allocate
+ // memory, we have to do it in BSP. To simplify the code, we allocate
+ // memory for IA32 case to cover both IA32 and X64 exception stack
+ // switch.
+ //
+ // Layout of memory to allocate for each processor:
+ // --------------------------------
+ // | Alignment | (just in case)
+ // --------------------------------
+ // | |
+ // | Original GDT |
+ // | |
+ // --------------------------------
+ // | Current task descriptor |
+ // --------------------------------
+ // | |
+ // | Exception task descriptors | X ExceptionNumber
+ // | |
+ // --------------------------------
+ // | Current task-state segment |
+ // --------------------------------
+ // | |
+ // | Exception task-state segment | X ExceptionNumber
+ // | |
+ // --------------------------------
+ //
+ NewGdtSize = sizeof (IA32_TSS_DESCRIPTOR) +
+ (Gdtr.Limit + 1) +
+ sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber + 1) +
+ sizeof (IA32_TASK_STATE_SEGMENT) * (ExceptionNumber + 1);
+ GdtBuffer = AllocateRuntimeZeroPool (NewGdtSize);
+ ASSERT (GdtBuffer != NULL);
+
+ EssData.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));
+ NewGdtSize -= ((UINT8 *)EssData.GdtTable - GdtBuffer);
+ EssData.GdtSize = NewGdtSize;
+
+ EssData.TssDesc = (IA32_TSS_DESCRIPTOR *)((UINTN)EssData.GdtTable +
+ Gdtr.Limit + 1);
+ EssData.Tss = (IA32_TASK_STATE_SEGMENT *)((UINTN)EssData.GdtTable +
+ Gdtr.Limit + 1 +
+ sizeof (IA32_TSS_DESCRIPTOR) *
+ (ExceptionNumber + 1));
+
+ EssData.StackTop = (UINTN)StackTop;
+ DEBUG ((DEBUG_INFO, "Exception stack top[%d]: 0x%lX\n", Index,
+ (UINT64)(UINTN)StackTop));
+
+ if (Index == Bsp) {
+ InitializeExceptionStackSwitchHandlers (&EssData);
+ } else {
+ MpInitLibStartupThisAP (
+ InitializeExceptionStackSwitchHandlers,
+ Index,
+ NULL,
+ 0,
+ (VOID *)&EssData,
+ NULL
+ );
+ }
+
+ StackTop -= NewStackSize;
+ }
+}
+
/**
Initialize Multi-processor support.
@@ -624,6 +787,11 @@ InitializeMpSupport (
mNumberOfProcessors = NumberOfProcessors;
DEBUG ((DEBUG_INFO, "Detect CPU count: %d\n", mNumberOfProcessors));
+ //
+ // Initialize exception stack switch handlers for each logic processor.
+ //
+ InitializeMpExceptionStackSwitchHandlers ();
+
//
// Update CPU healthy information from Guided HOB
//
diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h
index d530149d7e..86d54a95e9 100644
--- a/UefiCpuPkg/CpuDxe/CpuMp.h
+++ b/UefiCpuPkg/CpuDxe/CpuMp.h
@@ -15,6 +15,18 @@
#ifndef _CPU_MP_H_
#define _CPU_MP_H_
+typedef struct {
+ UINTN StackTop;
+ UINTN StackSize;
+ UINT8 *Exceptions;
+ UINTN ExceptionNumber;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_SEGMENT_DESCRIPTOR *GdtTable;
+ UINTN GdtSize;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+} EXCEPTION_STACK_SWITCH_DATA;
+
/**
Initialize Multi-processor support.
--
2.14.1.windows.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH v2 0/8] Implement stack guard feature
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
` (7 preceding siblings ...)
2017-11-22 8:45 ` [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP Jian J Wang
@ 2017-11-23 3:47 ` Yao, Jiewen
2017-11-23 5:09 ` Wang, Jian J
8 siblings, 1 reply; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 3:47 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
For test, can we test boot OS (windows/Linux) with PcdCpuStackGuard enabled?
Thank you
Yao Jiewen
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian J
> Wang
> Sent: Wednesday, November 22, 2017 4:46 PM
> To: edk2-devel@lists.01.org
> Subject: [edk2] [PATCH v2 0/8] Implement stack guard feature
>
> Stack guard feature makes use of paging mechanism to monitor if there's a
> stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added to
> enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and
> PcdCpuKnownGoodStackSize are introduced to configure the required
> exceptions
> and stack size.
>
> If this feature is enabled, DxeIpl will setup page tables and set page where
> the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page
> Fault exception will be triggered.
>
> In order to make sure exception handler works normally even when the stack
> is corrupted, stack switching is implemented in exception library.
>
> Due to the mechanism behind Stack Guard, this feature is only avaiable for
> UEFI drivers (memory avaiable). That also means it doesn't support NT32
> emulated platform (paging not supported).
>
> Validation works include:
> a. OVMF emulated platform: boot to shell (IA32/X64)
> b. Intel real platform: boot to shell (IA32/X64)
>
> Jian J Wang (8):
> MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
> MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
> MdePkg/BaseLib: Add stack switch related definitions for IA32
> MdeModulePkg/DxeIpl: Enable paging for Stack Guard
> UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch
> UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data
> UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
> UefiCpuPkg/CpuDxe: Initialize stack switch for MP
>
> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +-
> MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +
> MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 +
> MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++-
> .../Include/Library/CpuExceptionHandlerLib.h | 18 +
> MdeModulePkg/MdeModulePkg.dec | 7 +
> MdeModulePkg/MdeModulePkg.uni | 7 +
> MdePkg/Include/Library/BaseLib.h | 115 ++++++
> MdePkg/Library/BaseLib/BaseLib.inf | 3 +
> MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++
> MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++
> UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> UefiCpuPkg/CpuDxe/CpuMp.c | 168 +++++++++
> UefiCpuPkg/CpuDxe/CpuMp.h | 12 +
> .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> .../DxeCpuExceptionHandlerLib.inf | 6 +
> .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> .../Ia32/ArchInterruptDefs.h | 8 +
> .../Ia32/ExceptionTssEntryAsm.nasm | 398
> +++++++++++++++++++++
> .../PeiCpuExceptionHandlerLib.inf | 1 +
> .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> .../SmmCpuExceptionHandlerLib.inf | 1 +
> .../X64/ArchExceptionHandler.c | 133 +++++++
> .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +
> UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +
> UefiCpuPkg/UefiCpuPkg.dec | 12 +
> 28 files changed, 1304 insertions(+), 16 deletions(-)
> create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
> create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm
> create mode 100644
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
>
> --
> 2.14.1.windows.1
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
2017-11-22 8:45 ` [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API Jian J Wang
@ 2017-11-23 4:07 ` Yao, Jiewen
2017-11-23 5:06 ` Wang, Jian J
0 siblings, 1 reply; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 4:07 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org; +Cc: Dong, Eric, Zeng, Star
Hi
I am a little worried about the way to use VOID * to pass arch dependent data.
Can we define it clearly in each ARCH in the header file, and use a UNION to include all arch?
I think both the caller and the callee need parse it. As such, VOID * is not a good way.
Thank you
Yao Jiewen
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian J
> Wang
> Sent: Wednesday, November 22, 2017 4:46 PM
> To: edk2-devel@lists.01.org
> Cc: Yao, Jiewen <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Zeng, Star <star.zeng@intel.com>
> Subject: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add
> a new API
>
> > v2:
> > Add prototype definition of InitializeCpuExceptionStackSwitchHandlers()
>
> A new API InitializeCpuExceptionStackSwitchHandlers() is introduced to support
> initializing exception handlers being able to switch stack. StackSwitchData is
> arch dependent and required by IA32 processor to convey resources reserved in
> advance. This is necessary because the CpuExceptionHandlerLib will be linked
> in different phases, in which there's no common way to reserve resources.
>
> EFI_STATUS
> EFIAPI
> InitializeCpuExceptionStackSwitchHandlers (
> IN VOID *StackSwitchData OPTIONAL
> );
>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> ---
> MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h | 18
> ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> index 6cd8230127..68de4850e1 100644
> --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> @@ -41,6 +41,24 @@ InitializeCpuExceptionHandlers (
> IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> );
>
> +/**
> + Setup separate stack for given exceptions. StackSwitchData is optional and its
> + content depends one the specific arch of CPU.
> +
> + @param[in] StackSwitchData Pointer to data required for setuping up
> + stack switch.
> +
> + @retval EFI_SUCCESS The exceptions have been successfully
> + initialized.
> + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> content.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuExceptionStackSwitchHandlers (
> + IN VOID *StackSwitchData OPTIONAL
> + );
> +
> /**
> Initializes all CPU interrupt/exceptions entries and provides the default
> interrupt/exception handlers.
>
> --
> 2.14.1.windows.1
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
2017-11-22 8:45 ` [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP Jian J Wang
@ 2017-11-23 4:13 ` Yao, Jiewen
2017-11-23 5:03 ` Wang, Jian J
0 siblings, 1 reply; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 4:13 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
Cc: Dong, Eric, Laszlo Ersek, Kinney, Michael D
Hi
1) Can we enable this feature in early DxeCore?
Current DxeCore still calling InitializeCpuExceptionHandlers().
But I hope InitializeExceptionStackSwitchHandlers() can be used here.
In order to handle buffer from different arch, the DxeIpl can help provide some data in hob and pass to DxeCore.
2) In addition, InitializeCpuExceptionHandlers () has VectorInfoList as parameter.
Do we also need that for InitializeExceptionStackSwitchHandlers()?
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wang, Jian J
> Sent: Wednesday, November 22, 2017 4:46 PM
> To: edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Yao,
> Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
>
> > v2:
> > Add code to reserve resources and initialize AP exception with stack
> > switch besides BSP, if PcdCpuStackGuard is enabled.
>
> In current MP implementation, BSP and AP shares the same exception
> configuration. Stack switch required by Stack Guard feature needs that BSP
> and AP have their own configuration. This patch adds code to ask BSP and AP
> to do exception handler initialization separately.
>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Michael Kinney <michael.d.kinney@intel.com>
> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> ---
> UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> UefiCpuPkg/CpuDxe/CpuMp.c | 168
> +++++++++++++++++++++++++++++++++++++++++++
> UefiCpuPkg/CpuDxe/CpuMp.h | 12 ++++
> 3 files changed, 183 insertions(+)
>
> diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> index 3e8d196739..02f86b774c 100644
> --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> @@ -81,6 +81,9 @@
>
> [Pcd]
>
> gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
> ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> ## CONSUMES
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> ## CONSUMES
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> ## CONSUMES
>
> [Depex]
> TRUE
> diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
> index b3c0178d07..6b2ceacb39 100644
> --- a/UefiCpuPkg/CpuDxe/CpuMp.c
> +++ b/UefiCpuPkg/CpuDxe/CpuMp.c
> @@ -601,6 +601,169 @@ CollectBistDataFromHob (
> }
> }
>
> +/**
> + Get GDT register content.
> +
> + This function is mainly for AP purpose because AP may have different GDT
> + table than BSP.
> +
> +**/
> +VOID
> +EFIAPI
> +GetGdtr (
> + IN OUT VOID *Buffer
> + )
> +{
> + AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
> +}
> +
> +/**
> + Initializes CPU exceptions handlers for the sake of stack switch requirement.
> +
> + This function is a wrapper of InitializeCpuExceptionStackSwitchHandlers.
> + It's mainly for AP purpose because of EFI_AP_PROCEDURE API requirement.
> +
> +**/
> +VOID
> +EFIAPI
> +InitializeExceptionStackSwitchHandlers (
> + IN OUT VOID *Buffer
> + )
> +{
> + EXCEPTION_STACK_SWITCH_DATA *EssData;
> + IA32_DESCRIPTOR Idtr;
> + EFI_STATUS Status;
> +
> + EssData = Buffer;
> + //
> + // We don't plan to replace IDT table with a new one, and we don't assume
> + // the AP's IDT is the same as BSP's IDT either.
> + //
> + AsmReadIdtr (&Idtr);
> + EssData->IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> + Status = InitializeCpuExceptionStackSwitchHandlers (EssData);
> + ASSERT_EFI_ERROR (Status);
> +}
> +
> +/**
> + Initializes MP exceptions handlers for the sake of stack switch requirement.
> +
> + This function will allocate required resources for stack switch and pass
> + them through EXCEPTION_STACK_SWITCH_DATA to each logic processor.
> +
> +**/
> +VOID
> +InitializeMpExceptionStackSwitchHandlers (
> + VOID
> + )
> +{
> + UINTN Index;
> + UINTN Bsp;
> + UINTN ExceptionNumber;
> + UINTN NewGdtSize;
> + UINTN NewStackSize;
> + IA32_DESCRIPTOR Gdtr;
> + EXCEPTION_STACK_SWITCH_DATA EssData;
> + UINT8 *GdtBuffer;
> + UINT8 *StackTop;
> +
> + if (!PcdGetBool (PcdCpuStackGuard)) {
> + return;
> + }
> +
> + ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
> + NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) *
> ExceptionNumber;
> +
> + StackTop = AllocateRuntimeZeroPool (NewStackSize *
> mNumberOfProcessors);
> + ASSERT (StackTop != NULL);
> + StackTop += NewStackSize * mNumberOfProcessors;
> +
> + EssData.Exceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
> + EssData.ExceptionNumber = ExceptionNumber;
> + EssData.StackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
> +
> + MpInitLibWhoAmI (&Bsp);
> + for (Index = 0; Index < mNumberOfProcessors; ++Index) {
> + //
> + // To support stack switch, we need to re-construct GDT but not IDT.
> + //
> + if (Index == Bsp) {
> + GetGdtr (&Gdtr);
> + } else {
> + //
> + // AP might have different size of GDT from BSP.
> + //
> + MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL);
> + }
> +
> + //
> + // X64 needs only one TSS of current task working for all exceptions
> + // because of its IST feature. IA32 needs one TSS for each exception
> + // in addition to current task. Since AP is not supposed to allocate
> + // memory, we have to do it in BSP. To simplify the code, we allocate
> + // memory for IA32 case to cover both IA32 and X64 exception stack
> + // switch.
> + //
> + // Layout of memory to allocate for each processor:
> + // --------------------------------
> + // | Alignment | (just in case)
> + // --------------------------------
> + // | |
> + // | Original GDT |
> + // | |
> + // --------------------------------
> + // | Current task descriptor |
> + // --------------------------------
> + // | |
> + // | Exception task descriptors | X ExceptionNumber
> + // | |
> + // --------------------------------
> + // | Current task-state segment |
> + // --------------------------------
> + // | |
> + // | Exception task-state segment | X ExceptionNumber
> + // | |
> + // --------------------------------
> + //
> + NewGdtSize = sizeof (IA32_TSS_DESCRIPTOR) +
> + (Gdtr.Limit + 1) +
> + sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber + 1) +
> + sizeof (IA32_TASK_STATE_SEGMENT) * (ExceptionNumber +
> 1);
> + GdtBuffer = AllocateRuntimeZeroPool (NewGdtSize);
> + ASSERT (GdtBuffer != NULL);
> +
> + EssData.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof
> (IA32_TSS_DESCRIPTOR));
> + NewGdtSize -= ((UINT8 *)EssData.GdtTable - GdtBuffer);
> + EssData.GdtSize = NewGdtSize;
> +
> + EssData.TssDesc = (IA32_TSS_DESCRIPTOR *)((UINTN)EssData.GdtTable +
> + Gdtr.Limit + 1);
> + EssData.Tss = (IA32_TASK_STATE_SEGMENT *)((UINTN)EssData.GdtTable +
> + Gdtr.Limit + 1 +
> + sizeof
> (IA32_TSS_DESCRIPTOR) *
> + (ExceptionNumber + 1));
> +
> + EssData.StackTop = (UINTN)StackTop;
> + DEBUG ((DEBUG_INFO, "Exception stack top[%d]: 0x%lX\n", Index,
> + (UINT64)(UINTN)StackTop));
> +
> + if (Index == Bsp) {
> + InitializeExceptionStackSwitchHandlers (&EssData);
> + } else {
> + MpInitLibStartupThisAP (
> + InitializeExceptionStackSwitchHandlers,
> + Index,
> + NULL,
> + 0,
> + (VOID *)&EssData,
> + NULL
> + );
> + }
> +
> + StackTop -= NewStackSize;
> + }
> +}
> +
> /**
> Initialize Multi-processor support.
>
> @@ -624,6 +787,11 @@ InitializeMpSupport (
> mNumberOfProcessors = NumberOfProcessors;
> DEBUG ((DEBUG_INFO, "Detect CPU count: %d\n", mNumberOfProcessors));
>
> + //
> + // Initialize exception stack switch handlers for each logic processor.
> + //
> + InitializeMpExceptionStackSwitchHandlers ();
> +
> //
> // Update CPU healthy information from Guided HOB
> //
> diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h
> index d530149d7e..86d54a95e9 100644
> --- a/UefiCpuPkg/CpuDxe/CpuMp.h
> +++ b/UefiCpuPkg/CpuDxe/CpuMp.h
> @@ -15,6 +15,18 @@
> #ifndef _CPU_MP_H_
> #define _CPU_MP_H_
>
> +typedef struct {
> + UINTN StackTop;
> + UINTN StackSize;
> + UINT8 *Exceptions;
> + UINTN ExceptionNumber;
> + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> + UINTN GdtSize;
> + IA32_TSS_DESCRIPTOR *TssDesc;
> + IA32_TASK_STATE_SEGMENT *Tss;
> +} EXCEPTION_STACK_SWITCH_DATA;
> +
> /**
> Initialize Multi-processor support.
>
> --
> 2.14.1.windows.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
2017-11-23 4:13 ` Yao, Jiewen
@ 2017-11-23 5:03 ` Wang, Jian J
2017-11-23 5:19 ` Wang, Jian J
0 siblings, 1 reply; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 5:03 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
Cc: Dong, Eric, Laszlo Ersek, Kinney, Michael D
Hi,
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 12:14 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
>
> Hi
> 1) Can we enable this feature in early DxeCore?
>
Yes. Intead of calling InitializeExceptionStackSwitchHandlers () directly in DxeCore,
InitializeCpuExceptionHandlers() calls InitializeExceptionStackSwitchHandlers().
I think it's reasonable to do this because InitializeExceptionStackSwitchHandlers()
is arch dependent. It'd be better not to call it in DxeCore. Another benefit is that
this can avoid backward compatibility issue introduced by new API, which hasn't
been implemented by cpu driver or lib of other archs.
> Current DxeCore still calling InitializeCpuExceptionHandlers().
> But I hope InitializeExceptionStackSwitchHandlers() can be used here.
>
> In order to handle buffer from different arch, the DxeIpl can help provide some
> data in hob and pass to DxeCore.
>
> 2) In addition, InitializeCpuExceptionHandlers () has VectorInfoList as parameter.
> Do we also need that for InitializeExceptionStackSwitchHandlers()?
>
I don't see the need. Do you have any use cases in mind?
> Thank you
> Yao Jiewen
>
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Wednesday, November 22, 2017 4:46 PM
> > To: edk2-devel@lists.01.org
> > Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>;
> Yao,
> > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>
> > Subject: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> >
> > > v2:
> > > Add code to reserve resources and initialize AP exception with stack
> > > switch besides BSP, if PcdCpuStackGuard is enabled.
> >
> > In current MP implementation, BSP and AP shares the same exception
> > configuration. Stack switch required by Stack Guard feature needs that BSP
> > and AP have their own configuration. This patch adds code to ask BSP and AP
> > to do exception handler initialization separately.
> >
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > ---
> > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> > UefiCpuPkg/CpuDxe/CpuMp.c | 168
> > +++++++++++++++++++++++++++++++++++++++++++
> > UefiCpuPkg/CpuDxe/CpuMp.h | 12 ++++
> > 3 files changed, 183 insertions(+)
> >
> > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > index 3e8d196739..02f86b774c 100644
> > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > @@ -81,6 +81,9 @@
> >
> > [Pcd]
> >
> > gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
> > ## CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > ## CONSUMES
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > ## CONSUMES
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > ## CONSUMES
> >
> > [Depex]
> > TRUE
> > diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
> > index b3c0178d07..6b2ceacb39 100644
> > --- a/UefiCpuPkg/CpuDxe/CpuMp.c
> > +++ b/UefiCpuPkg/CpuDxe/CpuMp.c
> > @@ -601,6 +601,169 @@ CollectBistDataFromHob (
> > }
> > }
> >
> > +/**
> > + Get GDT register content.
> > +
> > + This function is mainly for AP purpose because AP may have different GDT
> > + table than BSP.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +GetGdtr (
> > + IN OUT VOID *Buffer
> > + )
> > +{
> > + AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
> > +}
> > +
> > +/**
> > + Initializes CPU exceptions handlers for the sake of stack switch requirement.
> > +
> > + This function is a wrapper of InitializeCpuExceptionStackSwitchHandlers.
> > + It's mainly for AP purpose because of EFI_AP_PROCEDURE API requirement.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +InitializeExceptionStackSwitchHandlers (
> > + IN OUT VOID *Buffer
> > + )
> > +{
> > + EXCEPTION_STACK_SWITCH_DATA *EssData;
> > + IA32_DESCRIPTOR Idtr;
> > + EFI_STATUS Status;
> > +
> > + EssData = Buffer;
> > + //
> > + // We don't plan to replace IDT table with a new one, and we don't assume
> > + // the AP's IDT is the same as BSP's IDT either.
> > + //
> > + AsmReadIdtr (&Idtr);
> > + EssData->IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > + Status = InitializeCpuExceptionStackSwitchHandlers (EssData);
> > + ASSERT_EFI_ERROR (Status);
> > +}
> > +
> > +/**
> > + Initializes MP exceptions handlers for the sake of stack switch requirement.
> > +
> > + This function will allocate required resources for stack switch and pass
> > + them through EXCEPTION_STACK_SWITCH_DATA to each logic processor.
> > +
> > +**/
> > +VOID
> > +InitializeMpExceptionStackSwitchHandlers (
> > + VOID
> > + )
> > +{
> > + UINTN Index;
> > + UINTN Bsp;
> > + UINTN ExceptionNumber;
> > + UINTN NewGdtSize;
> > + UINTN NewStackSize;
> > + IA32_DESCRIPTOR Gdtr;
> > + EXCEPTION_STACK_SWITCH_DATA EssData;
> > + UINT8 *GdtBuffer;
> > + UINT8 *StackTop;
> > +
> > + if (!PcdGetBool (PcdCpuStackGuard)) {
> > + return;
> > + }
> > +
> > + ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
> > + NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) *
> > ExceptionNumber;
> > +
> > + StackTop = AllocateRuntimeZeroPool (NewStackSize *
> > mNumberOfProcessors);
> > + ASSERT (StackTop != NULL);
> > + StackTop += NewStackSize * mNumberOfProcessors;
> > +
> > + EssData.Exceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
> > + EssData.ExceptionNumber = ExceptionNumber;
> > + EssData.StackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
> > +
> > + MpInitLibWhoAmI (&Bsp);
> > + for (Index = 0; Index < mNumberOfProcessors; ++Index) {
> > + //
> > + // To support stack switch, we need to re-construct GDT but not IDT.
> > + //
> > + if (Index == Bsp) {
> > + GetGdtr (&Gdtr);
> > + } else {
> > + //
> > + // AP might have different size of GDT from BSP.
> > + //
> > + MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL);
> > + }
> > +
> > + //
> > + // X64 needs only one TSS of current task working for all exceptions
> > + // because of its IST feature. IA32 needs one TSS for each exception
> > + // in addition to current task. Since AP is not supposed to allocate
> > + // memory, we have to do it in BSP. To simplify the code, we allocate
> > + // memory for IA32 case to cover both IA32 and X64 exception stack
> > + // switch.
> > + //
> > + // Layout of memory to allocate for each processor:
> > + // --------------------------------
> > + // | Alignment | (just in case)
> > + // --------------------------------
> > + // | |
> > + // | Original GDT |
> > + // | |
> > + // --------------------------------
> > + // | Current task descriptor |
> > + // --------------------------------
> > + // | |
> > + // | Exception task descriptors | X ExceptionNumber
> > + // | |
> > + // --------------------------------
> > + // | Current task-state segment |
> > + // --------------------------------
> > + // | |
> > + // | Exception task-state segment | X ExceptionNumber
> > + // | |
> > + // --------------------------------
> > + //
> > + NewGdtSize = sizeof (IA32_TSS_DESCRIPTOR) +
> > + (Gdtr.Limit + 1) +
> > + sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber + 1) +
> > + sizeof (IA32_TASK_STATE_SEGMENT) * (ExceptionNumber +
> > 1);
> > + GdtBuffer = AllocateRuntimeZeroPool (NewGdtSize);
> > + ASSERT (GdtBuffer != NULL);
> > +
> > + EssData.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof
> > (IA32_TSS_DESCRIPTOR));
> > + NewGdtSize -= ((UINT8 *)EssData.GdtTable - GdtBuffer);
> > + EssData.GdtSize = NewGdtSize;
> > +
> > + EssData.TssDesc = (IA32_TSS_DESCRIPTOR *)((UINTN)EssData.GdtTable +
> > + Gdtr.Limit + 1);
> > + EssData.Tss = (IA32_TASK_STATE_SEGMENT *)((UINTN)EssData.GdtTable +
> > + Gdtr.Limit + 1 +
> > + sizeof
> > (IA32_TSS_DESCRIPTOR) *
> > + (ExceptionNumber + 1));
> > +
> > + EssData.StackTop = (UINTN)StackTop;
> > + DEBUG ((DEBUG_INFO, "Exception stack top[%d]: 0x%lX\n", Index,
> > + (UINT64)(UINTN)StackTop));
> > +
> > + if (Index == Bsp) {
> > + InitializeExceptionStackSwitchHandlers (&EssData);
> > + } else {
> > + MpInitLibStartupThisAP (
> > + InitializeExceptionStackSwitchHandlers,
> > + Index,
> > + NULL,
> > + 0,
> > + (VOID *)&EssData,
> > + NULL
> > + );
> > + }
> > +
> > + StackTop -= NewStackSize;
> > + }
> > +}
> > +
> > /**
> > Initialize Multi-processor support.
> >
> > @@ -624,6 +787,11 @@ InitializeMpSupport (
> > mNumberOfProcessors = NumberOfProcessors;
> > DEBUG ((DEBUG_INFO, "Detect CPU count: %d\n", mNumberOfProcessors));
> >
> > + //
> > + // Initialize exception stack switch handlers for each logic processor.
> > + //
> > + InitializeMpExceptionStackSwitchHandlers ();
> > +
> > //
> > // Update CPU healthy information from Guided HOB
> > //
> > diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h
> > index d530149d7e..86d54a95e9 100644
> > --- a/UefiCpuPkg/CpuDxe/CpuMp.h
> > +++ b/UefiCpuPkg/CpuDxe/CpuMp.h
> > @@ -15,6 +15,18 @@
> > #ifndef _CPU_MP_H_
> > #define _CPU_MP_H_
> >
> > +typedef struct {
> > + UINTN StackTop;
> > + UINTN StackSize;
> > + UINT8 *Exceptions;
> > + UINTN ExceptionNumber;
> > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > + UINTN GdtSize;
> > + IA32_TSS_DESCRIPTOR *TssDesc;
> > + IA32_TASK_STATE_SEGMENT *Tss;
> > +} EXCEPTION_STACK_SWITCH_DATA;
> > +
> > /**
> > Initialize Multi-processor support.
> >
> > --
> > 2.14.1.windows.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
2017-11-23 4:07 ` Yao, Jiewen
@ 2017-11-23 5:06 ` Wang, Jian J
2017-11-25 13:17 ` 答复: " Fan Jeff
0 siblings, 1 reply; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 5:06 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org; +Cc: Dong, Eric, Zeng, Star
Good idea. I think it should be defined in also in following file besides the new API
MdeModulePkg\Include\Library\CpuExceptionHandlerLib.h
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 12:08 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: RE: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h:
> Add a new API
>
> Hi
> I am a little worried about the way to use VOID * to pass arch dependent data.
>
> Can we define it clearly in each ARCH in the header file, and use a UNION to
> include all arch?
>
> I think both the caller and the callee need parse it. As such, VOID * is not a good
> way.
>
> Thank you
> Yao Jiewen
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian
> J
> > Wang
> > Sent: Wednesday, November 22, 2017 4:46 PM
> > To: edk2-devel@lists.01.org
> > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Zeng, Star <star.zeng@intel.com>
> > Subject: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h:
> Add
> > a new API
> >
> > > v2:
> > > Add prototype definition of InitializeCpuExceptionStackSwitchHandlers()
> >
> > A new API InitializeCpuExceptionStackSwitchHandlers() is introduced to
> support
> > initializing exception handlers being able to switch stack. StackSwitchData is
> > arch dependent and required by IA32 processor to convey resources reserved
> in
> > advance. This is necessary because the CpuExceptionHandlerLib will be linked
> > in different phases, in which there's no common way to reserve resources.
> >
> > EFI_STATUS
> > EFIAPI
> > InitializeCpuExceptionStackSwitchHandlers (
> > IN VOID *StackSwitchData OPTIONAL
> > );
> >
> > Cc: Star Zeng <star.zeng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > ---
> > MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h | 18
> > ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > index 6cd8230127..68de4850e1 100644
> > --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > @@ -41,6 +41,24 @@ InitializeCpuExceptionHandlers (
> > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > );
> >
> > +/**
> > + Setup separate stack for given exceptions. StackSwitchData is optional and
> its
> > + content depends one the specific arch of CPU.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping up
> > + stack switch.
> > +
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +InitializeCpuExceptionStackSwitchHandlers (
> > + IN VOID *StackSwitchData OPTIONAL
> > + );
> > +
> > /**
> > Initializes all CPU interrupt/exceptions entries and provides the default
> > interrupt/exception handlers.
> >
> > --
> > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 0/8] Implement stack guard feature
2017-11-23 3:47 ` [PATCH v2 0/8] Implement stack guard feature Yao, Jiewen
@ 2017-11-23 5:09 ` Wang, Jian J
2017-11-23 5:40 ` Yao, Jiewen
0 siblings, 1 reply; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 5:09 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
I did test it with disabled. I'll try it enabled. Do you think this feature should be enabled
by default or not, just like the PcdCpuSmmStackGuard?
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 11:48 AM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Subject: RE: [edk2] [PATCH v2 0/8] Implement stack guard feature
>
> For test, can we test boot OS (windows/Linux) with PcdCpuStackGuard enabled?
>
> Thank you
> Yao Jiewen
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian
> J
> > Wang
> > Sent: Wednesday, November 22, 2017 4:46 PM
> > To: edk2-devel@lists.01.org
> > Subject: [edk2] [PATCH v2 0/8] Implement stack guard feature
> >
> > Stack guard feature makes use of paging mechanism to monitor if there's a
> > stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added
> to
> > enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and
> > PcdCpuKnownGoodStackSize are introduced to configure the required
> > exceptions
> > and stack size.
> >
> > If this feature is enabled, DxeIpl will setup page tables and set page where
> > the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page
> > Fault exception will be triggered.
> >
> > In order to make sure exception handler works normally even when the stack
> > is corrupted, stack switching is implemented in exception library.
> >
> > Due to the mechanism behind Stack Guard, this feature is only avaiable for
> > UEFI drivers (memory avaiable). That also means it doesn't support NT32
> > emulated platform (paging not supported).
> >
> > Validation works include:
> > a. OVMF emulated platform: boot to shell (IA32/X64)
> > b. Intel real platform: boot to shell (IA32/X64)
> >
> > Jian J Wang (8):
> > MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
> > MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
> > MdePkg/BaseLib: Add stack switch related definitions for IA32
> > MdeModulePkg/DxeIpl: Enable paging for Stack Guard
> > UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch
> > UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data
> > UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
> > UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> >
> > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +-
> > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +
> > MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 +
> > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++-
> > .../Include/Library/CpuExceptionHandlerLib.h | 18 +
> > MdeModulePkg/MdeModulePkg.dec | 7 +
> > MdeModulePkg/MdeModulePkg.uni | 7 +
> > MdePkg/Include/Library/BaseLib.h | 115 ++++++
> > MdePkg/Library/BaseLib/BaseLib.inf | 3 +
> > MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++
> > MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++
> > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> > UefiCpuPkg/CpuDxe/CpuMp.c | 168 +++++++++
> > UefiCpuPkg/CpuDxe/CpuMp.h | 12 +
> > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > .../Ia32/ArchInterruptDefs.h | 8 +
> > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > +++++++++++++++++++++
> > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > .../X64/ArchExceptionHandler.c | 133 +++++++
> > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +
> > UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +
> > UefiCpuPkg/UefiCpuPkg.dec | 12 +
> > 28 files changed, 1304 insertions(+), 16 deletions(-)
> > create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
> > create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm
> > create mode 100644
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> >
> > --
> > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
2017-11-23 5:03 ` Wang, Jian J
@ 2017-11-23 5:19 ` Wang, Jian J
2017-11-23 5:39 ` Yao, Jiewen
0 siblings, 1 reply; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 5:19 UTC (permalink / raw)
To: Wang, Jian J, Yao, Jiewen, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Laszlo Ersek, Dong, Eric
About 1), the code is in [PATCH v2 7/8]. Following is part of it.
@@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
+ EFI_STATUS Status;
+ EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
+ IA32_DESCRIPTOR Idtr;
+ IA32_DESCRIPTOR Gdtr;
+
mExceptionHandlerData.ReservedVectors = mReservedVectorsData;
mExceptionHandlerData.ExternalInterruptHandler = mExternalInterruptHandlerTable;
InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
- return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData);
+ Status = InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData);
+ if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
+ AsmReadIdtr (&Idtr);
+ AsmReadGdtr (&Gdtr);
+
+ StackSwitchData.StackTop = (UINTN)mNewStack;
+ StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
+ StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
+ StackSwitchData.ExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;
+ StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
+ StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
+ StackSwitchData.GdtSize = sizeof (mNewGdt);
+ StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt + Gdtr.Limit + 1);
+ StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt + Gdtr.Limit + 1 +
+ CPU_TSS_DESC_SIZE);
+ Status = InitializeCpuExceptionStackSwitchHandlers (
+ &StackSwitchData
+ );
+ }
+ return Status;
}
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Wang,
> Jian J
> Sent: Thursday, November 23, 2017 1:04 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Laszlo Ersek
> <lersek@redhat.com>; Dong, Eric <eric.dong@intel.com>
> Subject: Re: [edk2] [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch
> for MP
>
> Hi,
>
> > -----Original Message-----
> > From: Yao, Jiewen
> > Sent: Thursday, November 23, 2017 12:14 PM
> > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>;
> > Kinney, Michael D <michael.d.kinney@intel.com>
> > Subject: RE: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> >
> > Hi
> > 1) Can we enable this feature in early DxeCore?
> >
> Yes. Intead of calling InitializeExceptionStackSwitchHandlers () directly in
> DxeCore,
> InitializeCpuExceptionHandlers() calls InitializeExceptionStackSwitchHandlers().
>
> I think it's reasonable to do this because InitializeExceptionStackSwitchHandlers()
> is arch dependent. It'd be better not to call it in DxeCore. Another benefit is that
> this can avoid backward compatibility issue introduced by new API, which hasn't
> been implemented by cpu driver or lib of other archs.
>
> > Current DxeCore still calling InitializeCpuExceptionHandlers().
> > But I hope InitializeExceptionStackSwitchHandlers() can be used here.
> >
> > In order to handle buffer from different arch, the DxeIpl can help provide some
> > data in hob and pass to DxeCore.
> >
> > 2) In addition, InitializeCpuExceptionHandlers () has VectorInfoList as
> parameter.
> > Do we also need that for InitializeExceptionStackSwitchHandlers()?
> >
> I don't see the need. Do you have any use cases in mind?
>
> > Thank you
> > Yao Jiewen
> >
> > > -----Original Message-----
> > > From: Wang, Jian J
> > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > To: edk2-devel@lists.01.org
> > > Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>;
> > Yao,
> > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > <michael.d.kinney@intel.com>
> > > Subject: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> > >
> > > > v2:
> > > > Add code to reserve resources and initialize AP exception with stack
> > > > switch besides BSP, if PcdCpuStackGuard is enabled.
> > >
> > > In current MP implementation, BSP and AP shares the same exception
> > > configuration. Stack switch required by Stack Guard feature needs that BSP
> > > and AP have their own configuration. This patch adds code to ask BSP and AP
> > > to do exception handler initialization separately.
> > >
> > > Cc: Eric Dong <eric.dong@intel.com>
> > > Cc: Laszlo Ersek <lersek@redhat.com>
> > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > ---
> > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> > > UefiCpuPkg/CpuDxe/CpuMp.c | 168
> > > +++++++++++++++++++++++++++++++++++++++++++
> > > UefiCpuPkg/CpuDxe/CpuMp.h | 12 ++++
> > > 3 files changed, 183 insertions(+)
> > >
> > > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > index 3e8d196739..02f86b774c 100644
> > > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > @@ -81,6 +81,9 @@
> > >
> > > [Pcd]
> > >
> > >
> gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
> > > ## CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > ## CONSUMES
> > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > ## CONSUMES
> > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > ## CONSUMES
> > >
> > > [Depex]
> > > TRUE
> > > diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
> > > index b3c0178d07..6b2ceacb39 100644
> > > --- a/UefiCpuPkg/CpuDxe/CpuMp.c
> > > +++ b/UefiCpuPkg/CpuDxe/CpuMp.c
> > > @@ -601,6 +601,169 @@ CollectBistDataFromHob (
> > > }
> > > }
> > >
> > > +/**
> > > + Get GDT register content.
> > > +
> > > + This function is mainly for AP purpose because AP may have different GDT
> > > + table than BSP.
> > > +
> > > +**/
> > > +VOID
> > > +EFIAPI
> > > +GetGdtr (
> > > + IN OUT VOID *Buffer
> > > + )
> > > +{
> > > + AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
> > > +}
> > > +
> > > +/**
> > > + Initializes CPU exceptions handlers for the sake of stack switch
> requirement.
> > > +
> > > + This function is a wrapper of InitializeCpuExceptionStackSwitchHandlers.
> > > + It's mainly for AP purpose because of EFI_AP_PROCEDURE API
> requirement.
> > > +
> > > +**/
> > > +VOID
> > > +EFIAPI
> > > +InitializeExceptionStackSwitchHandlers (
> > > + IN OUT VOID *Buffer
> > > + )
> > > +{
> > > + EXCEPTION_STACK_SWITCH_DATA *EssData;
> > > + IA32_DESCRIPTOR Idtr;
> > > + EFI_STATUS Status;
> > > +
> > > + EssData = Buffer;
> > > + //
> > > + // We don't plan to replace IDT table with a new one, and we don't
> assume
> > > + // the AP's IDT is the same as BSP's IDT either.
> > > + //
> > > + AsmReadIdtr (&Idtr);
> > > + EssData->IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > + Status = InitializeCpuExceptionStackSwitchHandlers (EssData);
> > > + ASSERT_EFI_ERROR (Status);
> > > +}
> > > +
> > > +/**
> > > + Initializes MP exceptions handlers for the sake of stack switch requirement.
> > > +
> > > + This function will allocate required resources for stack switch and pass
> > > + them through EXCEPTION_STACK_SWITCH_DATA to each logic processor.
> > > +
> > > +**/
> > > +VOID
> > > +InitializeMpExceptionStackSwitchHandlers (
> > > + VOID
> > > + )
> > > +{
> > > + UINTN Index;
> > > + UINTN Bsp;
> > > + UINTN ExceptionNumber;
> > > + UINTN NewGdtSize;
> > > + UINTN NewStackSize;
> > > + IA32_DESCRIPTOR Gdtr;
> > > + EXCEPTION_STACK_SWITCH_DATA EssData;
> > > + UINT8 *GdtBuffer;
> > > + UINT8 *StackTop;
> > > +
> > > + if (!PcdGetBool (PcdCpuStackGuard)) {
> > > + return;
> > > + }
> > > +
> > > + ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
> > > + NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) *
> > > ExceptionNumber;
> > > +
> > > + StackTop = AllocateRuntimeZeroPool (NewStackSize *
> > > mNumberOfProcessors);
> > > + ASSERT (StackTop != NULL);
> > > + StackTop += NewStackSize * mNumberOfProcessors;
> > > +
> > > + EssData.Exceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
> > > + EssData.ExceptionNumber = ExceptionNumber;
> > > + EssData.StackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
> > > +
> > > + MpInitLibWhoAmI (&Bsp);
> > > + for (Index = 0; Index < mNumberOfProcessors; ++Index) {
> > > + //
> > > + // To support stack switch, we need to re-construct GDT but not IDT.
> > > + //
> > > + if (Index == Bsp) {
> > > + GetGdtr (&Gdtr);
> > > + } else {
> > > + //
> > > + // AP might have different size of GDT from BSP.
> > > + //
> > > + MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr, NULL);
> > > + }
> > > +
> > > + //
> > > + // X64 needs only one TSS of current task working for all exceptions
> > > + // because of its IST feature. IA32 needs one TSS for each exception
> > > + // in addition to current task. Since AP is not supposed to allocate
> > > + // memory, we have to do it in BSP. To simplify the code, we allocate
> > > + // memory for IA32 case to cover both IA32 and X64 exception stack
> > > + // switch.
> > > + //
> > > + // Layout of memory to allocate for each processor:
> > > + // --------------------------------
> > > + // | Alignment | (just in case)
> > > + // --------------------------------
> > > + // | |
> > > + // | Original GDT |
> > > + // | |
> > > + // --------------------------------
> > > + // | Current task descriptor |
> > > + // --------------------------------
> > > + // | |
> > > + // | Exception task descriptors | X ExceptionNumber
> > > + // | |
> > > + // --------------------------------
> > > + // | Current task-state segment |
> > > + // --------------------------------
> > > + // | |
> > > + // | Exception task-state segment | X ExceptionNumber
> > > + // | |
> > > + // --------------------------------
> > > + //
> > > + NewGdtSize = sizeof (IA32_TSS_DESCRIPTOR) +
> > > + (Gdtr.Limit + 1) +
> > > + sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber + 1) +
> > > + sizeof (IA32_TASK_STATE_SEGMENT) * (ExceptionNumber +
> > > 1);
> > > + GdtBuffer = AllocateRuntimeZeroPool (NewGdtSize);
> > > + ASSERT (GdtBuffer != NULL);
> > > +
> > > + EssData.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof
> > > (IA32_TSS_DESCRIPTOR));
> > > + NewGdtSize -= ((UINT8 *)EssData.GdtTable - GdtBuffer);
> > > + EssData.GdtSize = NewGdtSize;
> > > +
> > > + EssData.TssDesc = (IA32_TSS_DESCRIPTOR *)((UINTN)EssData.GdtTable +
> > > + Gdtr.Limit + 1);
> > > + EssData.Tss = (IA32_TASK_STATE_SEGMENT *)((UINTN)EssData.GdtTable
> +
> > > + Gdtr.Limit + 1 +
> > > + sizeof
> > > (IA32_TSS_DESCRIPTOR) *
> > > + (ExceptionNumber + 1));
> > > +
> > > + EssData.StackTop = (UINTN)StackTop;
> > > + DEBUG ((DEBUG_INFO, "Exception stack top[%d]: 0x%lX\n", Index,
> > > + (UINT64)(UINTN)StackTop));
> > > +
> > > + if (Index == Bsp) {
> > > + InitializeExceptionStackSwitchHandlers (&EssData);
> > > + } else {
> > > + MpInitLibStartupThisAP (
> > > + InitializeExceptionStackSwitchHandlers,
> > > + Index,
> > > + NULL,
> > > + 0,
> > > + (VOID *)&EssData,
> > > + NULL
> > > + );
> > > + }
> > > +
> > > + StackTop -= NewStackSize;
> > > + }
> > > +}
> > > +
> > > /**
> > > Initialize Multi-processor support.
> > >
> > > @@ -624,6 +787,11 @@ InitializeMpSupport (
> > > mNumberOfProcessors = NumberOfProcessors;
> > > DEBUG ((DEBUG_INFO, "Detect CPU count: %d\n",
> mNumberOfProcessors));
> > >
> > > + //
> > > + // Initialize exception stack switch handlers for each logic processor.
> > > + //
> > > + InitializeMpExceptionStackSwitchHandlers ();
> > > +
> > > //
> > > // Update CPU healthy information from Guided HOB
> > > //
> > > diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h
> > > index d530149d7e..86d54a95e9 100644
> > > --- a/UefiCpuPkg/CpuDxe/CpuMp.h
> > > +++ b/UefiCpuPkg/CpuDxe/CpuMp.h
> > > @@ -15,6 +15,18 @@
> > > #ifndef _CPU_MP_H_
> > > #define _CPU_MP_H_
> > >
> > > +typedef struct {
> > > + UINTN StackTop;
> > > + UINTN StackSize;
> > > + UINT8 *Exceptions;
> > > + UINTN ExceptionNumber;
> > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > + UINTN GdtSize;
> > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > +
> > > /**
> > > Initialize Multi-processor support.
> > >
> > > --
> > > 2.14.1.windows.1
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
2017-11-23 5:19 ` Wang, Jian J
@ 2017-11-23 5:39 ` Yao, Jiewen
0 siblings, 0 replies; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 5:39 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Laszlo Ersek, Dong, Eric
Got it. I like this idea.
It is better to hide it from DxeCore.
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wang, Jian J
> Sent: Thursday, November 23, 2017 1:19 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>;
> edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Laszlo Ersek
> <lersek@redhat.com>; Dong, Eric <eric.dong@intel.com>
> Subject: RE: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
>
> About 1), the code is in [PATCH v2 7/8]. Following is part of it.
>
> @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> )
> {
> + EFI_STATUS Status;
> + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> + IA32_DESCRIPTOR Idtr;
> + IA32_DESCRIPTOR Gdtr;
> +
> mExceptionHandlerData.ReservedVectors =
> mReservedVectorsData;
> mExceptionHandlerData.ExternalInterruptHandler =
> mExternalInterruptHandlerTable;
> InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> &mExceptionHandlerData);
> + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> &mExceptionHandlerData);
> + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> + AsmReadIdtr (&Idtr);
> + AsmReadGdtr (&Gdtr);
> +
> + StackSwitchData.StackTop = (UINTN)mNewStack;
> + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> + StackSwitchData.ExceptionNumber =
> CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
> + StackSwitchData.GdtSize = sizeof (mNewGdt);
> + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> Gdtr.Limit + 1);
> + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> Gdtr.Limit + 1 +
> +
> CPU_TSS_DESC_SIZE);
> + Status = InitializeCpuExceptionStackSwitchHandlers (
> + &StackSwitchData
> + );
> + }
> + return Status;
> }
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Wang,
> > Jian J
> > Sent: Thursday, November 23, 2017 1:04 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Laszlo Ersek
> > <lersek@redhat.com>; Dong, Eric <eric.dong@intel.com>
> > Subject: Re: [edk2] [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch
> > for MP
> >
> > Hi,
> >
> > > -----Original Message-----
> > > From: Yao, Jiewen
> > > Sent: Thursday, November 23, 2017 12:14 PM
> > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>;
> > > Kinney, Michael D <michael.d.kinney@intel.com>
> > > Subject: RE: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> > >
> > > Hi
> > > 1) Can we enable this feature in early DxeCore?
> > >
> > Yes. Intead of calling InitializeExceptionStackSwitchHandlers () directly in
> > DxeCore,
> > InitializeCpuExceptionHandlers() calls InitializeExceptionStackSwitchHandlers().
> >
> > I think it's reasonable to do this because
> InitializeExceptionStackSwitchHandlers()
> > is arch dependent. It'd be better not to call it in DxeCore. Another benefit is
> that
> > this can avoid backward compatibility issue introduced by new API, which hasn't
> > been implemented by cpu driver or lib of other archs.
> >
> > > Current DxeCore still calling InitializeCpuExceptionHandlers().
> > > But I hope InitializeExceptionStackSwitchHandlers() can be used here.
> > >
> > > In order to handle buffer from different arch, the DxeIpl can help provide
> some
> > > data in hob and pass to DxeCore.
> > >
> > > 2) In addition, InitializeCpuExceptionHandlers () has VectorInfoList as
> > parameter.
> > > Do we also need that for InitializeExceptionStackSwitchHandlers()?
> > >
> > I don't see the need. Do you have any use cases in mind?
> >
> > > Thank you
> > > Yao Jiewen
> > >
> > > > -----Original Message-----
> > > > From: Wang, Jian J
> > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > To: edk2-devel@lists.01.org
> > > > Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>;
> > > Yao,
> > > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > > <michael.d.kinney@intel.com>
> > > > Subject: [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> > > >
> > > > > v2:
> > > > > Add code to reserve resources and initialize AP exception with stack
> > > > > switch besides BSP, if PcdCpuStackGuard is enabled.
> > > >
> > > > In current MP implementation, BSP and AP shares the same exception
> > > > configuration. Stack switch required by Stack Guard feature needs that BSP
> > > > and AP have their own configuration. This patch adds code to ask BSP and
> AP
> > > > to do exception handler initialization separately.
> > > >
> > > > Cc: Eric Dong <eric.dong@intel.com>
> > > > Cc: Laszlo Ersek <lersek@redhat.com>
> > > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > > ---
> > > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> > > > UefiCpuPkg/CpuDxe/CpuMp.c | 168
> > > > +++++++++++++++++++++++++++++++++++++++++++
> > > > UefiCpuPkg/CpuDxe/CpuMp.h | 12 ++++
> > > > 3 files changed, 183 insertions(+)
> > > >
> > > > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > index 3e8d196739..02f86b774c 100644
> > > > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > @@ -81,6 +81,9 @@
> > > >
> > > > [Pcd]
> > > >
> > > >
> >
> gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask
> > > > ## CONSUMES
> > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > ## CONSUMES
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > ## CONSUMES
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > ## CONSUMES
> > > >
> > > > [Depex]
> > > > TRUE
> > > > diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
> > > > index b3c0178d07..6b2ceacb39 100644
> > > > --- a/UefiCpuPkg/CpuDxe/CpuMp.c
> > > > +++ b/UefiCpuPkg/CpuDxe/CpuMp.c
> > > > @@ -601,6 +601,169 @@ CollectBistDataFromHob (
> > > > }
> > > > }
> > > >
> > > > +/**
> > > > + Get GDT register content.
> > > > +
> > > > + This function is mainly for AP purpose because AP may have different
> GDT
> > > > + table than BSP.
> > > > +
> > > > +**/
> > > > +VOID
> > > > +EFIAPI
> > > > +GetGdtr (
> > > > + IN OUT VOID *Buffer
> > > > + )
> > > > +{
> > > > + AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
> > > > +}
> > > > +
> > > > +/**
> > > > + Initializes CPU exceptions handlers for the sake of stack switch
> > requirement.
> > > > +
> > > > + This function is a wrapper of InitializeCpuExceptionStackSwitchHandlers.
> > > > + It's mainly for AP purpose because of EFI_AP_PROCEDURE API
> > requirement.
> > > > +
> > > > +**/
> > > > +VOID
> > > > +EFIAPI
> > > > +InitializeExceptionStackSwitchHandlers (
> > > > + IN OUT VOID *Buffer
> > > > + )
> > > > +{
> > > > + EXCEPTION_STACK_SWITCH_DATA *EssData;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + EFI_STATUS Status;
> > > > +
> > > > + EssData = Buffer;
> > > > + //
> > > > + // We don't plan to replace IDT table with a new one, and we don't
> > assume
> > > > + // the AP's IDT is the same as BSP's IDT either.
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + EssData->IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > > + Status = InitializeCpuExceptionStackSwitchHandlers (EssData);
> > > > + ASSERT_EFI_ERROR (Status);
> > > > +}
> > > > +
> > > > +/**
> > > > + Initializes MP exceptions handlers for the sake of stack switch
> requirement.
> > > > +
> > > > + This function will allocate required resources for stack switch and pass
> > > > + them through EXCEPTION_STACK_SWITCH_DATA to each logic
> processor.
> > > > +
> > > > +**/
> > > > +VOID
> > > > +InitializeMpExceptionStackSwitchHandlers (
> > > > + VOID
> > > > + )
> > > > +{
> > > > + UINTN Index;
> > > > + UINTN Bsp;
> > > > + UINTN ExceptionNumber;
> > > > + UINTN NewGdtSize;
> > > > + UINTN NewStackSize;
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + EXCEPTION_STACK_SWITCH_DATA EssData;
> > > > + UINT8 *GdtBuffer;
> > > > + UINT8 *StackTop;
> > > > +
> > > > + if (!PcdGetBool (PcdCpuStackGuard)) {
> > > > + return;
> > > > + }
> > > > +
> > > > + ExceptionNumber = FixedPcdGetSize
> (PcdCpuStackSwitchExceptionList);
> > > > + NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) *
> > > > ExceptionNumber;
> > > > +
> > > > + StackTop = AllocateRuntimeZeroPool (NewStackSize *
> > > > mNumberOfProcessors);
> > > > + ASSERT (StackTop != NULL);
> > > > + StackTop += NewStackSize * mNumberOfProcessors;
> > > > +
> > > > + EssData.Exceptions = FixedPcdGetPtr
> (PcdCpuStackSwitchExceptionList);
> > > > + EssData.ExceptionNumber = ExceptionNumber;
> > > > + EssData.StackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
> > > > +
> > > > + MpInitLibWhoAmI (&Bsp);
> > > > + for (Index = 0; Index < mNumberOfProcessors; ++Index) {
> > > > + //
> > > > + // To support stack switch, we need to re-construct GDT but not IDT.
> > > > + //
> > > > + if (Index == Bsp) {
> > > > + GetGdtr (&Gdtr);
> > > > + } else {
> > > > + //
> > > > + // AP might have different size of GDT from BSP.
> > > > + //
> > > > + MpInitLibStartupThisAP (GetGdtr, Index, NULL, 0, (VOID *)&Gdtr,
> NULL);
> > > > + }
> > > > +
> > > > + //
> > > > + // X64 needs only one TSS of current task working for all exceptions
> > > > + // because of its IST feature. IA32 needs one TSS for each exception
> > > > + // in addition to current task. Since AP is not supposed to allocate
> > > > + // memory, we have to do it in BSP. To simplify the code, we allocate
> > > > + // memory for IA32 case to cover both IA32 and X64 exception stack
> > > > + // switch.
> > > > + //
> > > > + // Layout of memory to allocate for each processor:
> > > > + // --------------------------------
> > > > + // | Alignment | (just in case)
> > > > + // --------------------------------
> > > > + // | |
> > > > + // | Original GDT |
> > > > + // | |
> > > > + // --------------------------------
> > > > + // | Current task descriptor |
> > > > + // --------------------------------
> > > > + // | |
> > > > + // | Exception task descriptors | X ExceptionNumber
> > > > + // | |
> > > > + // --------------------------------
> > > > + // | Current task-state segment |
> > > > + // --------------------------------
> > > > + // | |
> > > > + // | Exception task-state segment | X ExceptionNumber
> > > > + // | |
> > > > + // --------------------------------
> > > > + //
> > > > + NewGdtSize = sizeof (IA32_TSS_DESCRIPTOR) +
> > > > + (Gdtr.Limit + 1) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR) * (ExceptionNumber +
> 1) +
> > > > + sizeof (IA32_TASK_STATE_SEGMENT) *
> (ExceptionNumber +
> > > > 1);
> > > > + GdtBuffer = AllocateRuntimeZeroPool (NewGdtSize);
> > > > + ASSERT (GdtBuffer != NULL);
> > > > +
> > > > + EssData.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof
> > > > (IA32_TSS_DESCRIPTOR));
> > > > + NewGdtSize -= ((UINT8 *)EssData.GdtTable - GdtBuffer);
> > > > + EssData.GdtSize = NewGdtSize;
> > > > +
> > > > + EssData.TssDesc = (IA32_TSS_DESCRIPTOR
> *)((UINTN)EssData.GdtTable +
> > > > + Gdtr.Limit + 1);
> > > > + EssData.Tss = (IA32_TASK_STATE_SEGMENT
> *)((UINTN)EssData.GdtTable
> > +
> > > > + Gdtr.Limit + 1 +
> > > > + sizeof
> > > > (IA32_TSS_DESCRIPTOR) *
> > > > + (ExceptionNumber +
> 1));
> > > > +
> > > > + EssData.StackTop = (UINTN)StackTop;
> > > > + DEBUG ((DEBUG_INFO, "Exception stack top[%d]: 0x%lX\n", Index,
> > > > + (UINT64)(UINTN)StackTop));
> > > > +
> > > > + if (Index == Bsp) {
> > > > + InitializeExceptionStackSwitchHandlers (&EssData);
> > > > + } else {
> > > > + MpInitLibStartupThisAP (
> > > > + InitializeExceptionStackSwitchHandlers,
> > > > + Index,
> > > > + NULL,
> > > > + 0,
> > > > + (VOID *)&EssData,
> > > > + NULL
> > > > + );
> > > > + }
> > > > +
> > > > + StackTop -= NewStackSize;
> > > > + }
> > > > +}
> > > > +
> > > > /**
> > > > Initialize Multi-processor support.
> > > >
> > > > @@ -624,6 +787,11 @@ InitializeMpSupport (
> > > > mNumberOfProcessors = NumberOfProcessors;
> > > > DEBUG ((DEBUG_INFO, "Detect CPU count: %d\n",
> > mNumberOfProcessors));
> > > >
> > > > + //
> > > > + // Initialize exception stack switch handlers for each logic processor.
> > > > + //
> > > > + InitializeMpExceptionStackSwitchHandlers ();
> > > > +
> > > > //
> > > > // Update CPU healthy information from Guided HOB
> > > > //
> > > > diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h
> > > > index d530149d7e..86d54a95e9 100644
> > > > --- a/UefiCpuPkg/CpuDxe/CpuMp.h
> > > > +++ b/UefiCpuPkg/CpuDxe/CpuMp.h
> > > > @@ -15,6 +15,18 @@
> > > > #ifndef _CPU_MP_H_
> > > > #define _CPU_MP_H_
> > > >
> > > > +typedef struct {
> > > > + UINTN StackTop;
> > > > + UINTN StackSize;
> > > > + UINT8 *Exceptions;
> > > > + UINTN ExceptionNumber;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > + UINTN GdtSize;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > +
> > > > /**
> > > > Initialize Multi-processor support.
> > > >
> > > > --
> > > > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 0/8] Implement stack guard feature
2017-11-23 5:09 ` Wang, Jian J
@ 2017-11-23 5:40 ` Yao, Jiewen
2017-11-25 13:44 ` 答复: " Fan Jeff
0 siblings, 1 reply; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 5:40 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
If we do not see any compatibility problem with Linux or Windows, we can enable it by default.
Or we have to disable it by default.
It is always good to have a try. Let's see.
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wang, Jian J
> Sent: Thursday, November 23, 2017 1:09 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> Subject: RE: [edk2] [PATCH v2 0/8] Implement stack guard feature
>
> I did test it with disabled. I'll try it enabled. Do you think this feature should be
> enabled
> by default or not, just like the PcdCpuSmmStackGuard?
>
> > -----Original Message-----
> > From: Yao, Jiewen
> > Sent: Thursday, November 23, 2017 11:48 AM
> > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > Subject: RE: [edk2] [PATCH v2 0/8] Implement stack guard feature
> >
> > For test, can we test boot OS (windows/Linux) with PcdCpuStackGuard
> enabled?
> >
> > Thank you
> > Yao Jiewen
> >
> > > -----Original Message-----
> > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Jian
> > J
> > > Wang
> > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > To: edk2-devel@lists.01.org
> > > Subject: [edk2] [PATCH v2 0/8] Implement stack guard feature
> > >
> > > Stack guard feature makes use of paging mechanism to monitor if there's a
> > > stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added
> > to
> > > enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and
> > > PcdCpuKnownGoodStackSize are introduced to configure the required
> > > exceptions
> > > and stack size.
> > >
> > > If this feature is enabled, DxeIpl will setup page tables and set page where
> > > the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page
> > > Fault exception will be triggered.
> > >
> > > In order to make sure exception handler works normally even when the stack
> > > is corrupted, stack switching is implemented in exception library.
> > >
> > > Due to the mechanism behind Stack Guard, this feature is only avaiable for
> > > UEFI drivers (memory avaiable). That also means it doesn't support NT32
> > > emulated platform (paging not supported).
> > >
> > > Validation works include:
> > > a. OVMF emulated platform: boot to shell (IA32/X64)
> > > b. Intel real platform: boot to shell (IA32/X64)
> > >
> > > Jian J Wang (8):
> > > MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
> > > MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
> > > MdePkg/BaseLib: Add stack switch related definitions for IA32
> > > MdeModulePkg/DxeIpl: Enable paging for Stack Guard
> > > UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch
> > > UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data
> > > UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
> > > UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> > >
> > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +-
> > > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +
> > > MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 +
> > > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++-
> > > .../Include/Library/CpuExceptionHandlerLib.h | 18 +
> > > MdeModulePkg/MdeModulePkg.dec | 7 +
> > > MdeModulePkg/MdeModulePkg.uni | 7 +
> > > MdePkg/Include/Library/BaseLib.h | 115 ++++++
> > > MdePkg/Library/BaseLib/BaseLib.inf | 3 +
> > > MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++
> > > MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++
> > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> > > UefiCpuPkg/CpuDxe/CpuMp.c | 168
> +++++++++
> > > UefiCpuPkg/CpuDxe/CpuMp.h | 12 +
> > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > +++++++++++++++++++++
> > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +
> > > UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +
> > > UefiCpuPkg/UefiCpuPkg.dec | 12 +
> > > 28 files changed, 1304 insertions(+), 16 deletions(-)
> > > create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
> > > create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm
> > > create mode 100644
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > >
> > > --
> > > 2.14.1.windows.1
> > >
> > > _______________________________________________
> > > edk2-devel mailing list
> > > edk2-devel@lists.01.org
> > > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-22 8:45 ` [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support Jian J Wang
@ 2017-11-23 5:50 ` Yao, Jiewen
2017-11-23 5:59 ` Yao, Jiewen
2017-11-23 6:05 ` Wang, Jian J
2017-11-25 13:35 ` 答复: " Fan Jeff
1 sibling, 2 replies; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 5:50 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
Cc: Zeng, Star, Dong, Eric, Kinney, Michael D
Some thought:
1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented in DxeException.c.
What about Pei/Smm instance?
I think it is OK to not implement it at this moment. But we need make sure no architecture issue if we want to enable it some time later.
2) #define IA32_GDT_TYPE_TSS 0x9
This is generic, can we move to BaseLib.h?
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wang, Jian J
> Sent: Wednesday, November 22, 2017 4:46 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>; Yao,
> Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> support
>
> > v2:
> > a. Move common TSS structure and API definitions to BaseLib.h
> > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to setup
> stack
> > switch. This can avoid allocating memory for it in this library.
> > c. Add globals to reserve memory for stack switch initialized in early
> > phase of DXE core.
> > d. Remove the filter code used to exclude boot modes which doesn't
> support
> > memory allocation because those memory can passed in by parameter
> now.
> > e. Remove the nasm macro to define exception handler one by one and
> add a
> > function to return the start address of each handler.
>
> If Stack Guard is enabled and there's really a stack overflow happened during
> boot, a Page Fault exception will be triggered. Because the stack is out of
> usage, the exception handler, which shares the stack with normal UEFI driver,
> cannot be executed and cannot dump the processor information.
>
> Without those information, it's very difficult for the BIOS developers locate
> the root cause of stack overflow. And without a workable stack, the developer
> cannot event use single step to debug the UEFI driver with JTAG debugger.
>
> In order to make sure the exception handler to execute normally after stack
> overflow. We need separate stacks for exception handlers in case of unusable
> stack.
>
> IA processor allows to switch to a new stack during handling interrupt and
> exception. But X64 and IA32 provides different ways to make it. X64 provides
> interrupt stack table (IST) to allow maximum 7 different exceptions to have
> new stack for its handler. IA32 doesn't have IST mechanism and can only use
> task gate to do it since task switch allows to load a new stack through its
> task-state segment (TSS).
>
> Cc: Star Zeng <star.zeng@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Michael Kinney <michael.d.kinney@intel.com>
> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> ---
> .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> .../DxeCpuExceptionHandlerLib.inf | 6 +
> .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> .../Ia32/ArchInterruptDefs.h | 8 +
> .../Ia32/ExceptionTssEntryAsm.nasm | 398
> +++++++++++++++++++++
> .../PeiCpuExceptionHandlerLib.inf | 1 +
> .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> .../SmmCpuExceptionHandlerLib.inf | 1 +
> .../X64/ArchExceptionHandler.c | 133 +++++++
> .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> 11 files changed, 820 insertions(+), 1 deletion(-)
> create mode 100644
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> index 740a58828b..30334105d2 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> @@ -48,6 +48,32 @@
> 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c, 0x83 }
> \
> }
>
> +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> +
> +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> +
> +#define CPU_KNOWN_GOOD_STACK_SIZE \
> + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> +
> +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)
> +
> +#define IA32_GDT_TYPE_TSS 0x9
> +#define IA32_GDT_ALIGNMENT 8
> +
> +typedef struct {
> + UINTN StackTop;
> + UINTN StackSize;
> + UINT8 *Exceptions;
> + UINTN ExceptionNumber;
> + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> + UINTN GdtSize;
> + IA32_TSS_DESCRIPTOR *TssDesc;
> + IA32_TASK_STATE_SEGMENT *Tss;
> +} EXCEPTION_STACK_SWITCH_DATA;
> +
> //
> // Record exception handler information
> //
> @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> );
>
> +/**
> + Setup separate stack for specific exceptions.
> +
> + @param[in] IdtTable IDT table base.
> +**/
> +EFI_STATUS
> +EFIAPI
> +ArchSetupExcpetionStack (
> + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> + );
> +
> +/**
> + Return address map of exception handler template so that C code can
> generate
> + exception tables. The template is only for exceptions using task gate instead
> + of interrupt gate.
> +
> + @param AddressMap Pointer to a buffer where the address map is
> returned.
> +**/
> +VOID
> +EFIAPI
> +AsmGetTssTemplateMap (
> + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> + );
> +
> #endif
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> index f4a8d01c80..58e55a8a2e 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> @@ -30,6 +30,7 @@
> [Sources.Ia32]
> Ia32/ExceptionHandlerAsm.asm
> Ia32/ExceptionHandlerAsm.nasm
> + Ia32/ExceptionTssEntryAsm.nasm
> Ia32/ExceptionHandlerAsm.S
> Ia32/ArchExceptionHandler.c
> Ia32/ArchInterruptDefs.h
> @@ -47,6 +48,11 @@
> PeiDxeSmmCpuException.c
> DxeException.c
>
> +[Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> +
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> index 31febec976..c0b2c615aa 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> @@ -25,6 +25,10 @@ UINTN mEnabledInterruptNum =
> 0;
>
> EXCEPTION_HANDLER_DATA mExceptionHandlerData;
>
> +UINT8
> mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> + CPU_KNOWN_GOOD_STACK_SIZE]
> = {0};
> +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> +
> /**
> Common exception handler.
>
> @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> )
> {
> + EFI_STATUS Status;
> + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> + IA32_DESCRIPTOR Idtr;
> + IA32_DESCRIPTOR Gdtr;
> +
> mExceptionHandlerData.ReservedVectors =
> mReservedVectorsData;
> mExceptionHandlerData.ExternalInterruptHandler =
> mExternalInterruptHandlerTable;
> InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> &mExceptionHandlerData);
> + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> &mExceptionHandlerData);
> + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> + AsmReadIdtr (&Idtr);
> + AsmReadGdtr (&Gdtr);
> +
> + StackSwitchData.StackTop = (UINTN)mNewStack;
> + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> + StackSwitchData.ExceptionNumber =
> CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
> + StackSwitchData.GdtSize = sizeof (mNewGdt);
> + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> Gdtr.Limit + 1);
> + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> Gdtr.Limit + 1 +
> +
> CPU_TSS_DESC_SIZE);
> + Status = InitializeCpuExceptionStackSwitchHandlers (
> + &StackSwitchData
> + );
> + }
> + return Status;
> }
>
> /**
> @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> {
> return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler,
> &mExceptionHandlerData);
> }
> +
> +/**
> + Setup separate stack for given exceptions. This is required by
> + PcdCpuStackGuard feature.
> +
> + Note: For IA32 processor, StackSwitchData is a required parameter.
> +
> + @param[in] StackSwitchData Pointer to data required for setuping up
> + stack switch.
> +
> + @retval EFI_SUCCESS The exceptions have been successfully
> + initialized.
> + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> content.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuExceptionStackSwitchHandlers (
> + IN VOID *StackSwitchData OPTIONAL
> + )
> +{
> + return ArchSetupExcpetionStack (StackSwitchData);
> +}
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> index f2c39eb193..0aaf794795 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> SystemContext.SystemContextIa32->ExceptionData =
> ReservedVectors[ExceptionType].ExceptionData;
> }
>
> +/**
> + Setup separate stack for given exceptions.
> +
> + @param[in] StackSwitchData Pointer to data required for setuping
> up
> + stack switch.
> + @retval EFI_SUCCESS The exceptions have been successfully
> + initialized.
> + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> content.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +ArchSetupExcpetionStack (
> + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> + )
> +{
> + IA32_DESCRIPTOR Gdtr;
> + IA32_DESCRIPTOR Idtr;
> + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> + IA32_TSS_DESCRIPTOR *TssDesc;
> + IA32_TASK_STATE_SEGMENT *Tss;
> + UINTN StackTop;
> + UINTN Index;
> + UINTN Vector;
> + UINTN TssBase;
> + UINTN GdtSize;
> + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> +
> + if (StackSwitchData == NULL ||
> + StackSwitchData->StackTop == 0 ||
> + StackSwitchData->StackSize == 0 ||
> + StackSwitchData->Exceptions == NULL ||
> + StackSwitchData->ExceptionNumber == 0 ||
> + StackSwitchData->GdtTable == NULL ||
> + StackSwitchData->IdtTable == NULL ||
> + StackSwitchData->TssDesc == NULL ||
> + StackSwitchData->Tss == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // The caller is responsible for that the GDT table, no matter the existing
> + // one or newly allocated, has enough space to hold descriptors for exception
> + // task-state segments.
> + //
> + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable))
> {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ((UINTN)StackSwitchData->TssDesc >=
> + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize))
> {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + GdtSize = (UINTN)StackSwitchData->TssDesc -
> + (UINTN)(StackSwitchData->GdtTable) +
> + sizeof (IA32_TSS_DESCRIPTOR) *
> + (StackSwitchData->ExceptionNumber + 1);
> + if (GdtSize > StackSwitchData->GdtSize) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Initialize new GDT table and/or IDT table, if any
> + //
> + AsmReadIdtr (&Idtr);
> + AsmReadGdtr (&Gdtr);
> + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
> + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> + }
> +
> + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> + }
> +
> + //
> + // Fixup current task descriptor. Task-state segment for current task will
> + // be filled by processor during task switching.
> + //
> + TssDesc = StackSwitchData->TssDesc;
> + Tss = StackSwitchData->Tss;
> +
> + TssBase = (UINTN)Tss;
> + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> + TssDesc->Bits.P = 1;
> + TssDesc->Bits.LimitHigh = 0;
> + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> +
> + //
> + // Fixup exception task descriptor and task-state segment
> + //
> + AsmGetTssTemplateMap (&TemplateMap);
> + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> + IdtTable = StackSwitchData->IdtTable;
> + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> + TssDesc += 1;
> + Tss += 1;
> +
> + //
> + // Fixup TSS descriptor
> + //
> + TssBase = (UINTN)Tss;
> +
> + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> + TssDesc->Bits.P = 1;
> + TssDesc->Bits.LimitHigh = 0;
> + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> +
> + //
> + // Fixup TSS
> + //
> + Vector = StackSwitchData->Exceptions[Index];
> + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> + + Vector *
> TemplateMap.ExceptionStubHeaderSize);
> + Tss->EFLAGS = 0x2;
> + Tss->ESP = StackTop;
> + Tss->CR3 = AsmReadCr3 ();
> + Tss->ES = AsmReadEs ();
> + Tss->CS = AsmReadCs ();
> + Tss->SS = AsmReadSs ();
> + Tss->DS = AsmReadDs ();
> + Tss->FS = AsmReadFs ();
> + Tss->GS = AsmReadGs ();
> +
> + StackTop -= StackSwitchData->StackSize;
> +
> + //
> + // Update IDT to use Task Gate for given exception
> + //
> + IdtTable[Vector].Bits.OffsetLow = 0;
> + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc - Gdtr.Base);
> + IdtTable[Vector].Bits.Reserved_0 = 0;
> + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> + IdtTable[Vector].Bits.OffsetHigh = 0;
> + }
> +
> + //
> + // Publish GDT
> + //
> + AsmWriteGdtr (&Gdtr);
> +
> + //
> + // Load current task
> + //
> + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> +
> + //
> + // Publish IDT
> + //
> + AsmWriteIdtr (&Idtr);
> +
> + return EFI_SUCCESS;
> +}
> +
> /**
> Display processor context.
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> index a8d3556a80..d9ded5977f 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> @@ -41,4 +41,12 @@ typedef struct {
> UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> } RESERVED_VECTORS_DATA;
>
> +#define CPU_TSS_DESC_SIZE \
> + (sizeof (IA32_TSS_DESCRIPTOR) * \
> + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> +
> +#define CPU_TSS_SIZE \
> + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> +
> #endif
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> m
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> m
> new file mode 100644
> index 0000000000..62bcedea1a
> --- /dev/null
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> m
> @@ -0,0 +1,398 @@
> +;------------------------------------------------------------------------------ ;
> +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +; This program and the accompanying materials
> +; are licensed and made available under the terms and conditions of the BSD
> License
> +; which accompanies this distribution. The full text of the license may be found
> at
> +; http://opensource.org/licenses/bsd-license.php.
> +;
> +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
> OR IMPLIED.
> +;
> +; Module Name:
> +;
> +; ExceptionTssEntryAsm.Asm
> +;
> +; Abstract:
> +;
> +; IA32 CPU Exception Handler with Separate Stack
> +;
> +; Notes:
> +;
> +;------------------------------------------------------------------------------
> +
> +;
> +; IA32 TSS Memory Layout Description
> +;
> +struc IA32_TSS
> + resw 1
> + resw 1
> + .ESP0: resd 1
> + .SS0: resw 1
> + resw 1
> + .ESP1: resd 1
> + .SS1: resw 1
> + resw 1
> + .ESP2: resd 1
> + .SS2: resw 1
> + resw 1
> + ._CR3: resd 1
> + .EIP: resd 1
> + .EFLAGS: resd 1
> + ._EAX: resd 1
> + ._ECX: resd 1
> + ._EDX: resd 1
> + ._EBX: resd 1
> + ._ESP: resd 1
> + ._EBP: resd 1
> + ._ESI: resd 1
> + ._EDI: resd 1
> + ._ES: resw 1
> + resw 1
> + ._CS: resw 1
> + resw 1
> + ._SS: resw 1
> + resw 1
> + ._DS: resw 1
> + resw 1
> + ._FS: resw 1
> + resw 1
> + ._GS: resw 1
> + resw 1
> + .LDT: resw 1
> + resw 1
> + resw 1
> + resw 1
> +endstruc
> +
> +;
> +; CommonExceptionHandler()
> +;
> +extern ASM_PFX(CommonExceptionHandler)
> +
> +SECTION .data
> +
> +SECTION .text
> +
> +ALIGN 8
> +
> +;
> +; Exception handler stub table
> +;
> +AsmExceptionEntryBegin:
> +%assign Vector 0
> +%rep 32
> +
> +DoIret%[Vector]:
> + iretd
> +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> + db 0x6a ; push #VectorNum
> + db %[Vector]
> + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> + call eax
> + mov esp, eax ; Restore stack top
> + jmp DoIret%[Vector]
> +
> +%assign Vector Vector+1
> +%endrep
> +AsmExceptionEntryEnd:
> +
> +;
> +; Common part of exception handler
> +;
> +global ASM_PFX(CommonTaskSwtichEntryPoint)
> +ASM_PFX(CommonTaskSwtichEntryPoint):
> + ;
> + ; Stack:
> + ; +---------------------+ <-- EBP - 8
> + ; + TSS Base +
> + ; +---------------------+ <-- EBP - 4
> + ; + CPUID.EDX +
> + ; +---------------------+ <-- EBP
> + ; + EIP +
> + ; +---------------------+ <-- EBP + 4
> + ; + Vector Number +
> + ; +---------------------+ <-- EBP + 8
> + ; + Error Code +
> + ; +---------------------+
> + ;
> +
> + mov ebp, esp ; Stack frame
> +
> +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> + mov eax, 1
> + cpuid
> + push edx
> +
> +; Get TSS base of interrupted task through PreviousTaskLink field in
> +; current TSS base
> + sub esp, 8
> + sgdt [esp + 2]
> + mov eax, [esp + 4] ; GDT base
> + add esp, 8
> +
> + xor ebx, ebx
> + str bx ; Current TR
> +
> + mov ecx, [eax + ebx + 2]
> + shl ecx, 8
> + mov cl, [eax + ebx + 7]
> + ror ecx, 8 ; ecx = Current TSS base
> + push ecx ; keep it in stack for later use
> +
> + movzx ebx, word [ecx] ; Previous Task Link
> + mov ecx, [eax + ebx + 2]
> + shl ecx, 8
> + mov cl, [eax + ebx + 7]
> + ror ecx, 8 ; ecx = Previous TSS base
> +
> +;
> +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> EFI_SYSTEM_CONTEXT_IA32
> +; is 16-byte aligned
> +;
> + and esp, 0xfffffff0
> + sub esp, 12
> +
> +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> + push dword [ecx + IA32_TSS._EAX]
> + push dword [ecx + IA32_TSS._ECX]
> + push dword [ecx + IA32_TSS._EDX]
> + push dword [ecx + IA32_TSS._EBX]
> + push dword [ecx + IA32_TSS._ESP]
> + push dword [ecx + IA32_TSS._EBP]
> + push dword [ecx + IA32_TSS._ESI]
> + push dword [ecx + IA32_TSS._EDI]
> +
> +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> + movzx eax, word [ecx + IA32_TSS._SS]
> + push eax
> + movzx eax, word [ecx + IA32_TSS._CS]
> + push eax
> + movzx eax, word [ecx + IA32_TSS._DS]
> + push eax
> + movzx eax, word [ecx + IA32_TSS._ES]
> + push eax
> + movzx eax, word [ecx + IA32_TSS._FS]
> + push eax
> + movzx eax, word [ecx + IA32_TSS._GS]
> + push eax
> +
> +;; UINT32 Eip;
> + push dword [ecx + IA32_TSS.EIP]
> +
> +;; UINT32 Gdtr[2], Idtr[2];
> + sub esp, 8
> + sidt [esp]
> + mov eax, [esp + 2]
> + xchg eax, [esp]
> + and eax, 0xFFFF
> + mov [esp+4], eax
> +
> + sub esp, 8
> + sgdt [esp]
> + mov eax, [esp + 2]
> + xchg eax, [esp]
> + and eax, 0xFFFF
> + mov [esp+4], eax
> +
> +;; UINT32 Ldtr, Tr;
> + mov eax, ebx ; ebx still keeps selector of interrupted task
> + push eax
> + movzx eax, word [ecx + IA32_TSS.LDT]
> + push eax
> +
> +;; UINT32 EFlags;
> + push dword [ecx + IA32_TSS.EFLAGS]
> +
> +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> + mov eax, cr4
> + push eax ; push cr4 firstly
> +
> + mov edx, [ebp - 4] ; cpuid.edx
> + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> + jz .1
> + or eax, BIT9 ; Set CR4.OSFXSR
> +.1:
> + test edx, BIT2 ; Test for Debugging Extensions support
> + jz .2
> + or eax, BIT3 ; Set CR4.DE
> +.2:
> + mov cr4, eax
> +
> + mov eax, cr3
> + push eax
> + mov eax, cr2
> + push eax
> + xor eax, eax
> + push eax
> + mov eax, cr0
> + push eax
> +
> +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> + mov eax, dr7
> + push eax
> + mov eax, dr6
> + push eax
> + mov eax, dr3
> + push eax
> + mov eax, dr2
> + push eax
> + mov eax, dr1
> + push eax
> + mov eax, dr0
> + push eax
> +
> +;; FX_SAVE_STATE_IA32 FxSaveState;
> +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> +;; when executing fxsave/fxrstor instruction
> + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> + ; edx still contains result from CPUID above
> + jz .3
> + clts
> + sub esp, 512
> + mov edi, esp
> + db 0xf, 0xae, 0x7 ;fxsave [edi]
> +.3:
> +
> +;; UINT32 ExceptionData;
> + push dword [ebp + 8]
> +
> +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
> + cld
> +
> +;; call into exception handler
> + mov esi, ecx ; Keep TSS base to avoid overwrite
> + mov eax, ASM_PFX(CommonExceptionHandler)
> +
> +;; Prepare parameter and call
> + mov edx, esp
> + push edx ; EFI_SYSTEM_CONTEXT
> + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> +
> + ;
> + ; Call External Exception Handler
> + ;
> + call eax
> + add esp, 8 ; Restore stack before calling
> + mov ecx, esi ; Restore TSS base
> +
> +;; UINT32 ExceptionData;
> + add esp, 4
> +
> +;; FX_SAVE_STATE_IA32 FxSaveState;
> + mov edx, [ebp - 4] ; cpuid.edx
> + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> + jz .4
> + mov esi, esp
> + db 0xf, 0xae, 0xe ; fxrstor [esi]
> +.4:
> + add esp, 512
> +
> +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> +;; Skip restoration of DRx registers to support debuggers
> +;; that set breakpoints in interrupt/exception context
> + add esp, 4 * 6
> +
> +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> + pop eax
> + mov cr0, eax
> + add esp, 4 ; not for Cr1
> + pop eax
> + mov cr2, eax
> + pop eax
> + mov dword [ecx + IA32_TSS._CR3], eax
> + pop eax
> + mov cr4, eax
> +
> +;; UINT32 EFlags;
> + pop dword [ecx + IA32_TSS.EFLAGS]
> + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> + btr ebx, 9 ; Do 'cli'
> + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> +
> +;; UINT32 Ldtr, Tr;
> +;; UINT32 Gdtr[2], Idtr[2];
> +;; Best not let anyone mess with these particular registers...
> + add esp, 24
> +
> +;; UINT32 Eip;
> + pop dword [ecx + IA32_TSS.EIP]
> +
> +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> +;; NOTE - modified segment registers could hang the debugger... We
> +;; could attempt to insulate ourselves against this possibility,
> +;; but that poses risks as well.
> +;;
> + pop eax
> +o16 mov [ecx + IA32_TSS._GS], ax
> + pop eax
> +o16 mov [ecx + IA32_TSS._FS], ax
> + pop eax
> +o16 mov [ecx + IA32_TSS._ES], ax
> + pop eax
> +o16 mov [ecx + IA32_TSS._DS], ax
> + pop eax
> +o16 mov [ecx + IA32_TSS._CS], ax
> + pop eax
> +o16 mov [ecx + IA32_TSS._SS], ax
> +
> +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> + pop dword [ecx + IA32_TSS._EDI]
> + pop dword [ecx + IA32_TSS._ESI]
> + add esp, 4 ; not for ebp
> + add esp, 4 ; not for esp
> + pop dword [ecx + IA32_TSS._EBX]
> + pop dword [ecx + IA32_TSS._EDX]
> + pop dword [ecx + IA32_TSS._ECX]
> + pop dword [ecx + IA32_TSS._EAX]
> +
> +; Set single step DB# to allow debugger to able to go back to the EIP
> +; where the exception is triggered.
> +
> +;; Create return context for iretd in stub function
> + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> + mov ebx, dword [ecx + IA32_TSS.EIP]
> + mov [eax - 0xc], ebx ; create EIP in old stack
> + movzx ebx, word [ecx + IA32_TSS._CS]
> + mov [eax - 0x8], ebx ; create CS in old stack
> + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> + bts ebx, 8
> + mov [eax - 0x4], ebx ; create eflags in old stack
> + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS
> + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> + sub eax, 0xc ; minus 12 byte
> + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
> +
> +;; Replace the EIP of interrupted task with stub function
> + mov eax, ASM_PFX(SingleStepStubFunction)
> + mov dword [ecx + IA32_TSS.EIP], eax
> +
> + mov ecx, [ebp - 8] ; Get current TSS base
> + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack top
> + mov esp, ebp
> +
> + ret
> +
> +global ASM_PFX(SingleStepStubFunction)
> +ASM_PFX(SingleStepStubFunction):
> +;
> +; we need clean TS bit in CR0 to execute
> +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> +;
> + clts
> + iretd
> +
> +global ASM_PFX(AsmGetTssTemplateMap)
> +ASM_PFX(AsmGetTssTemplateMap):
> + push ebp ; C prolog
> + mov ebp, esp
> + pushad
> +
> + mov ebx, dword [ebp + 0x8]
> + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> + mov dword [ebx + 0x4], (AsmExceptionEntryEnd - AsmExceptionEntryBegin)
> / 32
> + mov dword [ebx + 0x8], 0
> +
> + popad
> + pop ebp
> + ret
> +
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> index 75443288a9..4c0d435136 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> @@ -30,6 +30,7 @@
> [Sources.Ia32]
> Ia32/ExceptionHandlerAsm.asm
> Ia32/ExceptionHandlerAsm.nasm
> + Ia32/ExceptionTssEntryAsm.nasm
> Ia32/ExceptionHandlerAsm.S
> Ia32/ArchExceptionHandler.c
> Ia32/ArchInterruptDefs.h
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> nf
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> nf
> index d70a99c100..e5c03c16c9 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> nf
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> nf
> @@ -30,6 +30,7 @@
> [Sources.Ia32]
> Ia32/ExceptionHandlerAsm.asm
> Ia32/ExceptionHandlerAsm.nasm
> + Ia32/ExceptionTssEntryAsm.nasm
> Ia32/ExceptionHandlerAsm.S
> Ia32/ArchExceptionHandler.c
> Ia32/ArchInterruptDefs.h
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> index 634ffcb21d..56b875b7c8 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> @@ -30,6 +30,7 @@
> [Sources.Ia32]
> Ia32/ExceptionHandlerAsm.asm
> Ia32/ExceptionHandlerAsm.nasm
> + Ia32/ExceptionTssEntryAsm.nasm
> Ia32/ExceptionHandlerAsm.S
> Ia32/ArchExceptionHandler.c
> Ia32/ArchInterruptDefs.h
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> index 65f0cff680..214aafcc13 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> SystemContext.SystemContextX64->ExceptionData =
> ReservedVectors[ExceptionType].ExceptionData;
> }
>
> +/**
> + Setup separate stack for given exceptions.
> +
> + @param[in] StackSwitchData Pointer to data required for setuping up
> + stack switch.
> +
> + @retval EFI_SUCCESS The exceptions have been successfully
> + initialized.
> + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> content.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +ArchSetupExcpetionStack (
> + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> + )
> +{
> + IA32_DESCRIPTOR Gdtr;
> + IA32_DESCRIPTOR Idtr;
> + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> + IA32_TSS_DESCRIPTOR *TssDesc;
> + IA32_TASK_STATE_SEGMENT *Tss;
> + UINTN StackTop;
> + UINTN Index;
> + UINTN TssBase;
> + UINTN GdtSize;
> +
> + if (StackSwitchData == NULL ||
> + StackSwitchData->StackTop == 0 ||
> + StackSwitchData->StackSize == 0 ||
> + StackSwitchData->Exceptions == NULL ||
> + StackSwitchData->ExceptionNumber == 0 ||
> + StackSwitchData->GdtTable == NULL ||
> + StackSwitchData->IdtTable == NULL ||
> + StackSwitchData->TssDesc == NULL ||
> + StackSwitchData->Tss == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // The caller is responsible for that the GDT table, no matter the existing
> + // one or newly allocated, has enough space to hold descriptors for exception
> + // task-state segments.
> + //
> + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable))
> {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ((UINTN)StackSwitchData->TssDesc >=
> + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize))
> {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + GdtSize = (UINTN)StackSwitchData->TssDesc -
> + (UINTN)(StackSwitchData->GdtTable) +
> + sizeof (IA32_TSS_DESCRIPTOR);
> + if (GdtSize > StackSwitchData->GdtSize) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Initialize new GDT table and/or IDT table, if any
> + //
> + AsmReadIdtr (&Idtr);
> + AsmReadGdtr (&Gdtr);
> + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
> + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> + Gdtr.Limit = (UINT16)GdtSize - 1;
> + }
> +
> + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> + }
> +
> + //
> + // Fixup current task descriptor. Task-state segment for current task will
> + // be filled by processor during task switching.
> + //
> + TssDesc = StackSwitchData->TssDesc;
> + Tss = StackSwitchData->Tss;
> +
> + TssBase = (UINTN)Tss;
> + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> + TssDesc->Bits.P = 1;
> + TssDesc->Bits.LimitHigh = 0;
> + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> +
> + //
> + // Fixup exception task descriptor and task-state segment
> + //
> + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> + IdtTable = StackSwitchData->IdtTable;
> + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> + //
> + // Fixup IST
> + //
> + Tss->IST[Index] = StackTop;
> + StackTop -= StackSwitchData->StackSize;
> +
> + //
> + // Set the IST field to enable corresponding IST
> + //
> + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> (UINT8)(Index + 1);
> + }
> +
> + //
> + // Publish GDT
> + //
> + AsmWriteGdtr (&Gdtr);
> +
> + //
> + // Load current task
> + //
> + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> +
> + //
> + // Publish IDT
> + //
> + AsmWriteIdtr (&Idtr);
> +
> + return EFI_SUCCESS;
> +}
> +
> /**
> Display CPU information.
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> index 906480134a..c88be46286 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> @@ -43,4 +43,7 @@ typedef struct {
> UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> } RESERVED_VECTORS_DATA;
>
> +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> +
> #endif
> --
> 2.14.1.windows.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 5:50 ` Yao, Jiewen
@ 2017-11-23 5:59 ` Yao, Jiewen
2017-11-23 6:09 ` Wang, Jian J
2017-11-23 6:05 ` Wang, Jian J
1 sibling, 1 reply; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 5:59 UTC (permalink / raw)
To: Yao, Jiewen, Wang, Jian J, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
One more question:
I notice not all platforms are using the CpuDxe in UefiCpuPkg.
If so, is there any impact to the platform whose CPU driver does not have such InitializeCpuExceptionStackSwitchHandlers() call?
Have you tested that condition?
Thank you
Yao Jiewen
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Yao,
> Jiewen
> Sent: Thursday, November 23, 2017 1:50 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> stack switch support
>
> Some thought:
>
> 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented in
> DxeException.c.
> What about Pei/Smm instance?
>
> I think it is OK to not implement it at this moment. But we need make sure no
> architecture issue if we want to enable it some time later.
>
> 2) #define IA32_GDT_TYPE_TSS 0x9
> This is generic, can we move to BaseLib.h?
>
>
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Wednesday, November 22, 2017 4:46 PM
> > To: edk2-devel@lists.01.org
> > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>; Yao,
> > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>
> > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch
> > support
> >
> > > v2:
> > > a. Move common TSS structure and API definitions to BaseLib.h
> > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to setup
> > stack
> > > switch. This can avoid allocating memory for it in this library.
> > > c. Add globals to reserve memory for stack switch initialized in early
> > > phase of DXE core.
> > > d. Remove the filter code used to exclude boot modes which doesn't
> > support
> > > memory allocation because those memory can passed in by
> parameter
> > now.
> > > e. Remove the nasm macro to define exception handler one by one and
> > add a
> > > function to return the start address of each handler.
> >
> > If Stack Guard is enabled and there's really a stack overflow happened during
> > boot, a Page Fault exception will be triggered. Because the stack is out of
> > usage, the exception handler, which shares the stack with normal UEFI driver,
> > cannot be executed and cannot dump the processor information.
> >
> > Without those information, it's very difficult for the BIOS developers locate
> > the root cause of stack overflow. And without a workable stack, the developer
> > cannot event use single step to debug the UEFI driver with JTAG debugger.
> >
> > In order to make sure the exception handler to execute normally after stack
> > overflow. We need separate stacks for exception handlers in case of unusable
> > stack.
> >
> > IA processor allows to switch to a new stack during handling interrupt and
> > exception. But X64 and IA32 provides different ways to make it. X64 provides
> > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > new stack for its handler. IA32 doesn't have IST mechanism and can only use
> > task gate to do it since task switch allows to load a new stack through its
> > task-state segment (TSS).
> >
> > Cc: Star Zeng <star.zeng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > ---
> > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > .../Ia32/ArchInterruptDefs.h | 8 +
> > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > +++++++++++++++++++++
> > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > .../X64/ArchExceptionHandler.c | 133 +++++++
> > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > 11 files changed, 820 insertions(+), 1 deletion(-)
> > create mode 100644
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> >
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > index 740a58828b..30334105d2 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > @@ -48,6 +48,32 @@
> > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c,
> 0x83 }
> > \
> > }
> >
> > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > +
> > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > +
> > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > +
> > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> CPU_TSS_SIZE)
> > +
> > +#define IA32_GDT_TYPE_TSS 0x9
> > +#define IA32_GDT_ALIGNMENT 8
> > +
> > +typedef struct {
> > + UINTN StackTop;
> > + UINTN StackSize;
> > + UINT8 *Exceptions;
> > + UINTN ExceptionNumber;
> > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > + UINTN GdtSize;
> > + IA32_TSS_DESCRIPTOR *TssDesc;
> > + IA32_TASK_STATE_SEGMENT *Tss;
> > +} EXCEPTION_STACK_SWITCH_DATA;
> > +
> > //
> > // Record exception handler information
> > //
> > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > );
> >
> > +/**
> > + Setup separate stack for specific exceptions.
> > +
> > + @param[in] IdtTable IDT table base.
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArchSetupExcpetionStack (
> > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > + );
> > +
> > +/**
> > + Return address map of exception handler template so that C code can
> > generate
> > + exception tables. The template is only for exceptions using task gate
> instead
> > + of interrupt gate.
> > +
> > + @param AddressMap Pointer to a buffer where the address map is
> > returned.
> > +**/
> > +VOID
> > +EFIAPI
> > +AsmGetTssTemplateMap (
> > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > + );
> > +
> > #endif
> >
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > index f4a8d01c80..58e55a8a2e 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > @@ -47,6 +48,11 @@
> > PeiDxeSmmCpuException.c
> > DxeException.c
> >
> > +[Pcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > +
> > [Packages]
> > MdePkg/MdePkg.dec
> > MdeModulePkg/MdeModulePkg.dec
> > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > index 31febec976..c0b2c615aa 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > @@ -25,6 +25,10 @@ UINTN mEnabledInterruptNum
> =
> > 0;
> >
> > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> >
> > +UINT8
> > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > +
> CPU_KNOWN_GOOD_STACK_SIZE]
> > = {0};
> > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > +
> > /**
> > Common exception handler.
> >
> > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > )
> > {
> > + EFI_STATUS Status;
> > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > + IA32_DESCRIPTOR Idtr;
> > + IA32_DESCRIPTOR Gdtr;
> > +
> > mExceptionHandlerData.ReservedVectors =
> > mReservedVectorsData;
> > mExceptionHandlerData.ExternalInterruptHandler =
> > mExternalInterruptHandlerTable;
> > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > &mExceptionHandlerData);
> > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > &mExceptionHandlerData);
> > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > + AsmReadIdtr (&Idtr);
> > + AsmReadGdtr (&Gdtr);
> > +
> > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > + StackSwitchData.ExceptionNumber =
> > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
> > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > Gdtr.Limit + 1);
> > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > Gdtr.Limit + 1 +
> > +
> > CPU_TSS_DESC_SIZE);
> > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > + &StackSwitchData
> > + );
> > + }
> > + return Status;
> > }
> >
> > /**
> > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > {
> > return RegisterCpuInterruptHandlerWorker (InterruptType,
> InterruptHandler,
> > &mExceptionHandlerData);
> > }
> > +
> > +/**
> > + Setup separate stack for given exceptions. This is required by
> > + PcdCpuStackGuard feature.
> > +
> > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping up
> > + stack switch.
> > +
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +InitializeCpuExceptionStackSwitchHandlers (
> > + IN VOID *StackSwitchData OPTIONAL
> > + )
> > +{
> > + return ArchSetupExcpetionStack (StackSwitchData);
> > +}
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > index f2c39eb193..0aaf794795 100644
> > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > SystemContext.SystemContextIa32->ExceptionData =
> > ReservedVectors[ExceptionType].ExceptionData;
> > }
> >
> > +/**
> > + Setup separate stack for given exceptions.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > + stack switch.
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArchSetupExcpetionStack (
> > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > + )
> > +{
> > + IA32_DESCRIPTOR Gdtr;
> > + IA32_DESCRIPTOR Idtr;
> > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > + IA32_TSS_DESCRIPTOR *TssDesc;
> > + IA32_TASK_STATE_SEGMENT *Tss;
> > + UINTN StackTop;
> > + UINTN Index;
> > + UINTN Vector;
> > + UINTN TssBase;
> > + UINTN GdtSize;
> > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > +
> > + if (StackSwitchData == NULL ||
> > + StackSwitchData->StackTop == 0 ||
> > + StackSwitchData->StackSize == 0 ||
> > + StackSwitchData->Exceptions == NULL ||
> > + StackSwitchData->ExceptionNumber == 0 ||
> > + StackSwitchData->GdtTable == NULL ||
> > + StackSwitchData->IdtTable == NULL ||
> > + StackSwitchData->TssDesc == NULL ||
> > + StackSwitchData->Tss == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // The caller is responsible for that the GDT table, no matter the existing
> > + // one or newly allocated, has enough space to hold descriptors for
> exception
> > + // task-state segments.
> > + //
> > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0)
> {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc <
> (UINTN)(StackSwitchData->GdtTable))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc >=
> > + ((UINTN)(StackSwitchData->GdtTable) +
> StackSwitchData->GdtSize))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > + (UINTN)(StackSwitchData->GdtTable) +
> > + sizeof (IA32_TSS_DESCRIPTOR) *
> > + (StackSwitchData->ExceptionNumber + 1);
> > + if (GdtSize > StackSwitchData->GdtSize) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // Initialize new GDT table and/or IDT table, if any
> > + //
> > + AsmReadIdtr (&Idtr);
> > + AsmReadGdtr (&Gdtr);
> > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> 1);
> > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > + }
> > +
> > + //
> > + // Fixup current task descriptor. Task-state segment for current task will
> > + // be filled by processor during task switching.
> > + //
> > + TssDesc = StackSwitchData->TssDesc;
> > + Tss = StackSwitchData->Tss;
> > +
> > + TssBase = (UINTN)Tss;
> > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > + TssDesc->Bits.P = 1;
> > + TssDesc->Bits.LimitHigh = 0;
> > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > +
> > + //
> > + // Fixup exception task descriptor and task-state segment
> > + //
> > + AsmGetTssTemplateMap (&TemplateMap);
> > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> > + IdtTable = StackSwitchData->IdtTable;
> > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > + TssDesc += 1;
> > + Tss += 1;
> > +
> > + //
> > + // Fixup TSS descriptor
> > + //
> > + TssBase = (UINTN)Tss;
> > +
> > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > + TssDesc->Bits.P = 1;
> > + TssDesc->Bits.LimitHigh = 0;
> > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > +
> > + //
> > + // Fixup TSS
> > + //
> > + Vector = StackSwitchData->Exceptions[Index];
> > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > + + Vector *
> > TemplateMap.ExceptionStubHeaderSize);
> > + Tss->EFLAGS = 0x2;
> > + Tss->ESP = StackTop;
> > + Tss->CR3 = AsmReadCr3 ();
> > + Tss->ES = AsmReadEs ();
> > + Tss->CS = AsmReadCs ();
> > + Tss->SS = AsmReadSs ();
> > + Tss->DS = AsmReadDs ();
> > + Tss->FS = AsmReadFs ();
> > + Tss->GS = AsmReadGs ();
> > +
> > + StackTop -= StackSwitchData->StackSize;
> > +
> > + //
> > + // Update IDT to use Task Gate for given exception
> > + //
> > + IdtTable[Vector].Bits.OffsetLow = 0;
> > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc - Gdtr.Base);
> > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > + }
> > +
> > + //
> > + // Publish GDT
> > + //
> > + AsmWriteGdtr (&Gdtr);
> > +
> > + //
> > + // Load current task
> > + //
> > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > +
> > + //
> > + // Publish IDT
> > + //
> > + AsmWriteIdtr (&Idtr);
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > /**
> > Display processor context.
> >
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > index a8d3556a80..d9ded5977f 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > @@ -41,4 +41,12 @@ typedef struct {
> > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > } RESERVED_VECTORS_DATA;
> >
> > +#define CPU_TSS_DESC_SIZE \
> > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > +
> > +#define CPU_TSS_SIZE \
> > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > +
> > #endif
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > m
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > m
> > new file mode 100644
> > index 0000000000..62bcedea1a
> > --- /dev/null
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > m
> > @@ -0,0 +1,398 @@
> > +;------------------------------------------------------------------------------ ;
> > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > +; This program and the accompanying materials
> > +; are licensed and made available under the terms and conditions of the BSD
> > License
> > +; which accompanies this distribution. The full text of the license may be
> found
> > at
> > +; http://opensource.org/licenses/bsd-license.php.
> > +;
> > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
> > OR IMPLIED.
> > +;
> > +; Module Name:
> > +;
> > +; ExceptionTssEntryAsm.Asm
> > +;
> > +; Abstract:
> > +;
> > +; IA32 CPU Exception Handler with Separate Stack
> > +;
> > +; Notes:
> > +;
> > +;------------------------------------------------------------------------------
> > +
> > +;
> > +; IA32 TSS Memory Layout Description
> > +;
> > +struc IA32_TSS
> > + resw 1
> > + resw 1
> > + .ESP0: resd 1
> > + .SS0: resw 1
> > + resw 1
> > + .ESP1: resd 1
> > + .SS1: resw 1
> > + resw 1
> > + .ESP2: resd 1
> > + .SS2: resw 1
> > + resw 1
> > + ._CR3: resd 1
> > + .EIP: resd 1
> > + .EFLAGS: resd 1
> > + ._EAX: resd 1
> > + ._ECX: resd 1
> > + ._EDX: resd 1
> > + ._EBX: resd 1
> > + ._ESP: resd 1
> > + ._EBP: resd 1
> > + ._ESI: resd 1
> > + ._EDI: resd 1
> > + ._ES: resw 1
> > + resw 1
> > + ._CS: resw 1
> > + resw 1
> > + ._SS: resw 1
> > + resw 1
> > + ._DS: resw 1
> > + resw 1
> > + ._FS: resw 1
> > + resw 1
> > + ._GS: resw 1
> > + resw 1
> > + .LDT: resw 1
> > + resw 1
> > + resw 1
> > + resw 1
> > +endstruc
> > +
> > +;
> > +; CommonExceptionHandler()
> > +;
> > +extern ASM_PFX(CommonExceptionHandler)
> > +
> > +SECTION .data
> > +
> > +SECTION .text
> > +
> > +ALIGN 8
> > +
> > +;
> > +; Exception handler stub table
> > +;
> > +AsmExceptionEntryBegin:
> > +%assign Vector 0
> > +%rep 32
> > +
> > +DoIret%[Vector]:
> > + iretd
> > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > + db 0x6a ; push #VectorNum
> > + db %[Vector]
> > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > + call eax
> > + mov esp, eax ; Restore stack top
> > + jmp DoIret%[Vector]
> > +
> > +%assign Vector Vector+1
> > +%endrep
> > +AsmExceptionEntryEnd:
> > +
> > +;
> > +; Common part of exception handler
> > +;
> > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > + ;
> > + ; Stack:
> > + ; +---------------------+ <-- EBP - 8
> > + ; + TSS Base +
> > + ; +---------------------+ <-- EBP - 4
> > + ; + CPUID.EDX +
> > + ; +---------------------+ <-- EBP
> > + ; + EIP +
> > + ; +---------------------+ <-- EBP + 4
> > + ; + Vector Number +
> > + ; +---------------------+ <-- EBP + 8
> > + ; + Error Code +
> > + ; +---------------------+
> > + ;
> > +
> > + mov ebp, esp ; Stack frame
> > +
> > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > + mov eax, 1
> > + cpuid
> > + push edx
> > +
> > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > +; current TSS base
> > + sub esp, 8
> > + sgdt [esp + 2]
> > + mov eax, [esp + 4] ; GDT base
> > + add esp, 8
> > +
> > + xor ebx, ebx
> > + str bx ; Current TR
> > +
> > + mov ecx, [eax + ebx + 2]
> > + shl ecx, 8
> > + mov cl, [eax + ebx + 7]
> > + ror ecx, 8 ; ecx = Current TSS base
> > + push ecx ; keep it in stack for later use
> > +
> > + movzx ebx, word [ecx] ; Previous Task Link
> > + mov ecx, [eax + ebx + 2]
> > + shl ecx, 8
> > + mov cl, [eax + ebx + 7]
> > + ror ecx, 8 ; ecx = Previous TSS base
> > +
> > +;
> > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > EFI_SYSTEM_CONTEXT_IA32
> > +; is 16-byte aligned
> > +;
> > + and esp, 0xfffffff0
> > + sub esp, 12
> > +
> > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > + push dword [ecx + IA32_TSS._EAX]
> > + push dword [ecx + IA32_TSS._ECX]
> > + push dword [ecx + IA32_TSS._EDX]
> > + push dword [ecx + IA32_TSS._EBX]
> > + push dword [ecx + IA32_TSS._ESP]
> > + push dword [ecx + IA32_TSS._EBP]
> > + push dword [ecx + IA32_TSS._ESI]
> > + push dword [ecx + IA32_TSS._EDI]
> > +
> > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > + movzx eax, word [ecx + IA32_TSS._SS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._CS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._DS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._ES]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._FS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._GS]
> > + push eax
> > +
> > +;; UINT32 Eip;
> > + push dword [ecx + IA32_TSS.EIP]
> > +
> > +;; UINT32 Gdtr[2], Idtr[2];
> > + sub esp, 8
> > + sidt [esp]
> > + mov eax, [esp + 2]
> > + xchg eax, [esp]
> > + and eax, 0xFFFF
> > + mov [esp+4], eax
> > +
> > + sub esp, 8
> > + sgdt [esp]
> > + mov eax, [esp + 2]
> > + xchg eax, [esp]
> > + and eax, 0xFFFF
> > + mov [esp+4], eax
> > +
> > +;; UINT32 Ldtr, Tr;
> > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS.LDT]
> > + push eax
> > +
> > +;; UINT32 EFlags;
> > + push dword [ecx + IA32_TSS.EFLAGS]
> > +
> > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > + mov eax, cr4
> > + push eax ; push cr4 firstly
> > +
> > + mov edx, [ebp - 4] ; cpuid.edx
> > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > + jz .1
> > + or eax, BIT9 ; Set CR4.OSFXSR
> > +.1:
> > + test edx, BIT2 ; Test for Debugging Extensions support
> > + jz .2
> > + or eax, BIT3 ; Set CR4.DE
> > +.2:
> > + mov cr4, eax
> > +
> > + mov eax, cr3
> > + push eax
> > + mov eax, cr2
> > + push eax
> > + xor eax, eax
> > + push eax
> > + mov eax, cr0
> > + push eax
> > +
> > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > + mov eax, dr7
> > + push eax
> > + mov eax, dr6
> > + push eax
> > + mov eax, dr3
> > + push eax
> > + mov eax, dr2
> > + push eax
> > + mov eax, dr1
> > + push eax
> > + mov eax, dr0
> > + push eax
> > +
> > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > +;; when executing fxsave/fxrstor instruction
> > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > + ; edx still contains result from CPUID above
> > + jz .3
> > + clts
> > + sub esp, 512
> > + mov edi, esp
> > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > +.3:
> > +
> > +;; UINT32 ExceptionData;
> > + push dword [ebp + 8]
> > +
> > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
> > + cld
> > +
> > +;; call into exception handler
> > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > + mov eax, ASM_PFX(CommonExceptionHandler)
> > +
> > +;; Prepare parameter and call
> > + mov edx, esp
> > + push edx ; EFI_SYSTEM_CONTEXT
> > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > +
> > + ;
> > + ; Call External Exception Handler
> > + ;
> > + call eax
> > + add esp, 8 ; Restore stack before calling
> > + mov ecx, esi ; Restore TSS base
> > +
> > +;; UINT32 ExceptionData;
> > + add esp, 4
> > +
> > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > + mov edx, [ebp - 4] ; cpuid.edx
> > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > + jz .4
> > + mov esi, esp
> > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > +.4:
> > + add esp, 512
> > +
> > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > +;; Skip restoration of DRx registers to support debuggers
> > +;; that set breakpoints in interrupt/exception context
> > + add esp, 4 * 6
> > +
> > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > + pop eax
> > + mov cr0, eax
> > + add esp, 4 ; not for Cr1
> > + pop eax
> > + mov cr2, eax
> > + pop eax
> > + mov dword [ecx + IA32_TSS._CR3], eax
> > + pop eax
> > + mov cr4, eax
> > +
> > +;; UINT32 EFlags;
> > + pop dword [ecx + IA32_TSS.EFLAGS]
> > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > + btr ebx, 9 ; Do 'cli'
> > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > +
> > +;; UINT32 Ldtr, Tr;
> > +;; UINT32 Gdtr[2], Idtr[2];
> > +;; Best not let anyone mess with these particular registers...
> > + add esp, 24
> > +
> > +;; UINT32 Eip;
> > + pop dword [ecx + IA32_TSS.EIP]
> > +
> > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > +;; NOTE - modified segment registers could hang the debugger... We
> > +;; could attempt to insulate ourselves against this possibility,
> > +;; but that poses risks as well.
> > +;;
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._GS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._FS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._ES], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._DS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._CS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._SS], ax
> > +
> > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > + pop dword [ecx + IA32_TSS._EDI]
> > + pop dword [ecx + IA32_TSS._ESI]
> > + add esp, 4 ; not for ebp
> > + add esp, 4 ; not for esp
> > + pop dword [ecx + IA32_TSS._EBX]
> > + pop dword [ecx + IA32_TSS._EDX]
> > + pop dword [ecx + IA32_TSS._ECX]
> > + pop dword [ecx + IA32_TSS._EAX]
> > +
> > +; Set single step DB# to allow debugger to able to go back to the EIP
> > +; where the exception is triggered.
> > +
> > +;; Create return context for iretd in stub function
> > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > + mov [eax - 0xc], ebx ; create EIP in old stack
> > + movzx ebx, word [ecx + IA32_TSS._CS]
> > + mov [eax - 0x8], ebx ; create CS in old stack
> > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > + bts ebx, 8
> > + mov [eax - 0x4], ebx ; create eflags in old
> stack
> > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old
> TSS
> > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> > + sub eax, 0xc ; minus 12 byte
> > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
> > +
> > +;; Replace the EIP of interrupted task with stub function
> > + mov eax, ASM_PFX(SingleStepStubFunction)
> > + mov dword [ecx + IA32_TSS.EIP], eax
> > +
> > + mov ecx, [ebp - 8] ; Get current TSS base
> > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack
> top
> > + mov esp, ebp
> > +
> > + ret
> > +
> > +global ASM_PFX(SingleStepStubFunction)
> > +ASM_PFX(SingleStepStubFunction):
> > +;
> > +; we need clean TS bit in CR0 to execute
> > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > +;
> > + clts
> > + iretd
> > +
> > +global ASM_PFX(AsmGetTssTemplateMap)
> > +ASM_PFX(AsmGetTssTemplateMap):
> > + push ebp ; C prolog
> > + mov ebp, esp
> > + pushad
> > +
> > + mov ebx, dword [ebp + 0x8]
> > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> AsmExceptionEntryBegin)
> > / 32
> > + mov dword [ebx + 0x8], 0
> > +
> > + popad
> > + pop ebp
> > + ret
> > +
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > index 75443288a9..4c0d435136 100644
> > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> > index d70a99c100..e5c03c16c9 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > index 634ffcb21d..56b875b7c8 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > index 65f0cff680..214aafcc13 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > SystemContext.SystemContextX64->ExceptionData =
> > ReservedVectors[ExceptionType].ExceptionData;
> > }
> >
> > +/**
> > + Setup separate stack for given exceptions.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping up
> > + stack switch.
> > +
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArchSetupExcpetionStack (
> > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > + )
> > +{
> > + IA32_DESCRIPTOR Gdtr;
> > + IA32_DESCRIPTOR Idtr;
> > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > + IA32_TSS_DESCRIPTOR *TssDesc;
> > + IA32_TASK_STATE_SEGMENT *Tss;
> > + UINTN StackTop;
> > + UINTN Index;
> > + UINTN TssBase;
> > + UINTN GdtSize;
> > +
> > + if (StackSwitchData == NULL ||
> > + StackSwitchData->StackTop == 0 ||
> > + StackSwitchData->StackSize == 0 ||
> > + StackSwitchData->Exceptions == NULL ||
> > + StackSwitchData->ExceptionNumber == 0 ||
> > + StackSwitchData->GdtTable == NULL ||
> > + StackSwitchData->IdtTable == NULL ||
> > + StackSwitchData->TssDesc == NULL ||
> > + StackSwitchData->Tss == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // The caller is responsible for that the GDT table, no matter the existing
> > + // one or newly allocated, has enough space to hold descriptors for
> exception
> > + // task-state segments.
> > + //
> > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0)
> {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc <
> (UINTN)(StackSwitchData->GdtTable))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc >=
> > + ((UINTN)(StackSwitchData->GdtTable) +
> StackSwitchData->GdtSize))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > + (UINTN)(StackSwitchData->GdtTable) +
> > + sizeof (IA32_TSS_DESCRIPTOR);
> > + if (GdtSize > StackSwitchData->GdtSize) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // Initialize new GDT table and/or IDT table, if any
> > + //
> > + AsmReadIdtr (&Idtr);
> > + AsmReadGdtr (&Gdtr);
> > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> 1);
> > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > + }
> > +
> > + //
> > + // Fixup current task descriptor. Task-state segment for current task will
> > + // be filled by processor during task switching.
> > + //
> > + TssDesc = StackSwitchData->TssDesc;
> > + Tss = StackSwitchData->Tss;
> > +
> > + TssBase = (UINTN)Tss;
> > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > + TssDesc->Bits.P = 1;
> > + TssDesc->Bits.LimitHigh = 0;
> > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > +
> > + //
> > + // Fixup exception task descriptor and task-state segment
> > + //
> > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> > + IdtTable = StackSwitchData->IdtTable;
> > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > + //
> > + // Fixup IST
> > + //
> > + Tss->IST[Index] = StackTop;
> > + StackTop -= StackSwitchData->StackSize;
> > +
> > + //
> > + // Set the IST field to enable corresponding IST
> > + //
> > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > (UINT8)(Index + 1);
> > + }
> > +
> > + //
> > + // Publish GDT
> > + //
> > + AsmWriteGdtr (&Gdtr);
> > +
> > + //
> > + // Load current task
> > + //
> > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > +
> > + //
> > + // Publish IDT
> > + //
> > + AsmWriteIdtr (&Idtr);
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > /**
> > Display CPU information.
> >
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > index 906480134a..c88be46286 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > @@ -43,4 +43,7 @@ typedef struct {
> > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > } RESERVED_VECTORS_DATA;
> >
> > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > +
> > #endif
> > --
> > 2.14.1.windows.1
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 5:50 ` Yao, Jiewen
2017-11-23 5:59 ` Yao, Jiewen
@ 2017-11-23 6:05 ` Wang, Jian J
2017-11-23 6:16 ` Yao, Jiewen
1 sibling, 1 reply; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 6:05 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
Cc: Zeng, Star, Dong, Eric, Kinney, Michael D
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 1:50 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Some thought:
>
> 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented in
> DxeException.c.
> What about Pei/Smm instance?
>
> I think it is OK to not implement it at this moment. But we need make sure no
> architecture issue if we want to enable it some time later.
>
Like what we discussed before, this series of patch is for Stack Guard feature which
is only available for DXE (because Stack Guard needs paging to work). Stack switch
is enabled for the sake of Stack Guard feature. So I think it's enough to implement
it in DxeException.c. In addition, SMM has its own implementation of stack guard
and stack switch. It's not necessary to do it again.
I agree with you that we should merge those common code but I think we should do
it in a separate patch series since it's not Stack Guard relevant. And I've removed
all architecture issues I can think of. Current stack switch initialization should work
for both PEI and SMM as well.
> 2) #define IA32_GDT_TYPE_TSS 0x9
> This is generic, can we move to BaseLib.h?
>
>
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Wednesday, November 22, 2017 4:46 PM
> > To: edk2-devel@lists.01.org
> > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>; Yao,
> > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>
> > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch
> > support
> >
> > > v2:
> > > a. Move common TSS structure and API definitions to BaseLib.h
> > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to setup
> > stack
> > > switch. This can avoid allocating memory for it in this library.
> > > c. Add globals to reserve memory for stack switch initialized in early
> > > phase of DXE core.
> > > d. Remove the filter code used to exclude boot modes which doesn't
> > support
> > > memory allocation because those memory can passed in by parameter
> > now.
> > > e. Remove the nasm macro to define exception handler one by one and
> > add a
> > > function to return the start address of each handler.
> >
> > If Stack Guard is enabled and there's really a stack overflow happened during
> > boot, a Page Fault exception will be triggered. Because the stack is out of
> > usage, the exception handler, which shares the stack with normal UEFI driver,
> > cannot be executed and cannot dump the processor information.
> >
> > Without those information, it's very difficult for the BIOS developers locate
> > the root cause of stack overflow. And without a workable stack, the developer
> > cannot event use single step to debug the UEFI driver with JTAG debugger.
> >
> > In order to make sure the exception handler to execute normally after stack
> > overflow. We need separate stacks for exception handlers in case of unusable
> > stack.
> >
> > IA processor allows to switch to a new stack during handling interrupt and
> > exception. But X64 and IA32 provides different ways to make it. X64 provides
> > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > new stack for its handler. IA32 doesn't have IST mechanism and can only use
> > task gate to do it since task switch allows to load a new stack through its
> > task-state segment (TSS).
> >
> > Cc: Star Zeng <star.zeng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > ---
> > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > .../Ia32/ArchInterruptDefs.h | 8 +
> > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > +++++++++++++++++++++
> > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > .../X64/ArchExceptionHandler.c | 133 +++++++
> > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > 11 files changed, 820 insertions(+), 1 deletion(-)
> > create mode 100644
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> >
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > index 740a58828b..30334105d2 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > @@ -48,6 +48,32 @@
> > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c,
> 0x83 }
> > \
> > }
> >
> > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > +
> > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > +
> > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > +
> > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> CPU_TSS_SIZE)
> > +
> > +#define IA32_GDT_TYPE_TSS 0x9
> > +#define IA32_GDT_ALIGNMENT 8
> > +
> > +typedef struct {
> > + UINTN StackTop;
> > + UINTN StackSize;
> > + UINT8 *Exceptions;
> > + UINTN ExceptionNumber;
> > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > + UINTN GdtSize;
> > + IA32_TSS_DESCRIPTOR *TssDesc;
> > + IA32_TASK_STATE_SEGMENT *Tss;
> > +} EXCEPTION_STACK_SWITCH_DATA;
> > +
> > //
> > // Record exception handler information
> > //
> > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > );
> >
> > +/**
> > + Setup separate stack for specific exceptions.
> > +
> > + @param[in] IdtTable IDT table base.
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArchSetupExcpetionStack (
> > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > + );
> > +
> > +/**
> > + Return address map of exception handler template so that C code can
> > generate
> > + exception tables. The template is only for exceptions using task gate instead
> > + of interrupt gate.
> > +
> > + @param AddressMap Pointer to a buffer where the address map is
> > returned.
> > +**/
> > +VOID
> > +EFIAPI
> > +AsmGetTssTemplateMap (
> > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > + );
> > +
> > #endif
> >
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > index f4a8d01c80..58e55a8a2e 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > @@ -47,6 +48,11 @@
> > PeiDxeSmmCpuException.c
> > DxeException.c
> >
> > +[Pcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > +
> > [Packages]
> > MdePkg/MdePkg.dec
> > MdeModulePkg/MdeModulePkg.dec
> > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > index 31febec976..c0b2c615aa 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > @@ -25,6 +25,10 @@ UINTN mEnabledInterruptNum =
> > 0;
> >
> > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> >
> > +UINT8
> > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > + CPU_KNOWN_GOOD_STACK_SIZE]
> > = {0};
> > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > +
> > /**
> > Common exception handler.
> >
> > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > )
> > {
> > + EFI_STATUS Status;
> > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > + IA32_DESCRIPTOR Idtr;
> > + IA32_DESCRIPTOR Gdtr;
> > +
> > mExceptionHandlerData.ReservedVectors =
> > mReservedVectorsData;
> > mExceptionHandlerData.ExternalInterruptHandler =
> > mExternalInterruptHandlerTable;
> > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > &mExceptionHandlerData);
> > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > &mExceptionHandlerData);
> > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > + AsmReadIdtr (&Idtr);
> > + AsmReadGdtr (&Gdtr);
> > +
> > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > + StackSwitchData.ExceptionNumber =
> > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
> > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > Gdtr.Limit + 1);
> > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > Gdtr.Limit + 1 +
> > +
> > CPU_TSS_DESC_SIZE);
> > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > + &StackSwitchData
> > + );
> > + }
> > + return Status;
> > }
> >
> > /**
> > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > {
> > return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler,
> > &mExceptionHandlerData);
> > }
> > +
> > +/**
> > + Setup separate stack for given exceptions. This is required by
> > + PcdCpuStackGuard feature.
> > +
> > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping up
> > + stack switch.
> > +
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +InitializeCpuExceptionStackSwitchHandlers (
> > + IN VOID *StackSwitchData OPTIONAL
> > + )
> > +{
> > + return ArchSetupExcpetionStack (StackSwitchData);
> > +}
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > index f2c39eb193..0aaf794795 100644
> > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > SystemContext.SystemContextIa32->ExceptionData =
> > ReservedVectors[ExceptionType].ExceptionData;
> > }
> >
> > +/**
> > + Setup separate stack for given exceptions.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > + stack switch.
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArchSetupExcpetionStack (
> > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > + )
> > +{
> > + IA32_DESCRIPTOR Gdtr;
> > + IA32_DESCRIPTOR Idtr;
> > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > + IA32_TSS_DESCRIPTOR *TssDesc;
> > + IA32_TASK_STATE_SEGMENT *Tss;
> > + UINTN StackTop;
> > + UINTN Index;
> > + UINTN Vector;
> > + UINTN TssBase;
> > + UINTN GdtSize;
> > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > +
> > + if (StackSwitchData == NULL ||
> > + StackSwitchData->StackTop == 0 ||
> > + StackSwitchData->StackSize == 0 ||
> > + StackSwitchData->Exceptions == NULL ||
> > + StackSwitchData->ExceptionNumber == 0 ||
> > + StackSwitchData->GdtTable == NULL ||
> > + StackSwitchData->IdtTable == NULL ||
> > + StackSwitchData->TssDesc == NULL ||
> > + StackSwitchData->Tss == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // The caller is responsible for that the GDT table, no matter the existing
> > + // one or newly allocated, has enough space to hold descriptors for
> exception
> > + // task-state segments.
> > + //
> > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0)
> {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> >GdtTable))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc >=
> > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > + (UINTN)(StackSwitchData->GdtTable) +
> > + sizeof (IA32_TSS_DESCRIPTOR) *
> > + (StackSwitchData->ExceptionNumber + 1);
> > + if (GdtSize > StackSwitchData->GdtSize) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // Initialize new GDT table and/or IDT table, if any
> > + //
> > + AsmReadIdtr (&Idtr);
> > + AsmReadGdtr (&Gdtr);
> > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
> > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > + }
> > +
> > + //
> > + // Fixup current task descriptor. Task-state segment for current task will
> > + // be filled by processor during task switching.
> > + //
> > + TssDesc = StackSwitchData->TssDesc;
> > + Tss = StackSwitchData->Tss;
> > +
> > + TssBase = (UINTN)Tss;
> > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > + TssDesc->Bits.P = 1;
> > + TssDesc->Bits.LimitHigh = 0;
> > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > +
> > + //
> > + // Fixup exception task descriptor and task-state segment
> > + //
> > + AsmGetTssTemplateMap (&TemplateMap);
> > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> > + IdtTable = StackSwitchData->IdtTable;
> > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > + TssDesc += 1;
> > + Tss += 1;
> > +
> > + //
> > + // Fixup TSS descriptor
> > + //
> > + TssBase = (UINTN)Tss;
> > +
> > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > + TssDesc->Bits.P = 1;
> > + TssDesc->Bits.LimitHigh = 0;
> > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > +
> > + //
> > + // Fixup TSS
> > + //
> > + Vector = StackSwitchData->Exceptions[Index];
> > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > + + Vector *
> > TemplateMap.ExceptionStubHeaderSize);
> > + Tss->EFLAGS = 0x2;
> > + Tss->ESP = StackTop;
> > + Tss->CR3 = AsmReadCr3 ();
> > + Tss->ES = AsmReadEs ();
> > + Tss->CS = AsmReadCs ();
> > + Tss->SS = AsmReadSs ();
> > + Tss->DS = AsmReadDs ();
> > + Tss->FS = AsmReadFs ();
> > + Tss->GS = AsmReadGs ();
> > +
> > + StackTop -= StackSwitchData->StackSize;
> > +
> > + //
> > + // Update IDT to use Task Gate for given exception
> > + //
> > + IdtTable[Vector].Bits.OffsetLow = 0;
> > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc - Gdtr.Base);
> > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > + }
> > +
> > + //
> > + // Publish GDT
> > + //
> > + AsmWriteGdtr (&Gdtr);
> > +
> > + //
> > + // Load current task
> > + //
> > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > +
> > + //
> > + // Publish IDT
> > + //
> > + AsmWriteIdtr (&Idtr);
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > /**
> > Display processor context.
> >
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > index a8d3556a80..d9ded5977f 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > @@ -41,4 +41,12 @@ typedef struct {
> > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > } RESERVED_VECTORS_DATA;
> >
> > +#define CPU_TSS_DESC_SIZE \
> > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > +
> > +#define CPU_TSS_SIZE \
> > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > +
> > #endif
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > m
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > m
> > new file mode 100644
> > index 0000000000..62bcedea1a
> > --- /dev/null
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > m
> > @@ -0,0 +1,398 @@
> > +;------------------------------------------------------------------------------ ;
> > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > +; This program and the accompanying materials
> > +; are licensed and made available under the terms and conditions of the BSD
> > License
> > +; which accompanies this distribution. The full text of the license may be
> found
> > at
> > +; http://opensource.org/licenses/bsd-license.php.
> > +;
> > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS
> > OR IMPLIED.
> > +;
> > +; Module Name:
> > +;
> > +; ExceptionTssEntryAsm.Asm
> > +;
> > +; Abstract:
> > +;
> > +; IA32 CPU Exception Handler with Separate Stack
> > +;
> > +; Notes:
> > +;
> > +;------------------------------------------------------------------------------
> > +
> > +;
> > +; IA32 TSS Memory Layout Description
> > +;
> > +struc IA32_TSS
> > + resw 1
> > + resw 1
> > + .ESP0: resd 1
> > + .SS0: resw 1
> > + resw 1
> > + .ESP1: resd 1
> > + .SS1: resw 1
> > + resw 1
> > + .ESP2: resd 1
> > + .SS2: resw 1
> > + resw 1
> > + ._CR3: resd 1
> > + .EIP: resd 1
> > + .EFLAGS: resd 1
> > + ._EAX: resd 1
> > + ._ECX: resd 1
> > + ._EDX: resd 1
> > + ._EBX: resd 1
> > + ._ESP: resd 1
> > + ._EBP: resd 1
> > + ._ESI: resd 1
> > + ._EDI: resd 1
> > + ._ES: resw 1
> > + resw 1
> > + ._CS: resw 1
> > + resw 1
> > + ._SS: resw 1
> > + resw 1
> > + ._DS: resw 1
> > + resw 1
> > + ._FS: resw 1
> > + resw 1
> > + ._GS: resw 1
> > + resw 1
> > + .LDT: resw 1
> > + resw 1
> > + resw 1
> > + resw 1
> > +endstruc
> > +
> > +;
> > +; CommonExceptionHandler()
> > +;
> > +extern ASM_PFX(CommonExceptionHandler)
> > +
> > +SECTION .data
> > +
> > +SECTION .text
> > +
> > +ALIGN 8
> > +
> > +;
> > +; Exception handler stub table
> > +;
> > +AsmExceptionEntryBegin:
> > +%assign Vector 0
> > +%rep 32
> > +
> > +DoIret%[Vector]:
> > + iretd
> > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > + db 0x6a ; push #VectorNum
> > + db %[Vector]
> > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > + call eax
> > + mov esp, eax ; Restore stack top
> > + jmp DoIret%[Vector]
> > +
> > +%assign Vector Vector+1
> > +%endrep
> > +AsmExceptionEntryEnd:
> > +
> > +;
> > +; Common part of exception handler
> > +;
> > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > + ;
> > + ; Stack:
> > + ; +---------------------+ <-- EBP - 8
> > + ; + TSS Base +
> > + ; +---------------------+ <-- EBP - 4
> > + ; + CPUID.EDX +
> > + ; +---------------------+ <-- EBP
> > + ; + EIP +
> > + ; +---------------------+ <-- EBP + 4
> > + ; + Vector Number +
> > + ; +---------------------+ <-- EBP + 8
> > + ; + Error Code +
> > + ; +---------------------+
> > + ;
> > +
> > + mov ebp, esp ; Stack frame
> > +
> > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > + mov eax, 1
> > + cpuid
> > + push edx
> > +
> > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > +; current TSS base
> > + sub esp, 8
> > + sgdt [esp + 2]
> > + mov eax, [esp + 4] ; GDT base
> > + add esp, 8
> > +
> > + xor ebx, ebx
> > + str bx ; Current TR
> > +
> > + mov ecx, [eax + ebx + 2]
> > + shl ecx, 8
> > + mov cl, [eax + ebx + 7]
> > + ror ecx, 8 ; ecx = Current TSS base
> > + push ecx ; keep it in stack for later use
> > +
> > + movzx ebx, word [ecx] ; Previous Task Link
> > + mov ecx, [eax + ebx + 2]
> > + shl ecx, 8
> > + mov cl, [eax + ebx + 7]
> > + ror ecx, 8 ; ecx = Previous TSS base
> > +
> > +;
> > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > EFI_SYSTEM_CONTEXT_IA32
> > +; is 16-byte aligned
> > +;
> > + and esp, 0xfffffff0
> > + sub esp, 12
> > +
> > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > + push dword [ecx + IA32_TSS._EAX]
> > + push dword [ecx + IA32_TSS._ECX]
> > + push dword [ecx + IA32_TSS._EDX]
> > + push dword [ecx + IA32_TSS._EBX]
> > + push dword [ecx + IA32_TSS._ESP]
> > + push dword [ecx + IA32_TSS._EBP]
> > + push dword [ecx + IA32_TSS._ESI]
> > + push dword [ecx + IA32_TSS._EDI]
> > +
> > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > + movzx eax, word [ecx + IA32_TSS._SS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._CS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._DS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._ES]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._FS]
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS._GS]
> > + push eax
> > +
> > +;; UINT32 Eip;
> > + push dword [ecx + IA32_TSS.EIP]
> > +
> > +;; UINT32 Gdtr[2], Idtr[2];
> > + sub esp, 8
> > + sidt [esp]
> > + mov eax, [esp + 2]
> > + xchg eax, [esp]
> > + and eax, 0xFFFF
> > + mov [esp+4], eax
> > +
> > + sub esp, 8
> > + sgdt [esp]
> > + mov eax, [esp + 2]
> > + xchg eax, [esp]
> > + and eax, 0xFFFF
> > + mov [esp+4], eax
> > +
> > +;; UINT32 Ldtr, Tr;
> > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > + push eax
> > + movzx eax, word [ecx + IA32_TSS.LDT]
> > + push eax
> > +
> > +;; UINT32 EFlags;
> > + push dword [ecx + IA32_TSS.EFLAGS]
> > +
> > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > + mov eax, cr4
> > + push eax ; push cr4 firstly
> > +
> > + mov edx, [ebp - 4] ; cpuid.edx
> > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > + jz .1
> > + or eax, BIT9 ; Set CR4.OSFXSR
> > +.1:
> > + test edx, BIT2 ; Test for Debugging Extensions support
> > + jz .2
> > + or eax, BIT3 ; Set CR4.DE
> > +.2:
> > + mov cr4, eax
> > +
> > + mov eax, cr3
> > + push eax
> > + mov eax, cr2
> > + push eax
> > + xor eax, eax
> > + push eax
> > + mov eax, cr0
> > + push eax
> > +
> > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > + mov eax, dr7
> > + push eax
> > + mov eax, dr6
> > + push eax
> > + mov eax, dr3
> > + push eax
> > + mov eax, dr2
> > + push eax
> > + mov eax, dr1
> > + push eax
> > + mov eax, dr0
> > + push eax
> > +
> > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > +;; when executing fxsave/fxrstor instruction
> > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > + ; edx still contains result from CPUID above
> > + jz .3
> > + clts
> > + sub esp, 512
> > + mov edi, esp
> > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > +.3:
> > +
> > +;; UINT32 ExceptionData;
> > + push dword [ebp + 8]
> > +
> > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is
> clear
> > + cld
> > +
> > +;; call into exception handler
> > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > + mov eax, ASM_PFX(CommonExceptionHandler)
> > +
> > +;; Prepare parameter and call
> > + mov edx, esp
> > + push edx ; EFI_SYSTEM_CONTEXT
> > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > +
> > + ;
> > + ; Call External Exception Handler
> > + ;
> > + call eax
> > + add esp, 8 ; Restore stack before calling
> > + mov ecx, esi ; Restore TSS base
> > +
> > +;; UINT32 ExceptionData;
> > + add esp, 4
> > +
> > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > + mov edx, [ebp - 4] ; cpuid.edx
> > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > + jz .4
> > + mov esi, esp
> > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > +.4:
> > + add esp, 512
> > +
> > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > +;; Skip restoration of DRx registers to support debuggers
> > +;; that set breakpoints in interrupt/exception context
> > + add esp, 4 * 6
> > +
> > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > + pop eax
> > + mov cr0, eax
> > + add esp, 4 ; not for Cr1
> > + pop eax
> > + mov cr2, eax
> > + pop eax
> > + mov dword [ecx + IA32_TSS._CR3], eax
> > + pop eax
> > + mov cr4, eax
> > +
> > +;; UINT32 EFlags;
> > + pop dword [ecx + IA32_TSS.EFLAGS]
> > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > + btr ebx, 9 ; Do 'cli'
> > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > +
> > +;; UINT32 Ldtr, Tr;
> > +;; UINT32 Gdtr[2], Idtr[2];
> > +;; Best not let anyone mess with these particular registers...
> > + add esp, 24
> > +
> > +;; UINT32 Eip;
> > + pop dword [ecx + IA32_TSS.EIP]
> > +
> > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > +;; NOTE - modified segment registers could hang the debugger... We
> > +;; could attempt to insulate ourselves against this possibility,
> > +;; but that poses risks as well.
> > +;;
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._GS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._FS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._ES], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._DS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._CS], ax
> > + pop eax
> > +o16 mov [ecx + IA32_TSS._SS], ax
> > +
> > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > + pop dword [ecx + IA32_TSS._EDI]
> > + pop dword [ecx + IA32_TSS._ESI]
> > + add esp, 4 ; not for ebp
> > + add esp, 4 ; not for esp
> > + pop dword [ecx + IA32_TSS._EBX]
> > + pop dword [ecx + IA32_TSS._EDX]
> > + pop dword [ecx + IA32_TSS._ECX]
> > + pop dword [ecx + IA32_TSS._EAX]
> > +
> > +; Set single step DB# to allow debugger to able to go back to the EIP
> > +; where the exception is triggered.
> > +
> > +;; Create return context for iretd in stub function
> > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > + mov [eax - 0xc], ebx ; create EIP in old stack
> > + movzx ebx, word [ecx + IA32_TSS._CS]
> > + mov [eax - 0x8], ebx ; create CS in old stack
> > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > + bts ebx, 8
> > + mov [eax - 0x4], ebx ; create eflags in old stack
> > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS
> > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> > + sub eax, 0xc ; minus 12 byte
> > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
> > +
> > +;; Replace the EIP of interrupted task with stub function
> > + mov eax, ASM_PFX(SingleStepStubFunction)
> > + mov dword [ecx + IA32_TSS.EIP], eax
> > +
> > + mov ecx, [ebp - 8] ; Get current TSS base
> > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack top
> > + mov esp, ebp
> > +
> > + ret
> > +
> > +global ASM_PFX(SingleStepStubFunction)
> > +ASM_PFX(SingleStepStubFunction):
> > +;
> > +; we need clean TS bit in CR0 to execute
> > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > +;
> > + clts
> > + iretd
> > +
> > +global ASM_PFX(AsmGetTssTemplateMap)
> > +ASM_PFX(AsmGetTssTemplateMap):
> > + push ebp ; C prolog
> > + mov ebp, esp
> > + pushad
> > +
> > + mov ebx, dword [ebp + 0x8]
> > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd - AsmExceptionEntryBegin)
> > / 32
> > + mov dword [ebx + 0x8], 0
> > +
> > + popad
> > + pop ebp
> > + ret
> > +
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > index 75443288a9..4c0d435136 100644
> > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> > index d70a99c100..e5c03c16c9 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > nf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > index 634ffcb21d..56b875b7c8 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > @@ -30,6 +30,7 @@
> > [Sources.Ia32]
> > Ia32/ExceptionHandlerAsm.asm
> > Ia32/ExceptionHandlerAsm.nasm
> > + Ia32/ExceptionTssEntryAsm.nasm
> > Ia32/ExceptionHandlerAsm.S
> > Ia32/ArchExceptionHandler.c
> > Ia32/ArchInterruptDefs.h
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > index 65f0cff680..214aafcc13 100644
> > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > SystemContext.SystemContextX64->ExceptionData =
> > ReservedVectors[ExceptionType].ExceptionData;
> > }
> >
> > +/**
> > + Setup separate stack for given exceptions.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping up
> > + stack switch.
> > +
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArchSetupExcpetionStack (
> > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > + )
> > +{
> > + IA32_DESCRIPTOR Gdtr;
> > + IA32_DESCRIPTOR Idtr;
> > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > + IA32_TSS_DESCRIPTOR *TssDesc;
> > + IA32_TASK_STATE_SEGMENT *Tss;
> > + UINTN StackTop;
> > + UINTN Index;
> > + UINTN TssBase;
> > + UINTN GdtSize;
> > +
> > + if (StackSwitchData == NULL ||
> > + StackSwitchData->StackTop == 0 ||
> > + StackSwitchData->StackSize == 0 ||
> > + StackSwitchData->Exceptions == NULL ||
> > + StackSwitchData->ExceptionNumber == 0 ||
> > + StackSwitchData->GdtTable == NULL ||
> > + StackSwitchData->IdtTable == NULL ||
> > + StackSwitchData->TssDesc == NULL ||
> > + StackSwitchData->Tss == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // The caller is responsible for that the GDT table, no matter the existing
> > + // one or newly allocated, has enough space to hold descriptors for
> exception
> > + // task-state segments.
> > + //
> > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0)
> {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> >GdtTable))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->TssDesc >=
> > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize))
> > {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > + (UINTN)(StackSwitchData->GdtTable) +
> > + sizeof (IA32_TSS_DESCRIPTOR);
> > + if (GdtSize > StackSwitchData->GdtSize) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // Initialize new GDT table and/or IDT table, if any
> > + //
> > + AsmReadIdtr (&Idtr);
> > + AsmReadGdtr (&Gdtr);
> > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
> > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > + }
> > +
> > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > + }
> > +
> > + //
> > + // Fixup current task descriptor. Task-state segment for current task will
> > + // be filled by processor during task switching.
> > + //
> > + TssDesc = StackSwitchData->TssDesc;
> > + Tss = StackSwitchData->Tss;
> > +
> > + TssBase = (UINTN)Tss;
> > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > + TssDesc->Bits.P = 1;
> > + TssDesc->Bits.LimitHigh = 0;
> > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > +
> > + //
> > + // Fixup exception task descriptor and task-state segment
> > + //
> > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> > + IdtTable = StackSwitchData->IdtTable;
> > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > + //
> > + // Fixup IST
> > + //
> > + Tss->IST[Index] = StackTop;
> > + StackTop -= StackSwitchData->StackSize;
> > +
> > + //
> > + // Set the IST field to enable corresponding IST
> > + //
> > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > (UINT8)(Index + 1);
> > + }
> > +
> > + //
> > + // Publish GDT
> > + //
> > + AsmWriteGdtr (&Gdtr);
> > +
> > + //
> > + // Load current task
> > + //
> > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > +
> > + //
> > + // Publish IDT
> > + //
> > + AsmWriteIdtr (&Idtr);
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > /**
> > Display CPU information.
> >
> > diff --git
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > index 906480134a..c88be46286 100644
> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > @@ -43,4 +43,7 @@ typedef struct {
> > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > } RESERVED_VECTORS_DATA;
> >
> > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > +
> > #endif
> > --
> > 2.14.1.windows.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 5:59 ` Yao, Jiewen
@ 2017-11-23 6:09 ` Wang, Jian J
2017-11-23 6:25 ` Yao, Jiewen
0 siblings, 1 reply; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 6:09 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
If PcdCpuStackGuard is not enabled, there's no impact. If it's enabled, the only
issue is that the exception dump cannot be done but no other impact. From this
point of view, maybe PcdCpuStackGuard should be FALSE by default.
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 1:59 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J <jian.j.wang@intel.com>;
> edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> One more question:
> I notice not all platforms are using the CpuDxe in UefiCpuPkg.
> If so, is there any impact to the platform whose CPU driver does not have such
> InitializeCpuExceptionStackSwitchHandlers() call?
> Have you tested that condition?
>
> Thank you
> Yao Jiewen
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Yao,
> > Jiewen
> > Sent: Thursday, November 23, 2017 1:50 PM
> > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> > <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> > stack switch support
> >
> > Some thought:
> >
> > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented in
> > DxeException.c.
> > What about Pei/Smm instance?
> >
> > I think it is OK to not implement it at this moment. But we need make sure no
> > architecture issue if we want to enable it some time later.
> >
> > 2) #define IA32_GDT_TYPE_TSS 0x9
> > This is generic, can we move to BaseLib.h?
> >
> >
> > Thank you
> > Yao Jiewen
> >
> >
> > > -----Original Message-----
> > > From: Wang, Jian J
> > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > To: edk2-devel@lists.01.org
> > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Yao,
> > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > <michael.d.kinney@intel.com>
> > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch
> > > support
> > >
> > > > v2:
> > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to setup
> > > stack
> > > > switch. This can avoid allocating memory for it in this library.
> > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > phase of DXE core.
> > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > support
> > > > memory allocation because those memory can passed in by
> > parameter
> > > now.
> > > > e. Remove the nasm macro to define exception handler one by one and
> > > add a
> > > > function to return the start address of each handler.
> > >
> > > If Stack Guard is enabled and there's really a stack overflow happened during
> > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > usage, the exception handler, which shares the stack with normal UEFI driver,
> > > cannot be executed and cannot dump the processor information.
> > >
> > > Without those information, it's very difficult for the BIOS developers locate
> > > the root cause of stack overflow. And without a workable stack, the
> developer
> > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > >
> > > In order to make sure the exception handler to execute normally after stack
> > > overflow. We need separate stacks for exception handlers in case of
> unusable
> > > stack.
> > >
> > > IA processor allows to switch to a new stack during handling interrupt and
> > > exception. But X64 and IA32 provides different ways to make it. X64 provides
> > > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > > new stack for its handler. IA32 doesn't have IST mechanism and can only use
> > > task gate to do it since task switch allows to load a new stack through its
> > > task-state segment (TSS).
> > >
> > > Cc: Star Zeng <star.zeng@intel.com>
> > > Cc: Eric Dong <eric.dong@intel.com>
> > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > ---
> > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > +++++++++++++++++++++
> > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > create mode 100644
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > >
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > index 740a58828b..30334105d2 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > @@ -48,6 +48,32 @@
> > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c,
> > 0x83 }
> > > \
> > > }
> > >
> > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > +
> > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > +
> > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > +
> > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > CPU_TSS_SIZE)
> > > +
> > > +#define IA32_GDT_TYPE_TSS 0x9
> > > +#define IA32_GDT_ALIGNMENT 8
> > > +
> > > +typedef struct {
> > > + UINTN StackTop;
> > > + UINTN StackSize;
> > > + UINT8 *Exceptions;
> > > + UINTN ExceptionNumber;
> > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > + UINTN GdtSize;
> > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > +
> > > //
> > > // Record exception handler information
> > > //
> > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > );
> > >
> > > +/**
> > > + Setup separate stack for specific exceptions.
> > > +
> > > + @param[in] IdtTable IDT table base.
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +ArchSetupExcpetionStack (
> > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > + );
> > > +
> > > +/**
> > > + Return address map of exception handler template so that C code can
> > > generate
> > > + exception tables. The template is only for exceptions using task gate
> > instead
> > > + of interrupt gate.
> > > +
> > > + @param AddressMap Pointer to a buffer where the address map is
> > > returned.
> > > +**/
> > > +VOID
> > > +EFIAPI
> > > +AsmGetTssTemplateMap (
> > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > + );
> > > +
> > > #endif
> > >
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > index f4a8d01c80..58e55a8a2e 100644
> > > ---
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > @@ -47,6 +48,11 @@
> > > PeiDxeSmmCpuException.c
> > > DxeException.c
> > >
> > > +[Pcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > +
> > > [Packages]
> > > MdePkg/MdePkg.dec
> > > MdeModulePkg/MdeModulePkg.dec
> > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > index 31febec976..c0b2c615aa 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > @@ -25,6 +25,10 @@ UINTN mEnabledInterruptNum
> > =
> > > 0;
> > >
> > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > >
> > > +UINT8
> > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > +
> > CPU_KNOWN_GOOD_STACK_SIZE]
> > > = {0};
> > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > +
> > > /**
> > > Common exception handler.
> > >
> > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > )
> > > {
> > > + EFI_STATUS Status;
> > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > + IA32_DESCRIPTOR Idtr;
> > > + IA32_DESCRIPTOR Gdtr;
> > > +
> > > mExceptionHandlerData.ReservedVectors =
> > > mReservedVectorsData;
> > > mExceptionHandlerData.ExternalInterruptHandler =
> > > mExternalInterruptHandlerTable;
> > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > &mExceptionHandlerData);
> > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > &mExceptionHandlerData);
> > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > + AsmReadIdtr (&Idtr);
> > > + AsmReadGdtr (&Gdtr);
> > > +
> > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > + StackSwitchData.ExceptionNumber =
> > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
> > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > Gdtr.Limit + 1);
> > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > Gdtr.Limit + 1 +
> > > +
> > > CPU_TSS_DESC_SIZE);
> > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > + &StackSwitchData
> > > + );
> > > + }
> > > + return Status;
> > > }
> > >
> > > /**
> > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > {
> > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > InterruptHandler,
> > > &mExceptionHandlerData);
> > > }
> > > +
> > > +/**
> > > + Setup separate stack for given exceptions. This is required by
> > > + PcdCpuStackGuard feature.
> > > +
> > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > +
> > > + @param[in] StackSwitchData Pointer to data required for setuping up
> > > + stack switch.
> > > +
> > > + @retval EFI_SUCCESS The exceptions have been successfully
> > > + initialized.
> > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > content.
> > > +
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +InitializeCpuExceptionStackSwitchHandlers (
> > > + IN VOID *StackSwitchData OPTIONAL
> > > + )
> > > +{
> > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > +}
> > > diff --git
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > index f2c39eb193..0aaf794795 100644
> > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > +++
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > SystemContext.SystemContextIa32->ExceptionData =
> > > ReservedVectors[ExceptionType].ExceptionData;
> > > }
> > >
> > > +/**
> > > + Setup separate stack for given exceptions.
> > > +
> > > + @param[in] StackSwitchData Pointer to data required for setuping
> > > up
> > > + stack switch.
> > > + @retval EFI_SUCCESS The exceptions have been successfully
> > > + initialized.
> > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > content.
> > > +
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +ArchSetupExcpetionStack (
> > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > + )
> > > +{
> > > + IA32_DESCRIPTOR Gdtr;
> > > + IA32_DESCRIPTOR Idtr;
> > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > + UINTN StackTop;
> > > + UINTN Index;
> > > + UINTN Vector;
> > > + UINTN TssBase;
> > > + UINTN GdtSize;
> > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > +
> > > + if (StackSwitchData == NULL ||
> > > + StackSwitchData->StackTop == 0 ||
> > > + StackSwitchData->StackSize == 0 ||
> > > + StackSwitchData->Exceptions == NULL ||
> > > + StackSwitchData->ExceptionNumber == 0 ||
> > > + StackSwitchData->GdtTable == NULL ||
> > > + StackSwitchData->IdtTable == NULL ||
> > > + StackSwitchData->TssDesc == NULL ||
> > > + StackSwitchData->Tss == NULL) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // The caller is responsible for that the GDT table, no matter the existing
> > > + // one or newly allocated, has enough space to hold descriptors for
> > exception
> > > + // task-state segments.
> > > + //
> > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=
> 0)
> > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc <
> > (UINTN)(StackSwitchData->GdtTable))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > + (UINTN)(StackSwitchData->GdtTable) +
> > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > + (StackSwitchData->ExceptionNumber + 1);
> > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // Initialize new GDT table and/or IDT table, if any
> > > + //
> > > + AsmReadIdtr (&Idtr);
> > > + AsmReadGdtr (&Gdtr);
> > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > + }
> > > +
> > > + //
> > > + // Fixup current task descriptor. Task-state segment for current task will
> > > + // be filled by processor during task switching.
> > > + //
> > > + TssDesc = StackSwitchData->TssDesc;
> > > + Tss = StackSwitchData->Tss;
> > > +
> > > + TssBase = (UINTN)Tss;
> > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > + TssDesc->Bits.P = 1;
> > > + TssDesc->Bits.LimitHigh = 0;
> > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > +
> > > + //
> > > + // Fixup exception task descriptor and task-state segment
> > > + //
> > > + AsmGetTssTemplateMap (&TemplateMap);
> > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> > > + IdtTable = StackSwitchData->IdtTable;
> > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > + TssDesc += 1;
> > > + Tss += 1;
> > > +
> > > + //
> > > + // Fixup TSS descriptor
> > > + //
> > > + TssBase = (UINTN)Tss;
> > > +
> > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > + TssDesc->Bits.P = 1;
> > > + TssDesc->Bits.LimitHigh = 0;
> > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > +
> > > + //
> > > + // Fixup TSS
> > > + //
> > > + Vector = StackSwitchData->Exceptions[Index];
> > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > + + Vector *
> > > TemplateMap.ExceptionStubHeaderSize);
> > > + Tss->EFLAGS = 0x2;
> > > + Tss->ESP = StackTop;
> > > + Tss->CR3 = AsmReadCr3 ();
> > > + Tss->ES = AsmReadEs ();
> > > + Tss->CS = AsmReadCs ();
> > > + Tss->SS = AsmReadSs ();
> > > + Tss->DS = AsmReadDs ();
> > > + Tss->FS = AsmReadFs ();
> > > + Tss->GS = AsmReadGs ();
> > > +
> > > + StackTop -= StackSwitchData->StackSize;
> > > +
> > > + //
> > > + // Update IDT to use Task Gate for given exception
> > > + //
> > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc - Gdtr.Base);
> > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > + }
> > > +
> > > + //
> > > + // Publish GDT
> > > + //
> > > + AsmWriteGdtr (&Gdtr);
> > > +
> > > + //
> > > + // Load current task
> > > + //
> > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > +
> > > + //
> > > + // Publish IDT
> > > + //
> > > + AsmWriteIdtr (&Idtr);
> > > +
> > > + return EFI_SUCCESS;
> > > +}
> > > +
> > > /**
> > > Display processor context.
> > >
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > index a8d3556a80..d9ded5977f 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > @@ -41,4 +41,12 @@ typedef struct {
> > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > } RESERVED_VECTORS_DATA;
> > >
> > > +#define CPU_TSS_DESC_SIZE \
> > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > +
> > > +#define CPU_TSS_SIZE \
> > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > +
> > > #endif
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > m
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > m
> > > new file mode 100644
> > > index 0000000000..62bcedea1a
> > > --- /dev/null
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > m
> > > @@ -0,0 +1,398 @@
> > > +;------------------------------------------------------------------------------ ;
> > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > +; This program and the accompanying materials
> > > +; are licensed and made available under the terms and conditions of the BSD
> > > License
> > > +; which accompanies this distribution. The full text of the license may be
> > found
> > > at
> > > +; http://opensource.org/licenses/bsd-license.php.
> > > +;
> > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > BASIS,
> > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS
> > > OR IMPLIED.
> > > +;
> > > +; Module Name:
> > > +;
> > > +; ExceptionTssEntryAsm.Asm
> > > +;
> > > +; Abstract:
> > > +;
> > > +; IA32 CPU Exception Handler with Separate Stack
> > > +;
> > > +; Notes:
> > > +;
> > > +;------------------------------------------------------------------------------
> > > +
> > > +;
> > > +; IA32 TSS Memory Layout Description
> > > +;
> > > +struc IA32_TSS
> > > + resw 1
> > > + resw 1
> > > + .ESP0: resd 1
> > > + .SS0: resw 1
> > > + resw 1
> > > + .ESP1: resd 1
> > > + .SS1: resw 1
> > > + resw 1
> > > + .ESP2: resd 1
> > > + .SS2: resw 1
> > > + resw 1
> > > + ._CR3: resd 1
> > > + .EIP: resd 1
> > > + .EFLAGS: resd 1
> > > + ._EAX: resd 1
> > > + ._ECX: resd 1
> > > + ._EDX: resd 1
> > > + ._EBX: resd 1
> > > + ._ESP: resd 1
> > > + ._EBP: resd 1
> > > + ._ESI: resd 1
> > > + ._EDI: resd 1
> > > + ._ES: resw 1
> > > + resw 1
> > > + ._CS: resw 1
> > > + resw 1
> > > + ._SS: resw 1
> > > + resw 1
> > > + ._DS: resw 1
> > > + resw 1
> > > + ._FS: resw 1
> > > + resw 1
> > > + ._GS: resw 1
> > > + resw 1
> > > + .LDT: resw 1
> > > + resw 1
> > > + resw 1
> > > + resw 1
> > > +endstruc
> > > +
> > > +;
> > > +; CommonExceptionHandler()
> > > +;
> > > +extern ASM_PFX(CommonExceptionHandler)
> > > +
> > > +SECTION .data
> > > +
> > > +SECTION .text
> > > +
> > > +ALIGN 8
> > > +
> > > +;
> > > +; Exception handler stub table
> > > +;
> > > +AsmExceptionEntryBegin:
> > > +%assign Vector 0
> > > +%rep 32
> > > +
> > > +DoIret%[Vector]:
> > > + iretd
> > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > + db 0x6a ; push #VectorNum
> > > + db %[Vector]
> > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > + call eax
> > > + mov esp, eax ; Restore stack top
> > > + jmp DoIret%[Vector]
> > > +
> > > +%assign Vector Vector+1
> > > +%endrep
> > > +AsmExceptionEntryEnd:
> > > +
> > > +;
> > > +; Common part of exception handler
> > > +;
> > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > + ;
> > > + ; Stack:
> > > + ; +---------------------+ <-- EBP - 8
> > > + ; + TSS Base +
> > > + ; +---------------------+ <-- EBP - 4
> > > + ; + CPUID.EDX +
> > > + ; +---------------------+ <-- EBP
> > > + ; + EIP +
> > > + ; +---------------------+ <-- EBP + 4
> > > + ; + Vector Number +
> > > + ; +---------------------+ <-- EBP + 8
> > > + ; + Error Code +
> > > + ; +---------------------+
> > > + ;
> > > +
> > > + mov ebp, esp ; Stack frame
> > > +
> > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > + mov eax, 1
> > > + cpuid
> > > + push edx
> > > +
> > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > +; current TSS base
> > > + sub esp, 8
> > > + sgdt [esp + 2]
> > > + mov eax, [esp + 4] ; GDT base
> > > + add esp, 8
> > > +
> > > + xor ebx, ebx
> > > + str bx ; Current TR
> > > +
> > > + mov ecx, [eax + ebx + 2]
> > > + shl ecx, 8
> > > + mov cl, [eax + ebx + 7]
> > > + ror ecx, 8 ; ecx = Current TSS base
> > > + push ecx ; keep it in stack for later use
> > > +
> > > + movzx ebx, word [ecx] ; Previous Task Link
> > > + mov ecx, [eax + ebx + 2]
> > > + shl ecx, 8
> > > + mov cl, [eax + ebx + 7]
> > > + ror ecx, 8 ; ecx = Previous TSS base
> > > +
> > > +;
> > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > EFI_SYSTEM_CONTEXT_IA32
> > > +; is 16-byte aligned
> > > +;
> > > + and esp, 0xfffffff0
> > > + sub esp, 12
> > > +
> > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > + push dword [ecx + IA32_TSS._EAX]
> > > + push dword [ecx + IA32_TSS._ECX]
> > > + push dword [ecx + IA32_TSS._EDX]
> > > + push dword [ecx + IA32_TSS._EBX]
> > > + push dword [ecx + IA32_TSS._ESP]
> > > + push dword [ecx + IA32_TSS._EBP]
> > > + push dword [ecx + IA32_TSS._ESI]
> > > + push dword [ecx + IA32_TSS._EDI]
> > > +
> > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > + push eax
> > > +
> > > +;; UINT32 Eip;
> > > + push dword [ecx + IA32_TSS.EIP]
> > > +
> > > +;; UINT32 Gdtr[2], Idtr[2];
> > > + sub esp, 8
> > > + sidt [esp]
> > > + mov eax, [esp + 2]
> > > + xchg eax, [esp]
> > > + and eax, 0xFFFF
> > > + mov [esp+4], eax
> > > +
> > > + sub esp, 8
> > > + sgdt [esp]
> > > + mov eax, [esp + 2]
> > > + xchg eax, [esp]
> > > + and eax, 0xFFFF
> > > + mov [esp+4], eax
> > > +
> > > +;; UINT32 Ldtr, Tr;
> > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > + push eax
> > > +
> > > +;; UINT32 EFlags;
> > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > +
> > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > + mov eax, cr4
> > > + push eax ; push cr4 firstly
> > > +
> > > + mov edx, [ebp - 4] ; cpuid.edx
> > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > + jz .1
> > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > +.1:
> > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > + jz .2
> > > + or eax, BIT3 ; Set CR4.DE
> > > +.2:
> > > + mov cr4, eax
> > > +
> > > + mov eax, cr3
> > > + push eax
> > > + mov eax, cr2
> > > + push eax
> > > + xor eax, eax
> > > + push eax
> > > + mov eax, cr0
> > > + push eax
> > > +
> > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > + mov eax, dr7
> > > + push eax
> > > + mov eax, dr6
> > > + push eax
> > > + mov eax, dr3
> > > + push eax
> > > + mov eax, dr2
> > > + push eax
> > > + mov eax, dr1
> > > + push eax
> > > + mov eax, dr0
> > > + push eax
> > > +
> > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > +;; when executing fxsave/fxrstor instruction
> > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > + ; edx still contains result from CPUID above
> > > + jz .3
> > > + clts
> > > + sub esp, 512
> > > + mov edi, esp
> > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > +.3:
> > > +
> > > +;; UINT32 ExceptionData;
> > > + push dword [ebp + 8]
> > > +
> > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is
> clear
> > > + cld
> > > +
> > > +;; call into exception handler
> > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > +
> > > +;; Prepare parameter and call
> > > + mov edx, esp
> > > + push edx ; EFI_SYSTEM_CONTEXT
> > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > > +
> > > + ;
> > > + ; Call External Exception Handler
> > > + ;
> > > + call eax
> > > + add esp, 8 ; Restore stack before calling
> > > + mov ecx, esi ; Restore TSS base
> > > +
> > > +;; UINT32 ExceptionData;
> > > + add esp, 4
> > > +
> > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > + mov edx, [ebp - 4] ; cpuid.edx
> > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > + jz .4
> > > + mov esi, esp
> > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > +.4:
> > > + add esp, 512
> > > +
> > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > +;; Skip restoration of DRx registers to support debuggers
> > > +;; that set breakpoints in interrupt/exception context
> > > + add esp, 4 * 6
> > > +
> > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > + pop eax
> > > + mov cr0, eax
> > > + add esp, 4 ; not for Cr1
> > > + pop eax
> > > + mov cr2, eax
> > > + pop eax
> > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > + pop eax
> > > + mov cr4, eax
> > > +
> > > +;; UINT32 EFlags;
> > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > + btr ebx, 9 ; Do 'cli'
> > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > +
> > > +;; UINT32 Ldtr, Tr;
> > > +;; UINT32 Gdtr[2], Idtr[2];
> > > +;; Best not let anyone mess with these particular registers...
> > > + add esp, 24
> > > +
> > > +;; UINT32 Eip;
> > > + pop dword [ecx + IA32_TSS.EIP]
> > > +
> > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > +;; NOTE - modified segment registers could hang the debugger... We
> > > +;; could attempt to insulate ourselves against this possibility,
> > > +;; but that poses risks as well.
> > > +;;
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > +
> > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > + pop dword [ecx + IA32_TSS._EDI]
> > > + pop dword [ecx + IA32_TSS._ESI]
> > > + add esp, 4 ; not for ebp
> > > + add esp, 4 ; not for esp
> > > + pop dword [ecx + IA32_TSS._EBX]
> > > + pop dword [ecx + IA32_TSS._EDX]
> > > + pop dword [ecx + IA32_TSS._ECX]
> > > + pop dword [ecx + IA32_TSS._EAX]
> > > +
> > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > +; where the exception is triggered.
> > > +
> > > +;; Create return context for iretd in stub function
> > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > + mov [eax - 0xc], ebx ; create EIP in old stack
> > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > + mov [eax - 0x8], ebx ; create CS in old stack
> > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > + bts ebx, 8
> > > + mov [eax - 0x4], ebx ; create eflags in old
> > stack
> > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old
> > TSS
> > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
> > > + sub eax, 0xc ; minus 12 byte
> > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
> > > +
> > > +;; Replace the EIP of interrupted task with stub function
> > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > +
> > > + mov ecx, [ebp - 8] ; Get current TSS base
> > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack
> > top
> > > + mov esp, ebp
> > > +
> > > + ret
> > > +
> > > +global ASM_PFX(SingleStepStubFunction)
> > > +ASM_PFX(SingleStepStubFunction):
> > > +;
> > > +; we need clean TS bit in CR0 to execute
> > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > +;
> > > + clts
> > > + iretd
> > > +
> > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > +ASM_PFX(AsmGetTssTemplateMap):
> > > + push ebp ; C prolog
> > > + mov ebp, esp
> > > + pushad
> > > +
> > > + mov ebx, dword [ebp + 0x8]
> > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > AsmExceptionEntryBegin)
> > > / 32
> > > + mov dword [ebx + 0x8], 0
> > > +
> > > + popad
> > > + pop ebp
> > > + ret
> > > +
> > > diff --git
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > index 75443288a9..4c0d435136 100644
> > > ---
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > +++
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > > index d70a99c100..e5c03c16c9 100644
> > > ---
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > index 634ffcb21d..56b875b7c8 100644
> > > ---
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > index 65f0cff680..214aafcc13 100644
> > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > SystemContext.SystemContextX64->ExceptionData =
> > > ReservedVectors[ExceptionType].ExceptionData;
> > > }
> > >
> > > +/**
> > > + Setup separate stack for given exceptions.
> > > +
> > > + @param[in] StackSwitchData Pointer to data required for setuping up
> > > + stack switch.
> > > +
> > > + @retval EFI_SUCCESS The exceptions have been successfully
> > > + initialized.
> > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > content.
> > > +
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +ArchSetupExcpetionStack (
> > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > + )
> > > +{
> > > + IA32_DESCRIPTOR Gdtr;
> > > + IA32_DESCRIPTOR Idtr;
> > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > + UINTN StackTop;
> > > + UINTN Index;
> > > + UINTN TssBase;
> > > + UINTN GdtSize;
> > > +
> > > + if (StackSwitchData == NULL ||
> > > + StackSwitchData->StackTop == 0 ||
> > > + StackSwitchData->StackSize == 0 ||
> > > + StackSwitchData->Exceptions == NULL ||
> > > + StackSwitchData->ExceptionNumber == 0 ||
> > > + StackSwitchData->GdtTable == NULL ||
> > > + StackSwitchData->IdtTable == NULL ||
> > > + StackSwitchData->TssDesc == NULL ||
> > > + StackSwitchData->Tss == NULL) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // The caller is responsible for that the GDT table, no matter the existing
> > > + // one or newly allocated, has enough space to hold descriptors for
> > exception
> > > + // task-state segments.
> > > + //
> > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=
> 0)
> > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc <
> > (UINTN)(StackSwitchData->GdtTable))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > + (UINTN)(StackSwitchData->GdtTable) +
> > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // Initialize new GDT table and/or IDT table, if any
> > > + //
> > > + AsmReadIdtr (&Idtr);
> > > + AsmReadGdtr (&Gdtr);
> > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > + }
> > > +
> > > + //
> > > + // Fixup current task descriptor. Task-state segment for current task will
> > > + // be filled by processor during task switching.
> > > + //
> > > + TssDesc = StackSwitchData->TssDesc;
> > > + Tss = StackSwitchData->Tss;
> > > +
> > > + TssBase = (UINTN)Tss;
> > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > + TssDesc->Bits.P = 1;
> > > + TssDesc->Bits.LimitHigh = 0;
> > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > +
> > > + //
> > > + // Fixup exception task descriptor and task-state segment
> > > + //
> > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > + StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
> > > + IdtTable = StackSwitchData->IdtTable;
> > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > + //
> > > + // Fixup IST
> > > + //
> > > + Tss->IST[Index] = StackTop;
> > > + StackTop -= StackSwitchData->StackSize;
> > > +
> > > + //
> > > + // Set the IST field to enable corresponding IST
> > > + //
> > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > (UINT8)(Index + 1);
> > > + }
> > > +
> > > + //
> > > + // Publish GDT
> > > + //
> > > + AsmWriteGdtr (&Gdtr);
> > > +
> > > + //
> > > + // Load current task
> > > + //
> > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > +
> > > + //
> > > + // Publish IDT
> > > + //
> > > + AsmWriteIdtr (&Idtr);
> > > +
> > > + return EFI_SUCCESS;
> > > +}
> > > +
> > > /**
> > > Display CPU information.
> > >
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > index 906480134a..c88be46286 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > @@ -43,4 +43,7 @@ typedef struct {
> > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > } RESERVED_VECTORS_DATA;
> > >
> > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > +
> > > #endif
> > > --
> > > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 6:05 ` Wang, Jian J
@ 2017-11-23 6:16 ` Yao, Jiewen
2017-11-23 6:43 ` Wang, Jian J
0 siblings, 1 reply; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 6:16 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
Cc: Zeng, Star, Dong, Eric, Kinney, Michael D
Here is my thought for 1)
1.1) We must provide the InitializeCpuExceptionStackSwitchHandlers() implementation in Pei instance and Smm instance.
The basic requirement is a library instance must provide symbol for functions declared in header file.
It is ok to return unsupported. But we MUST provide the symbol.
1.2) For SMM, I think our ultimate goal is to remove SMM specific stack guard, and use the common one. Duplicating code is completely unnecessary, and it is easy to introduce bug. And unfortunately, we already have bug in existing SMM exception handler. -- That is a good reason to remove duplication.
Again, it is not necessary to do it in this patch. I am totally OK to do it in another patch.
1.3) For PEI, I do not think we can use current way to allocate stack in data section, because it might be readonly in pre-mem phase. We must use some other way.
1.4) I believe this patch has a hidden assumption is that: InitializeCpuExceptionHandlers() won't be called by multiple APs.
If 2 or more APs call the it at same time, it might be broken because you use mNewStack for all the callers....
Is that right?
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wang, Jian J
> Sent: Thursday, November 23, 2017 2:06 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
>
>
> > -----Original Message-----
> > From: Yao, Jiewen
> > Sent: Thursday, November 23, 2017 1:50 PM
> > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Kinney, Michael D <michael.d.kinney@intel.com>
> > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch support
> >
> > Some thought:
> >
> > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented in
> > DxeException.c.
> > What about Pei/Smm instance?
> >
> > I think it is OK to not implement it at this moment. But we need make sure no
> > architecture issue if we want to enable it some time later.
> >
> Like what we discussed before, this series of patch is for Stack Guard feature
> which
> is only available for DXE (because Stack Guard needs paging to work). Stack
> switch
> is enabled for the sake of Stack Guard feature. So I think it's enough to
> implement
> it in DxeException.c. In addition, SMM has its own implementation of stack guard
> and stack switch. It's not necessary to do it again.
>
> I agree with you that we should merge those common code but I think we should
> do
> it in a separate patch series since it's not Stack Guard relevant. And I've removed
> all architecture issues I can think of. Current stack switch initialization should work
> for both PEI and SMM as well.
>
> > 2) #define IA32_GDT_TYPE_TSS 0x9
> > This is generic, can we move to BaseLib.h?
> >
> >
> > Thank you
> > Yao Jiewen
> >
> >
> > > -----Original Message-----
> > > From: Wang, Jian J
> > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > To: edk2-devel@lists.01.org
> > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>; Yao,
> > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > <michael.d.kinney@intel.com>
> > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch
> > > support
> > >
> > > > v2:
> > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to
> setup
> > > stack
> > > > switch. This can avoid allocating memory for it in this library.
> > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > phase of DXE core.
> > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > support
> > > > memory allocation because those memory can passed in by
> parameter
> > > now.
> > > > e. Remove the nasm macro to define exception handler one by one
> and
> > > add a
> > > > function to return the start address of each handler.
> > >
> > > If Stack Guard is enabled and there's really a stack overflow happened during
> > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > usage, the exception handler, which shares the stack with normal UEFI driver,
> > > cannot be executed and cannot dump the processor information.
> > >
> > > Without those information, it's very difficult for the BIOS developers locate
> > > the root cause of stack overflow. And without a workable stack, the
> developer
> > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > >
> > > In order to make sure the exception handler to execute normally after stack
> > > overflow. We need separate stacks for exception handlers in case of unusable
> > > stack.
> > >
> > > IA processor allows to switch to a new stack during handling interrupt and
> > > exception. But X64 and IA32 provides different ways to make it. X64 provides
> > > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > > new stack for its handler. IA32 doesn't have IST mechanism and can only use
> > > task gate to do it since task switch allows to load a new stack through its
> > > task-state segment (TSS).
> > >
> > > Cc: Star Zeng <star.zeng@intel.com>
> > > Cc: Eric Dong <eric.dong@intel.com>
> > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > ---
> > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > +++++++++++++++++++++
> > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > create mode 100644
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > >
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > index 740a58828b..30334105d2 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > @@ -48,6 +48,32 @@
> > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c,
> > 0x83 }
> > > \
> > > }
> > >
> > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > +
> > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > +
> > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > +
> > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > CPU_TSS_SIZE)
> > > +
> > > +#define IA32_GDT_TYPE_TSS 0x9
> > > +#define IA32_GDT_ALIGNMENT 8
> > > +
> > > +typedef struct {
> > > + UINTN StackTop;
> > > + UINTN StackSize;
> > > + UINT8 *Exceptions;
> > > + UINTN ExceptionNumber;
> > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > + UINTN GdtSize;
> > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > +
> > > //
> > > // Record exception handler information
> > > //
> > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > );
> > >
> > > +/**
> > > + Setup separate stack for specific exceptions.
> > > +
> > > + @param[in] IdtTable IDT table base.
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +ArchSetupExcpetionStack (
> > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > + );
> > > +
> > > +/**
> > > + Return address map of exception handler template so that C code can
> > > generate
> > > + exception tables. The template is only for exceptions using task gate
> instead
> > > + of interrupt gate.
> > > +
> > > + @param AddressMap Pointer to a buffer where the address map is
> > > returned.
> > > +**/
> > > +VOID
> > > +EFIAPI
> > > +AsmGetTssTemplateMap (
> > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > + );
> > > +
> > > #endif
> > >
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > index f4a8d01c80..58e55a8a2e 100644
> > > ---
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > @@ -47,6 +48,11 @@
> > > PeiDxeSmmCpuException.c
> > > DxeException.c
> > >
> > > +[Pcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > +
> > > [Packages]
> > > MdePkg/MdePkg.dec
> > > MdeModulePkg/MdeModulePkg.dec
> > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > index 31febec976..c0b2c615aa 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > @@ -25,6 +25,10 @@ UINTN
> mEnabledInterruptNum =
> > > 0;
> > >
> > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > >
> > > +UINT8
> > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > +
> CPU_KNOWN_GOOD_STACK_SIZE]
> > > = {0};
> > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > +
> > > /**
> > > Common exception handler.
> > >
> > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > )
> > > {
> > > + EFI_STATUS Status;
> > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > + IA32_DESCRIPTOR Idtr;
> > > + IA32_DESCRIPTOR Gdtr;
> > > +
> > > mExceptionHandlerData.ReservedVectors =
> > > mReservedVectorsData;
> > > mExceptionHandlerData.ExternalInterruptHandler =
> > > mExternalInterruptHandlerTable;
> > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > &mExceptionHandlerData);
> > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > &mExceptionHandlerData);
> > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > + AsmReadIdtr (&Idtr);
> > > + AsmReadGdtr (&Gdtr);
> > > +
> > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > + StackSwitchData.ExceptionNumber =
> > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> *)mNewGdt;
> > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > Gdtr.Limit + 1);
> > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > Gdtr.Limit + 1 +
> > > +
> > > CPU_TSS_DESC_SIZE);
> > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > + &StackSwitchData
> > > + );
> > > + }
> > > + return Status;
> > > }
> > >
> > > /**
> > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > {
> > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> InterruptHandler,
> > > &mExceptionHandlerData);
> > > }
> > > +
> > > +/**
> > > + Setup separate stack for given exceptions. This is required by
> > > + PcdCpuStackGuard feature.
> > > +
> > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > +
> > > + @param[in] StackSwitchData Pointer to data required for setuping
> up
> > > + stack switch.
> > > +
> > > + @retval EFI_SUCCESS The exceptions have been
> successfully
> > > + initialized.
> > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > content.
> > > +
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +InitializeCpuExceptionStackSwitchHandlers (
> > > + IN VOID *StackSwitchData OPTIONAL
> > > + )
> > > +{
> > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > +}
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > index f2c39eb193..0aaf794795 100644
> > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > SystemContext.SystemContextIa32->ExceptionData =
> > > ReservedVectors[ExceptionType].ExceptionData;
> > > }
> > >
> > > +/**
> > > + Setup separate stack for given exceptions.
> > > +
> > > + @param[in] StackSwitchData Pointer to data required for
> setuping
> > > up
> > > + stack switch.
> > > + @retval EFI_SUCCESS The exceptions have been
> successfully
> > > + initialized.
> > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > content.
> > > +
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +ArchSetupExcpetionStack (
> > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > + )
> > > +{
> > > + IA32_DESCRIPTOR Gdtr;
> > > + IA32_DESCRIPTOR Idtr;
> > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > + UINTN StackTop;
> > > + UINTN Index;
> > > + UINTN Vector;
> > > + UINTN TssBase;
> > > + UINTN GdtSize;
> > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > +
> > > + if (StackSwitchData == NULL ||
> > > + StackSwitchData->StackTop == 0 ||
> > > + StackSwitchData->StackSize == 0 ||
> > > + StackSwitchData->Exceptions == NULL ||
> > > + StackSwitchData->ExceptionNumber == 0 ||
> > > + StackSwitchData->GdtTable == NULL ||
> > > + StackSwitchData->IdtTable == NULL ||
> > > + StackSwitchData->TssDesc == NULL ||
> > > + StackSwitchData->Tss == NULL) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // The caller is responsible for that the GDT table, no matter the existing
> > > + // one or newly allocated, has enough space to hold descriptors for
> > exception
> > > + // task-state segments.
> > > + //
> > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=
> 0)
> > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > >GdtTable))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > + ((UINTN)(StackSwitchData->GdtTable) +
> StackSwitchData->GdtSize))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > + (UINTN)(StackSwitchData->GdtTable) +
> > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > + (StackSwitchData->ExceptionNumber + 1);
> > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // Initialize new GDT table and/or IDT table, if any
> > > + //
> > > + AsmReadIdtr (&Idtr);
> > > + AsmReadGdtr (&Gdtr);
> > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> 1);
> > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > + }
> > > +
> > > + //
> > > + // Fixup current task descriptor. Task-state segment for current task will
> > > + // be filled by processor during task switching.
> > > + //
> > > + TssDesc = StackSwitchData->TssDesc;
> > > + Tss = StackSwitchData->Tss;
> > > +
> > > + TssBase = (UINTN)Tss;
> > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > + TssDesc->Bits.P = 1;
> > > + TssDesc->Bits.LimitHigh = 0;
> > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > +
> > > + //
> > > + // Fixup exception task descriptor and task-state segment
> > > + //
> > > + AsmGetTssTemplateMap (&TemplateMap);
> > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> CPU_STACK_ALIGNMENT);
> > > + IdtTable = StackSwitchData->IdtTable;
> > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > + TssDesc += 1;
> > > + Tss += 1;
> > > +
> > > + //
> > > + // Fixup TSS descriptor
> > > + //
> > > + TssBase = (UINTN)Tss;
> > > +
> > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > + TssDesc->Bits.P = 1;
> > > + TssDesc->Bits.LimitHigh = 0;
> > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > +
> > > + //
> > > + // Fixup TSS
> > > + //
> > > + Vector = StackSwitchData->Exceptions[Index];
> > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > + + Vector *
> > > TemplateMap.ExceptionStubHeaderSize);
> > > + Tss->EFLAGS = 0x2;
> > > + Tss->ESP = StackTop;
> > > + Tss->CR3 = AsmReadCr3 ();
> > > + Tss->ES = AsmReadEs ();
> > > + Tss->CS = AsmReadCs ();
> > > + Tss->SS = AsmReadSs ();
> > > + Tss->DS = AsmReadDs ();
> > > + Tss->FS = AsmReadFs ();
> > > + Tss->GS = AsmReadGs ();
> > > +
> > > + StackTop -= StackSwitchData->StackSize;
> > > +
> > > + //
> > > + // Update IDT to use Task Gate for given exception
> > > + //
> > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> Gdtr.Base);
> > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > + }
> > > +
> > > + //
> > > + // Publish GDT
> > > + //
> > > + AsmWriteGdtr (&Gdtr);
> > > +
> > > + //
> > > + // Load current task
> > > + //
> > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > +
> > > + //
> > > + // Publish IDT
> > > + //
> > > + AsmWriteIdtr (&Idtr);
> > > +
> > > + return EFI_SUCCESS;
> > > +}
> > > +
> > > /**
> > > Display processor context.
> > >
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > index a8d3556a80..d9ded5977f 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > @@ -41,4 +41,12 @@ typedef struct {
> > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > } RESERVED_VECTORS_DATA;
> > >
> > > +#define CPU_TSS_DESC_SIZE \
> > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > +
> > > +#define CPU_TSS_SIZE \
> > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > +
> > > #endif
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > m
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > m
> > > new file mode 100644
> > > index 0000000000..62bcedea1a
> > > --- /dev/null
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > m
> > > @@ -0,0 +1,398 @@
> > > +;------------------------------------------------------------------------------ ;
> > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > +; This program and the accompanying materials
> > > +; are licensed and made available under the terms and conditions of the BSD
> > > License
> > > +; which accompanies this distribution. The full text of the license may be
> > found
> > > at
> > > +; http://opensource.org/licenses/bsd-license.php.
> > > +;
> > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > BASIS,
> > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > EXPRESS
> > > OR IMPLIED.
> > > +;
> > > +; Module Name:
> > > +;
> > > +; ExceptionTssEntryAsm.Asm
> > > +;
> > > +; Abstract:
> > > +;
> > > +; IA32 CPU Exception Handler with Separate Stack
> > > +;
> > > +; Notes:
> > > +;
> > > +;------------------------------------------------------------------------------
> > > +
> > > +;
> > > +; IA32 TSS Memory Layout Description
> > > +;
> > > +struc IA32_TSS
> > > + resw 1
> > > + resw 1
> > > + .ESP0: resd 1
> > > + .SS0: resw 1
> > > + resw 1
> > > + .ESP1: resd 1
> > > + .SS1: resw 1
> > > + resw 1
> > > + .ESP2: resd 1
> > > + .SS2: resw 1
> > > + resw 1
> > > + ._CR3: resd 1
> > > + .EIP: resd 1
> > > + .EFLAGS: resd 1
> > > + ._EAX: resd 1
> > > + ._ECX: resd 1
> > > + ._EDX: resd 1
> > > + ._EBX: resd 1
> > > + ._ESP: resd 1
> > > + ._EBP: resd 1
> > > + ._ESI: resd 1
> > > + ._EDI: resd 1
> > > + ._ES: resw 1
> > > + resw 1
> > > + ._CS: resw 1
> > > + resw 1
> > > + ._SS: resw 1
> > > + resw 1
> > > + ._DS: resw 1
> > > + resw 1
> > > + ._FS: resw 1
> > > + resw 1
> > > + ._GS: resw 1
> > > + resw 1
> > > + .LDT: resw 1
> > > + resw 1
> > > + resw 1
> > > + resw 1
> > > +endstruc
> > > +
> > > +;
> > > +; CommonExceptionHandler()
> > > +;
> > > +extern ASM_PFX(CommonExceptionHandler)
> > > +
> > > +SECTION .data
> > > +
> > > +SECTION .text
> > > +
> > > +ALIGN 8
> > > +
> > > +;
> > > +; Exception handler stub table
> > > +;
> > > +AsmExceptionEntryBegin:
> > > +%assign Vector 0
> > > +%rep 32
> > > +
> > > +DoIret%[Vector]:
> > > + iretd
> > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > + db 0x6a ; push #VectorNum
> > > + db %[Vector]
> > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > + call eax
> > > + mov esp, eax ; Restore stack top
> > > + jmp DoIret%[Vector]
> > > +
> > > +%assign Vector Vector+1
> > > +%endrep
> > > +AsmExceptionEntryEnd:
> > > +
> > > +;
> > > +; Common part of exception handler
> > > +;
> > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > + ;
> > > + ; Stack:
> > > + ; +---------------------+ <-- EBP - 8
> > > + ; + TSS Base +
> > > + ; +---------------------+ <-- EBP - 4
> > > + ; + CPUID.EDX +
> > > + ; +---------------------+ <-- EBP
> > > + ; + EIP +
> > > + ; +---------------------+ <-- EBP + 4
> > > + ; + Vector Number +
> > > + ; +---------------------+ <-- EBP + 8
> > > + ; + Error Code +
> > > + ; +---------------------+
> > > + ;
> > > +
> > > + mov ebp, esp ; Stack frame
> > > +
> > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > + mov eax, 1
> > > + cpuid
> > > + push edx
> > > +
> > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > +; current TSS base
> > > + sub esp, 8
> > > + sgdt [esp + 2]
> > > + mov eax, [esp + 4] ; GDT base
> > > + add esp, 8
> > > +
> > > + xor ebx, ebx
> > > + str bx ; Current TR
> > > +
> > > + mov ecx, [eax + ebx + 2]
> > > + shl ecx, 8
> > > + mov cl, [eax + ebx + 7]
> > > + ror ecx, 8 ; ecx = Current TSS base
> > > + push ecx ; keep it in stack for later use
> > > +
> > > + movzx ebx, word [ecx] ; Previous Task Link
> > > + mov ecx, [eax + ebx + 2]
> > > + shl ecx, 8
> > > + mov cl, [eax + ebx + 7]
> > > + ror ecx, 8 ; ecx = Previous TSS base
> > > +
> > > +;
> > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > EFI_SYSTEM_CONTEXT_IA32
> > > +; is 16-byte aligned
> > > +;
> > > + and esp, 0xfffffff0
> > > + sub esp, 12
> > > +
> > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > + push dword [ecx + IA32_TSS._EAX]
> > > + push dword [ecx + IA32_TSS._ECX]
> > > + push dword [ecx + IA32_TSS._EDX]
> > > + push dword [ecx + IA32_TSS._EBX]
> > > + push dword [ecx + IA32_TSS._ESP]
> > > + push dword [ecx + IA32_TSS._EBP]
> > > + push dword [ecx + IA32_TSS._ESI]
> > > + push dword [ecx + IA32_TSS._EDI]
> > > +
> > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > + push eax
> > > +
> > > +;; UINT32 Eip;
> > > + push dword [ecx + IA32_TSS.EIP]
> > > +
> > > +;; UINT32 Gdtr[2], Idtr[2];
> > > + sub esp, 8
> > > + sidt [esp]
> > > + mov eax, [esp + 2]
> > > + xchg eax, [esp]
> > > + and eax, 0xFFFF
> > > + mov [esp+4], eax
> > > +
> > > + sub esp, 8
> > > + sgdt [esp]
> > > + mov eax, [esp + 2]
> > > + xchg eax, [esp]
> > > + and eax, 0xFFFF
> > > + mov [esp+4], eax
> > > +
> > > +;; UINT32 Ldtr, Tr;
> > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > + push eax
> > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > + push eax
> > > +
> > > +;; UINT32 EFlags;
> > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > +
> > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > + mov eax, cr4
> > > + push eax ; push cr4 firstly
> > > +
> > > + mov edx, [ebp - 4] ; cpuid.edx
> > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > + jz .1
> > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > +.1:
> > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > + jz .2
> > > + or eax, BIT3 ; Set CR4.DE
> > > +.2:
> > > + mov cr4, eax
> > > +
> > > + mov eax, cr3
> > > + push eax
> > > + mov eax, cr2
> > > + push eax
> > > + xor eax, eax
> > > + push eax
> > > + mov eax, cr0
> > > + push eax
> > > +
> > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > + mov eax, dr7
> > > + push eax
> > > + mov eax, dr6
> > > + push eax
> > > + mov eax, dr3
> > > + push eax
> > > + mov eax, dr2
> > > + push eax
> > > + mov eax, dr1
> > > + push eax
> > > + mov eax, dr0
> > > + push eax
> > > +
> > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > +;; when executing fxsave/fxrstor instruction
> > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > + ; edx still contains result from CPUID above
> > > + jz .3
> > > + clts
> > > + sub esp, 512
> > > + mov edi, esp
> > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > +.3:
> > > +
> > > +;; UINT32 ExceptionData;
> > > + push dword [ebp + 8]
> > > +
> > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is
> > clear
> > > + cld
> > > +
> > > +;; call into exception handler
> > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > +
> > > +;; Prepare parameter and call
> > > + mov edx, esp
> > > + push edx ; EFI_SYSTEM_CONTEXT
> > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > > +
> > > + ;
> > > + ; Call External Exception Handler
> > > + ;
> > > + call eax
> > > + add esp, 8 ; Restore stack before calling
> > > + mov ecx, esi ; Restore TSS base
> > > +
> > > +;; UINT32 ExceptionData;
> > > + add esp, 4
> > > +
> > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > + mov edx, [ebp - 4] ; cpuid.edx
> > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > + jz .4
> > > + mov esi, esp
> > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > +.4:
> > > + add esp, 512
> > > +
> > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > +;; Skip restoration of DRx registers to support debuggers
> > > +;; that set breakpoints in interrupt/exception context
> > > + add esp, 4 * 6
> > > +
> > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > + pop eax
> > > + mov cr0, eax
> > > + add esp, 4 ; not for Cr1
> > > + pop eax
> > > + mov cr2, eax
> > > + pop eax
> > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > + pop eax
> > > + mov cr4, eax
> > > +
> > > +;; UINT32 EFlags;
> > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > + btr ebx, 9 ; Do 'cli'
> > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > +
> > > +;; UINT32 Ldtr, Tr;
> > > +;; UINT32 Gdtr[2], Idtr[2];
> > > +;; Best not let anyone mess with these particular registers...
> > > + add esp, 24
> > > +
> > > +;; UINT32 Eip;
> > > + pop dword [ecx + IA32_TSS.EIP]
> > > +
> > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > +;; NOTE - modified segment registers could hang the debugger... We
> > > +;; could attempt to insulate ourselves against this possibility,
> > > +;; but that poses risks as well.
> > > +;;
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > + pop eax
> > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > +
> > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > + pop dword [ecx + IA32_TSS._EDI]
> > > + pop dword [ecx + IA32_TSS._ESI]
> > > + add esp, 4 ; not for ebp
> > > + add esp, 4 ; not for esp
> > > + pop dword [ecx + IA32_TSS._EBX]
> > > + pop dword [ecx + IA32_TSS._EDX]
> > > + pop dword [ecx + IA32_TSS._ECX]
> > > + pop dword [ecx + IA32_TSS._EAX]
> > > +
> > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > +; where the exception is triggered.
> > > +
> > > +;; Create return context for iretd in stub function
> > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> pointer
> > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > + mov [eax - 0xc], ebx ; create EIP in old
> stack
> > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > + mov [eax - 0x8], ebx ; create CS in old stack
> > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > + bts ebx, 8
> > > + mov [eax - 0x4], ebx ; create eflags in old
> stack
> > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old
> TSS
> > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> pointer
> > > + sub eax, 0xc ; minus 12 byte
> > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> pointer
> > > +
> > > +;; Replace the EIP of interrupted task with stub function
> > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > +
> > > + mov ecx, [ebp - 8] ; Get current TSS base
> > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack
> top
> > > + mov esp, ebp
> > > +
> > > + ret
> > > +
> > > +global ASM_PFX(SingleStepStubFunction)
> > > +ASM_PFX(SingleStepStubFunction):
> > > +;
> > > +; we need clean TS bit in CR0 to execute
> > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > +;
> > > + clts
> > > + iretd
> > > +
> > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > +ASM_PFX(AsmGetTssTemplateMap):
> > > + push ebp ; C prolog
> > > + mov ebp, esp
> > > + pushad
> > > +
> > > + mov ebx, dword [ebp + 0x8]
> > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> AsmExceptionEntryBegin)
> > > / 32
> > > + mov dword [ebx + 0x8], 0
> > > +
> > > + popad
> > > + pop ebp
> > > + ret
> > > +
> > > diff --git
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > index 75443288a9..4c0d435136 100644
> > > ---
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > +++
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > > index d70a99c100..e5c03c16c9 100644
> > > ---
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > nf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > diff --git
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > index 634ffcb21d..56b875b7c8 100644
> > > ---
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > +++
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > @@ -30,6 +30,7 @@
> > > [Sources.Ia32]
> > > Ia32/ExceptionHandlerAsm.asm
> > > Ia32/ExceptionHandlerAsm.nasm
> > > + Ia32/ExceptionTssEntryAsm.nasm
> > > Ia32/ExceptionHandlerAsm.S
> > > Ia32/ArchExceptionHandler.c
> > > Ia32/ArchInterruptDefs.h
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > index 65f0cff680..214aafcc13 100644
> > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > SystemContext.SystemContextX64->ExceptionData =
> > > ReservedVectors[ExceptionType].ExceptionData;
> > > }
> > >
> > > +/**
> > > + Setup separate stack for given exceptions.
> > > +
> > > + @param[in] StackSwitchData Pointer to data required for setuping
> up
> > > + stack switch.
> > > +
> > > + @retval EFI_SUCCESS The exceptions have been
> successfully
> > > + initialized.
> > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > content.
> > > +
> > > +**/
> > > +EFI_STATUS
> > > +EFIAPI
> > > +ArchSetupExcpetionStack (
> > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > + )
> > > +{
> > > + IA32_DESCRIPTOR Gdtr;
> > > + IA32_DESCRIPTOR Idtr;
> > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > + UINTN StackTop;
> > > + UINTN Index;
> > > + UINTN TssBase;
> > > + UINTN GdtSize;
> > > +
> > > + if (StackSwitchData == NULL ||
> > > + StackSwitchData->StackTop == 0 ||
> > > + StackSwitchData->StackSize == 0 ||
> > > + StackSwitchData->Exceptions == NULL ||
> > > + StackSwitchData->ExceptionNumber == 0 ||
> > > + StackSwitchData->GdtTable == NULL ||
> > > + StackSwitchData->IdtTable == NULL ||
> > > + StackSwitchData->TssDesc == NULL ||
> > > + StackSwitchData->Tss == NULL) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // The caller is responsible for that the GDT table, no matter the existing
> > > + // one or newly allocated, has enough space to hold descriptors for
> > exception
> > > + // task-state segments.
> > > + //
> > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) !=
> 0)
> > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > >GdtTable))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > + ((UINTN)(StackSwitchData->GdtTable) +
> StackSwitchData->GdtSize))
> > > {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > + (UINTN)(StackSwitchData->GdtTable) +
> > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > +
> > > + //
> > > + // Initialize new GDT table and/or IDT table, if any
> > > + //
> > > + AsmReadIdtr (&Idtr);
> > > + AsmReadGdtr (&Gdtr);
> > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> 1);
> > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > + }
> > > +
> > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > + }
> > > +
> > > + //
> > > + // Fixup current task descriptor. Task-state segment for current task will
> > > + // be filled by processor during task switching.
> > > + //
> > > + TssDesc = StackSwitchData->TssDesc;
> > > + Tss = StackSwitchData->Tss;
> > > +
> > > + TssBase = (UINTN)Tss;
> > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > + TssDesc->Bits.P = 1;
> > > + TssDesc->Bits.LimitHigh = 0;
> > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > +
> > > + //
> > > + // Fixup exception task descriptor and task-state segment
> > > + //
> > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> CPU_STACK_ALIGNMENT);
> > > + IdtTable = StackSwitchData->IdtTable;
> > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > + //
> > > + // Fixup IST
> > > + //
> > > + Tss->IST[Index] = StackTop;
> > > + StackTop -= StackSwitchData->StackSize;
> > > +
> > > + //
> > > + // Set the IST field to enable corresponding IST
> > > + //
> > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > (UINT8)(Index + 1);
> > > + }
> > > +
> > > + //
> > > + // Publish GDT
> > > + //
> > > + AsmWriteGdtr (&Gdtr);
> > > +
> > > + //
> > > + // Load current task
> > > + //
> > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > +
> > > + //
> > > + // Publish IDT
> > > + //
> > > + AsmWriteIdtr (&Idtr);
> > > +
> > > + return EFI_SUCCESS;
> > > +}
> > > +
> > > /**
> > > Display CPU information.
> > >
> > > diff --git
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > index 906480134a..c88be46286 100644
> > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > @@ -43,4 +43,7 @@ typedef struct {
> > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > } RESERVED_VECTORS_DATA;
> > >
> > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > +
> > > #endif
> > > --
> > > 2.14.1.windows.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 6:09 ` Wang, Jian J
@ 2017-11-23 6:25 ` Yao, Jiewen
2017-11-23 7:54 ` Wang, Jian J
0 siblings, 1 reply; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-23 6:25 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
I am ok to keep FALSE by default. But I still suggest we test existing UEFI OS behavior.
Please help me understand below condition, if we do not change a platform specific CPU driver:
1) If PcdCpuStackGuard is FALSE, and CPU driver is still consuming existing API in ExceptionLib. Is there any impact?
2) If PcdCpuStackGuard is TRUE, and CPU driver is still consuming existing API in ExceptionLib. Is there any impact?
3) If PcdCpuStackGuard is FALSE, and CPU driver is not consuming existing API in ExceptionLib. Is there any impact?
4) If PcdCpuStackGuard is TRUE, and CPU driver is not consuming existing API in ExceptionLib. Is there any impact?
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wang, Jian J
> Sent: Thursday, November 23, 2017 2:09 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> If PcdCpuStackGuard is not enabled, there's no impact. If it's enabled, the only
> issue is that the exception dump cannot be done but no other impact. From this
> point of view, maybe PcdCpuStackGuard should be FALSE by default.
>
> > -----Original Message-----
> > From: Yao, Jiewen
> > Sent: Thursday, November 23, 2017 1:59 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J
> <jian.j.wang@intel.com>;
> > edk2-devel@lists.01.org
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> > <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch support
> >
> > One more question:
> > I notice not all platforms are using the CpuDxe in UefiCpuPkg.
> > If so, is there any impact to the platform whose CPU driver does not have such
> > InitializeCpuExceptionStackSwitchHandlers() call?
> > Have you tested that condition?
> >
> > Thank you
> > Yao Jiewen
> >
> > > -----Original Message-----
> > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Yao,
> > > Jiewen
> > > Sent: Thursday, November 23, 2017 1:50 PM
> > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> > > <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > > Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> > > stack switch support
> > >
> > > Some thought:
> > >
> > > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented in
> > > DxeException.c.
> > > What about Pei/Smm instance?
> > >
> > > I think it is OK to not implement it at this moment. But we need make sure no
> > > architecture issue if we want to enable it some time later.
> > >
> > > 2) #define IA32_GDT_TYPE_TSS 0x9
> > > This is generic, can we move to BaseLib.h?
> > >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > >
> > > > -----Original Message-----
> > > > From: Wang, Jian J
> > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > To: edk2-devel@lists.01.org
> > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Yao,
> > > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > > <michael.d.kinney@intel.com>
> > > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch
> > > > support
> > > >
> > > > > v2:
> > > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to
> setup
> > > > stack
> > > > > switch. This can avoid allocating memory for it in this library.
> > > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > > phase of DXE core.
> > > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > > support
> > > > > memory allocation because those memory can passed in by
> > > parameter
> > > > now.
> > > > > e. Remove the nasm macro to define exception handler one by one
> and
> > > > add a
> > > > > function to return the start address of each handler.
> > > >
> > > > If Stack Guard is enabled and there's really a stack overflow happened
> during
> > > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > > usage, the exception handler, which shares the stack with normal UEFI
> driver,
> > > > cannot be executed and cannot dump the processor information.
> > > >
> > > > Without those information, it's very difficult for the BIOS developers locate
> > > > the root cause of stack overflow. And without a workable stack, the
> > developer
> > > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > > >
> > > > In order to make sure the exception handler to execute normally after stack
> > > > overflow. We need separate stacks for exception handlers in case of
> > unusable
> > > > stack.
> > > >
> > > > IA processor allows to switch to a new stack during handling interrupt and
> > > > exception. But X64 and IA32 provides different ways to make it. X64
> provides
> > > > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > > > new stack for its handler. IA32 doesn't have IST mechanism and can only use
> > > > task gate to do it since task switch allows to load a new stack through its
> > > > task-state segment (TSS).
> > > >
> > > > Cc: Star Zeng <star.zeng@intel.com>
> > > > Cc: Eric Dong <eric.dong@intel.com>
> > > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > > ---
> > > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > > +++++++++++++++++++++
> > > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > > create mode 100644
> > > >
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > index 740a58828b..30334105d2 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > @@ -48,6 +48,32 @@
> > > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9,
> 0x2c,
> > > 0x83 }
> > > > \
> > > > }
> > > >
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > > +
> > > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > > CPU_TSS_SIZE)
> > > > +
> > > > +#define IA32_GDT_TYPE_TSS 0x9
> > > > +#define IA32_GDT_ALIGNMENT 8
> > > > +
> > > > +typedef struct {
> > > > + UINTN StackTop;
> > > > + UINTN StackSize;
> > > > + UINT8 *Exceptions;
> > > > + UINTN ExceptionNumber;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > + UINTN GdtSize;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > +
> > > > //
> > > > // Record exception handler information
> > > > //
> > > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > > );
> > > >
> > > > +/**
> > > > + Setup separate stack for specific exceptions.
> > > > +
> > > > + @param[in] IdtTable IDT table base.
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + );
> > > > +
> > > > +/**
> > > > + Return address map of exception handler template so that C code can
> > > > generate
> > > > + exception tables. The template is only for exceptions using task gate
> > > instead
> > > > + of interrupt gate.
> > > > +
> > > > + @param AddressMap Pointer to a buffer where the address map is
> > > > returned.
> > > > +**/
> > > > +VOID
> > > > +EFIAPI
> > > > +AsmGetTssTemplateMap (
> > > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > > + );
> > > > +
> > > > #endif
> > > >
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > index f4a8d01c80..58e55a8a2e 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > @@ -47,6 +48,11 @@
> > > > PeiDxeSmmCpuException.c
> > > > DxeException.c
> > > >
> > > > +[Pcd]
> > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > +
> > > > [Packages]
> > > > MdePkg/MdePkg.dec
> > > > MdeModulePkg/MdeModulePkg.dec
> > > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > index 31febec976..c0b2c615aa 100644
> > > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > @@ -25,6 +25,10 @@ UINTN
> mEnabledInterruptNum
> > > =
> > > > 0;
> > > >
> > > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > > >
> > > > +UINT8
> > > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > > +
> > > CPU_KNOWN_GOOD_STACK_SIZE]
> > > > = {0};
> > > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > > +
> > > > /**
> > > > Common exception handler.
> > > >
> > > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > > )
> > > > {
> > > > + EFI_STATUS Status;
> > > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > +
> > > > mExceptionHandlerData.ReservedVectors =
> > > > mReservedVectorsData;
> > > > mExceptionHandlerData.ExternalInterruptHandler =
> > > > mExternalInterruptHandlerTable;
> > > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > +
> > > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > > + StackSwitchData.ExceptionNumber =
> > > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> *)mNewGdt;
> > > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > > Gdtr.Limit + 1);
> > > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > > Gdtr.Limit + 1 +
> > > > +
> > > > CPU_TSS_DESC_SIZE);
> > > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > > + &StackSwitchData
> > > > + );
> > > > + }
> > > > + return Status;
> > > > }
> > > >
> > > > /**
> > > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > > {
> > > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > > InterruptHandler,
> > > > &mExceptionHandlerData);
> > > > }
> > > > +
> > > > +/**
> > > > + Setup separate stack for given exceptions. This is required by
> > > > + PcdCpuStackGuard feature.
> > > > +
> > > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for
> setuping up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +InitializeCpuExceptionStackSwitchHandlers (
> > > > + IN VOID *StackSwitchData OPTIONAL
> > > > + )
> > > > +{
> > > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > > +}
> > > > diff --git
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > index f2c39eb193..0aaf794795 100644
> > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > +++
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextIa32->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for
> setuping
> > > > up
> > > > + stack switch.
> > > > + @retval EFI_SUCCESS The exceptions have been
> successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN Vector;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc <
> > > (UINTN)(StackSwitchData->GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > > + (StackSwitchData->ExceptionNumber + 1);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit
> +
> > > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + AsmGetTssTemplateMap (&TemplateMap);
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + TssDesc += 1;
> > > > + Tss += 1;
> > > > +
> > > > + //
> > > > + // Fixup TSS descriptor
> > > > + //
> > > > + TssBase = (UINTN)Tss;
> > > > +
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup TSS
> > > > + //
> > > > + Vector = StackSwitchData->Exceptions[Index];
> > > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > > + + Vector *
> > > > TemplateMap.ExceptionStubHeaderSize);
> > > > + Tss->EFLAGS = 0x2;
> > > > + Tss->ESP = StackTop;
> > > > + Tss->CR3 = AsmReadCr3 ();
> > > > + Tss->ES = AsmReadEs ();
> > > > + Tss->CS = AsmReadCs ();
> > > > + Tss->SS = AsmReadSs ();
> > > > + Tss->DS = AsmReadDs ();
> > > > + Tss->FS = AsmReadFs ();
> > > > + Tss->GS = AsmReadGs ();
> > > > +
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Update IDT to use Task Gate for given exception
> > > > + //
> > > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> Gdtr.Base);
> > > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display processor context.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > index a8d3556a80..d9ded5977f 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > @@ -41,4 +41,12 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE \
> > > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > +#define CPU_TSS_SIZE \
> > > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > #endif
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > new file mode 100644
> > > > index 0000000000..62bcedea1a
> > > > --- /dev/null
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > @@ -0,0 +1,398 @@
> > > > +;------------------------------------------------------------------------------ ;
> > > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > > +; This program and the accompanying materials
> > > > +; are licensed and made available under the terms and conditions of the
> BSD
> > > > License
> > > > +; which accompanies this distribution. The full text of the license may be
> > > found
> > > > at
> > > > +; http://opensource.org/licenses/bsd-license.php.
> > > > +;
> > > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > > BASIS,
> > > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > EXPRESS
> > > > OR IMPLIED.
> > > > +;
> > > > +; Module Name:
> > > > +;
> > > > +; ExceptionTssEntryAsm.Asm
> > > > +;
> > > > +; Abstract:
> > > > +;
> > > > +; IA32 CPU Exception Handler with Separate Stack
> > > > +;
> > > > +; Notes:
> > > > +;
> > > > +;------------------------------------------------------------------------------
> > > > +
> > > > +;
> > > > +; IA32 TSS Memory Layout Description
> > > > +;
> > > > +struc IA32_TSS
> > > > + resw 1
> > > > + resw 1
> > > > + .ESP0: resd 1
> > > > + .SS0: resw 1
> > > > + resw 1
> > > > + .ESP1: resd 1
> > > > + .SS1: resw 1
> > > > + resw 1
> > > > + .ESP2: resd 1
> > > > + .SS2: resw 1
> > > > + resw 1
> > > > + ._CR3: resd 1
> > > > + .EIP: resd 1
> > > > + .EFLAGS: resd 1
> > > > + ._EAX: resd 1
> > > > + ._ECX: resd 1
> > > > + ._EDX: resd 1
> > > > + ._EBX: resd 1
> > > > + ._ESP: resd 1
> > > > + ._EBP: resd 1
> > > > + ._ESI: resd 1
> > > > + ._EDI: resd 1
> > > > + ._ES: resw 1
> > > > + resw 1
> > > > + ._CS: resw 1
> > > > + resw 1
> > > > + ._SS: resw 1
> > > > + resw 1
> > > > + ._DS: resw 1
> > > > + resw 1
> > > > + ._FS: resw 1
> > > > + resw 1
> > > > + ._GS: resw 1
> > > > + resw 1
> > > > + .LDT: resw 1
> > > > + resw 1
> > > > + resw 1
> > > > + resw 1
> > > > +endstruc
> > > > +
> > > > +;
> > > > +; CommonExceptionHandler()
> > > > +;
> > > > +extern ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +SECTION .data
> > > > +
> > > > +SECTION .text
> > > > +
> > > > +ALIGN 8
> > > > +
> > > > +;
> > > > +; Exception handler stub table
> > > > +;
> > > > +AsmExceptionEntryBegin:
> > > > +%assign Vector 0
> > > > +%rep 32
> > > > +
> > > > +DoIret%[Vector]:
> > > > + iretd
> > > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > > + db 0x6a ; push #VectorNum
> > > > + db %[Vector]
> > > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > + call eax
> > > > + mov esp, eax ; Restore stack top
> > > > + jmp DoIret%[Vector]
> > > > +
> > > > +%assign Vector Vector+1
> > > > +%endrep
> > > > +AsmExceptionEntryEnd:
> > > > +
> > > > +;
> > > > +; Common part of exception handler
> > > > +;
> > > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > > + ;
> > > > + ; Stack:
> > > > + ; +---------------------+ <-- EBP - 8
> > > > + ; + TSS Base +
> > > > + ; +---------------------+ <-- EBP - 4
> > > > + ; + CPUID.EDX +
> > > > + ; +---------------------+ <-- EBP
> > > > + ; + EIP +
> > > > + ; +---------------------+ <-- EBP + 4
> > > > + ; + Vector Number +
> > > > + ; +---------------------+ <-- EBP + 8
> > > > + ; + Error Code +
> > > > + ; +---------------------+
> > > > + ;
> > > > +
> > > > + mov ebp, esp ; Stack frame
> > > > +
> > > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > > + mov eax, 1
> > > > + cpuid
> > > > + push edx
> > > > +
> > > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > > +; current TSS base
> > > > + sub esp, 8
> > > > + sgdt [esp + 2]
> > > > + mov eax, [esp + 4] ; GDT base
> > > > + add esp, 8
> > > > +
> > > > + xor ebx, ebx
> > > > + str bx ; Current TR
> > > > +
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Current TSS base
> > > > + push ecx ; keep it in stack for later
> use
> > > > +
> > > > + movzx ebx, word [ecx] ; Previous Task Link
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Previous TSS base
> > > > +
> > > > +;
> > > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > > EFI_SYSTEM_CONTEXT_IA32
> > > > +; is 16-byte aligned
> > > > +;
> > > > + and esp, 0xfffffff0
> > > > + sub esp, 12
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + push dword [ecx + IA32_TSS._EAX]
> > > > + push dword [ecx + IA32_TSS._ECX]
> > > > + push dword [ecx + IA32_TSS._EDX]
> > > > + push dword [ecx + IA32_TSS._EBX]
> > > > + push dword [ecx + IA32_TSS._ESP]
> > > > + push dword [ecx + IA32_TSS._EBP]
> > > > + push dword [ecx + IA32_TSS._ESI]
> > > > + push dword [ecx + IA32_TSS._EDI]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > > + push eax
> > > > +
> > > > +;; UINT32 Eip;
> > > > + push dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > + sub esp, 8
> > > > + sidt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > + sub esp, 8
> > > > + sgdt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > > + push eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + mov eax, cr4
> > > > + push eax ; push cr4 firstly
> > > > +
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .1
> > > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > > +.1:
> > > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > > + jz .2
> > > > + or eax, BIT3 ; Set CR4.DE
> > > > +.2:
> > > > + mov cr4, eax
> > > > +
> > > > + mov eax, cr3
> > > > + push eax
> > > > + mov eax, cr2
> > > > + push eax
> > > > + xor eax, eax
> > > > + push eax
> > > > + mov eax, cr0
> > > > + push eax
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > + mov eax, dr7
> > > > + push eax
> > > > + mov eax, dr6
> > > > + push eax
> > > > + mov eax, dr3
> > > > + push eax
> > > > + mov eax, dr2
> > > > + push eax
> > > > + mov eax, dr1
> > > > + push eax
> > > > + mov eax, dr0
> > > > + push eax
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > > +;; when executing fxsave/fxrstor instruction
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > > + ; edx still contains result from CPUID above
> > > > + jz .3
> > > > + clts
> > > > + sub esp, 512
> > > > + mov edi, esp
> > > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > > +.3:
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + push dword [ebp + 8]
> > > > +
> > > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is
> > clear
> > > > + cld
> > > > +
> > > > +;; call into exception handler
> > > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +;; Prepare parameter and call
> > > > + mov edx, esp
> > > > + push edx ; EFI_SYSTEM_CONTEXT
> > > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector
> number)
> > > > +
> > > > + ;
> > > > + ; Call External Exception Handler
> > > > + ;
> > > > + call eax
> > > > + add esp, 8 ; Restore stack before calling
> > > > + mov ecx, esi ; Restore TSS base
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + add esp, 4
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .4
> > > > + mov esi, esp
> > > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > > +.4:
> > > > + add esp, 512
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > +;; Skip restoration of DRx registers to support debuggers
> > > > +;; that set breakpoints in interrupt/exception context
> > > > + add esp, 4 * 6
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + pop eax
> > > > + mov cr0, eax
> > > > + add esp, 4 ; not for Cr1
> > > > + pop eax
> > > > + mov cr2, eax
> > > > + pop eax
> > > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > > + pop eax
> > > > + mov cr4, eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + btr ebx, 9 ; Do 'cli'
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > +;; Best not let anyone mess with these particular registers...
> > > > + add esp, 24
> > > > +
> > > > +;; UINT32 Eip;
> > > > + pop dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > +;; NOTE - modified segment registers could hang the debugger... We
> > > > +;; could attempt to insulate ourselves against this possibility,
> > > > +;; but that poses risks as well.
> > > > +;;
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + pop dword [ecx + IA32_TSS._EDI]
> > > > + pop dword [ecx + IA32_TSS._ESI]
> > > > + add esp, 4 ; not for ebp
> > > > + add esp, 4 ; not for esp
> > > > + pop dword [ecx + IA32_TSS._EBX]
> > > > + pop dword [ecx + IA32_TSS._EDX]
> > > > + pop dword [ecx + IA32_TSS._ECX]
> > > > + pop dword [ecx + IA32_TSS._EAX]
> > > > +
> > > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > > +; where the exception is triggered.
> > > > +
> > > > +;; Create return context for iretd in stub function
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> pointer
> > > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > > + mov [eax - 0xc], ebx ; create EIP in old
> stack
> > > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > > + mov [eax - 0x8], ebx ; create CS in old
> stack
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + bts ebx, 8
> > > > + mov [eax - 0x4], ebx ; create eflags in old
> > > stack
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in
> old
> > > TSS
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> pointer
> > > > + sub eax, 0xc ; minus 12 byte
> > > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> pointer
> > > > +
> > > > +;; Replace the EIP of interrupted task with stub function
> > > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > > +
> > > > + mov ecx, [ebp - 8] ; Get current TSS
> base
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current
> stack
> > > top
> > > > + mov esp, ebp
> > > > +
> > > > + ret
> > > > +
> > > > +global ASM_PFX(SingleStepStubFunction)
> > > > +ASM_PFX(SingleStepStubFunction):
> > > > +;
> > > > +; we need clean TS bit in CR0 to execute
> > > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > > +;
> > > > + clts
> > > > + iretd
> > > > +
> > > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > > +ASM_PFX(AsmGetTssTemplateMap):
> > > > + push ebp ; C prolog
> > > > + mov ebp, esp
> > > > + pushad
> > > > +
> > > > + mov ebx, dword [ebp + 0x8]
> > > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > > AsmExceptionEntryBegin)
> > > > / 32
> > > > + mov dword [ebx + 0x8], 0
> > > > +
> > > > + popad
> > > > + pop ebp
> > > > + ret
> > > > +
> > > > diff --git
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > index 75443288a9..4c0d435136 100644
> > > > ---
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > index d70a99c100..e5c03c16c9 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > index 634ffcb21d..56b875b7c8 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > index 65f0cff680..214aafcc13 100644
> > > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextX64->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for
> setuping up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc <
> > > (UINTN)(StackSwitchData->GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit
> +
> > > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + //
> > > > + // Fixup IST
> > > > + //
> > > > + Tss->IST[Index] = StackTop;
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Set the IST field to enable corresponding IST
> > > > + //
> > > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > > (UINT8)(Index + 1);
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display CPU information.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > index 906480134a..c88be46286 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > @@ -43,4 +43,7 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > > +
> > > > #endif
> > > > --
> > > > 2.14.1.windows.1
> > >
> > > _______________________________________________
> > > edk2-devel mailing list
> > > edk2-devel@lists.01.org
> > > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 6:16 ` Yao, Jiewen
@ 2017-11-23 6:43 ` Wang, Jian J
2017-11-25 13:27 ` 答复: " Fan Jeff
2017-11-28 1:38 ` Wang, Jian J
0 siblings, 2 replies; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 6:43 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
Cc: Zeng, Star, Dong, Eric, Kinney, Michael D
1.1) Got your point. I'll add dummy function in this patch.
1.2) Yep, we're on the same page.
1.3) Here's my opinion:
Actually almost all MP code has such assumption: any AP configuration will copy
from BSP. If we allow AP to call InitializeCpuExceptionHandlers(), we have to do a lot
of other changes than just updating InitializeCpuExceptionHandlers(). If so, it may
be premature to figure out a solution at this patch.
In addition, CpuDxe actually calls InitializeCpuInterruptHandlers() which covers the
functionalities of InitializeCpuExceptionHandlers() (its settings will be overwritten).
If we want AP to initialize interrupt and exception individually, maybe we should
let AP call InitializeCpuInterruptHandlers() instead.
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 2:16 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Here is my thought for 1)
>
> 1.1) We must provide the InitializeCpuExceptionStackSwitchHandlers()
> implementation in Pei instance and Smm instance.
>
> The basic requirement is a library instance must provide symbol for functions
> declared in header file.
> It is ok to return unsupported. But we MUST provide the symbol.
>
> 1.2) For SMM, I think our ultimate goal is to remove SMM specific stack guard,
> and use the common one. Duplicating code is completely unnecessary, and it is
> easy to introduce bug. And unfortunately, we already have bug in existing SMM
> exception handler. -- That is a good reason to remove duplication.
>
> Again, it is not necessary to do it in this patch. I am totally OK to do it in another
> patch.
>
> 1.3) For PEI, I do not think we can use current way to allocate stack in data
> section, because it might be readonly in pre-mem phase. We must use some
> other way.
>
> 1.4) I believe this patch has a hidden assumption is that:
> InitializeCpuExceptionHandlers() won't be called by multiple APs.
> If 2 or more APs call the it at same time, it might be broken because you use
> mNewStack for all the callers....
> Is that right?
>
>
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Thursday, November 23, 2017 2:06 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Kinney,
> > Michael D <michael.d.kinney@intel.com>
> > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch support
> >
> >
> >
> > > -----Original Message-----
> > > From: Yao, Jiewen
> > > Sent: Thursday, November 23, 2017 1:50 PM
> > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > > Kinney, Michael D <michael.d.kinney@intel.com>
> > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch support
> > >
> > > Some thought:
> > >
> > > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented
> in
> > > DxeException.c.
> > > What about Pei/Smm instance?
> > >
> > > I think it is OK to not implement it at this moment. But we need make sure no
> > > architecture issue if we want to enable it some time later.
> > >
> > Like what we discussed before, this series of patch is for Stack Guard feature
> > which
> > is only available for DXE (because Stack Guard needs paging to work). Stack
> > switch
> > is enabled for the sake of Stack Guard feature. So I think it's enough to
> > implement
> > it in DxeException.c. In addition, SMM has its own implementation of stack
> guard
> > and stack switch. It's not necessary to do it again.
> >
> > I agree with you that we should merge those common code but I think we
> should
> > do
> > it in a separate patch series since it's not Stack Guard relevant. And I've
> removed
> > all architecture issues I can think of. Current stack switch initialization should
> work
> > for both PEI and SMM as well.
> >
> > > 2) #define IA32_GDT_TYPE_TSS 0x9
> > > This is generic, can we move to BaseLib.h?
> > >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > >
> > > > -----Original Message-----
> > > > From: Wang, Jian J
> > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > To: edk2-devel@lists.01.org
> > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Yao,
> > > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > > <michael.d.kinney@intel.com>
> > > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch
> > > > support
> > > >
> > > > > v2:
> > > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to
> > setup
> > > > stack
> > > > > switch. This can avoid allocating memory for it in this library.
> > > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > > phase of DXE core.
> > > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > > support
> > > > > memory allocation because those memory can passed in by
> > parameter
> > > > now.
> > > > > e. Remove the nasm macro to define exception handler one by one
> > and
> > > > add a
> > > > > function to return the start address of each handler.
> > > >
> > > > If Stack Guard is enabled and there's really a stack overflow happened
> during
> > > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > > usage, the exception handler, which shares the stack with normal UEFI
> driver,
> > > > cannot be executed and cannot dump the processor information.
> > > >
> > > > Without those information, it's very difficult for the BIOS developers locate
> > > > the root cause of stack overflow. And without a workable stack, the
> > developer
> > > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > > >
> > > > In order to make sure the exception handler to execute normally after
> stack
> > > > overflow. We need separate stacks for exception handlers in case of
> unusable
> > > > stack.
> > > >
> > > > IA processor allows to switch to a new stack during handling interrupt and
> > > > exception. But X64 and IA32 provides different ways to make it. X64
> provides
> > > > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > > > new stack for its handler. IA32 doesn't have IST mechanism and can only
> use
> > > > task gate to do it since task switch allows to load a new stack through its
> > > > task-state segment (TSS).
> > > >
> > > > Cc: Star Zeng <star.zeng@intel.com>
> > > > Cc: Eric Dong <eric.dong@intel.com>
> > > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > > ---
> > > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > > +++++++++++++++++++++
> > > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > > create mode 100644
> > > >
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > index 740a58828b..30334105d2 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > @@ -48,6 +48,32 @@
> > > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c,
> > > 0x83 }
> > > > \
> > > > }
> > > >
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > > +
> > > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > > CPU_TSS_SIZE)
> > > > +
> > > > +#define IA32_GDT_TYPE_TSS 0x9
> > > > +#define IA32_GDT_ALIGNMENT 8
> > > > +
> > > > +typedef struct {
> > > > + UINTN StackTop;
> > > > + UINTN StackSize;
> > > > + UINT8 *Exceptions;
> > > > + UINTN ExceptionNumber;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > + UINTN GdtSize;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > +
> > > > //
> > > > // Record exception handler information
> > > > //
> > > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > > );
> > > >
> > > > +/**
> > > > + Setup separate stack for specific exceptions.
> > > > +
> > > > + @param[in] IdtTable IDT table base.
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + );
> > > > +
> > > > +/**
> > > > + Return address map of exception handler template so that C code can
> > > > generate
> > > > + exception tables. The template is only for exceptions using task gate
> > instead
> > > > + of interrupt gate.
> > > > +
> > > > + @param AddressMap Pointer to a buffer where the address map is
> > > > returned.
> > > > +**/
> > > > +VOID
> > > > +EFIAPI
> > > > +AsmGetTssTemplateMap (
> > > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > > + );
> > > > +
> > > > #endif
> > > >
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > index f4a8d01c80..58e55a8a2e 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > @@ -47,6 +48,11 @@
> > > > PeiDxeSmmCpuException.c
> > > > DxeException.c
> > > >
> > > > +[Pcd]
> > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > +
> > > > [Packages]
> > > > MdePkg/MdePkg.dec
> > > > MdeModulePkg/MdeModulePkg.dec
> > > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > index 31febec976..c0b2c615aa 100644
> > > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > @@ -25,6 +25,10 @@ UINTN
> > mEnabledInterruptNum =
> > > > 0;
> > > >
> > > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > > >
> > > > +UINT8
> > > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > > +
> > CPU_KNOWN_GOOD_STACK_SIZE]
> > > > = {0};
> > > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > > +
> > > > /**
> > > > Common exception handler.
> > > >
> > > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > > )
> > > > {
> > > > + EFI_STATUS Status;
> > > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > +
> > > > mExceptionHandlerData.ReservedVectors =
> > > > mReservedVectorsData;
> > > > mExceptionHandlerData.ExternalInterruptHandler =
> > > > mExternalInterruptHandlerTable;
> > > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > +
> > > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > > + StackSwitchData.ExceptionNumber =
> > > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> > *)mNewGdt;
> > > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > > Gdtr.Limit + 1);
> > > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > > Gdtr.Limit + 1 +
> > > > +
> > > > CPU_TSS_DESC_SIZE);
> > > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > > + &StackSwitchData
> > > > + );
> > > > + }
> > > > + return Status;
> > > > }
> > > >
> > > > /**
> > > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > > {
> > > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > InterruptHandler,
> > > > &mExceptionHandlerData);
> > > > }
> > > > +
> > > > +/**
> > > > + Setup separate stack for given exceptions. This is required by
> > > > + PcdCpuStackGuard feature.
> > > > +
> > > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +InitializeCpuExceptionStackSwitchHandlers (
> > > > + IN VOID *StackSwitchData OPTIONAL
> > > > + )
> > > > +{
> > > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > > +}
> > > > diff --git
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > index f2c39eb193..0aaf794795 100644
> > > > ---
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > +++
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextIa32->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for
> > setuping
> > > > up
> > > > + stack switch.
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN Vector;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > >GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > > + (StackSwitchData->ExceptionNumber + 1);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + AsmGetTssTemplateMap (&TemplateMap);
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + TssDesc += 1;
> > > > + Tss += 1;
> > > > +
> > > > + //
> > > > + // Fixup TSS descriptor
> > > > + //
> > > > + TssBase = (UINTN)Tss;
> > > > +
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup TSS
> > > > + //
> > > > + Vector = StackSwitchData->Exceptions[Index];
> > > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > > + + Vector *
> > > > TemplateMap.ExceptionStubHeaderSize);
> > > > + Tss->EFLAGS = 0x2;
> > > > + Tss->ESP = StackTop;
> > > > + Tss->CR3 = AsmReadCr3 ();
> > > > + Tss->ES = AsmReadEs ();
> > > > + Tss->CS = AsmReadCs ();
> > > > + Tss->SS = AsmReadSs ();
> > > > + Tss->DS = AsmReadDs ();
> > > > + Tss->FS = AsmReadFs ();
> > > > + Tss->GS = AsmReadGs ();
> > > > +
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Update IDT to use Task Gate for given exception
> > > > + //
> > > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> > Gdtr.Base);
> > > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display processor context.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > index a8d3556a80..d9ded5977f 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > @@ -41,4 +41,12 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE \
> > > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > +#define CPU_TSS_SIZE \
> > > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > #endif
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > new file mode 100644
> > > > index 0000000000..62bcedea1a
> > > > --- /dev/null
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > @@ -0,0 +1,398 @@
> > > > +;------------------------------------------------------------------------------ ;
> > > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > > +; This program and the accompanying materials
> > > > +; are licensed and made available under the terms and conditions of the
> BSD
> > > > License
> > > > +; which accompanies this distribution. The full text of the license may be
> > > found
> > > > at
> > > > +; http://opensource.org/licenses/bsd-license.php.
> > > > +;
> > > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > > BASIS,
> > > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > > EXPRESS
> > > > OR IMPLIED.
> > > > +;
> > > > +; Module Name:
> > > > +;
> > > > +; ExceptionTssEntryAsm.Asm
> > > > +;
> > > > +; Abstract:
> > > > +;
> > > > +; IA32 CPU Exception Handler with Separate Stack
> > > > +;
> > > > +; Notes:
> > > > +;
> > > > +;------------------------------------------------------------------------------
> > > > +
> > > > +;
> > > > +; IA32 TSS Memory Layout Description
> > > > +;
> > > > +struc IA32_TSS
> > > > + resw 1
> > > > + resw 1
> > > > + .ESP0: resd 1
> > > > + .SS0: resw 1
> > > > + resw 1
> > > > + .ESP1: resd 1
> > > > + .SS1: resw 1
> > > > + resw 1
> > > > + .ESP2: resd 1
> > > > + .SS2: resw 1
> > > > + resw 1
> > > > + ._CR3: resd 1
> > > > + .EIP: resd 1
> > > > + .EFLAGS: resd 1
> > > > + ._EAX: resd 1
> > > > + ._ECX: resd 1
> > > > + ._EDX: resd 1
> > > > + ._EBX: resd 1
> > > > + ._ESP: resd 1
> > > > + ._EBP: resd 1
> > > > + ._ESI: resd 1
> > > > + ._EDI: resd 1
> > > > + ._ES: resw 1
> > > > + resw 1
> > > > + ._CS: resw 1
> > > > + resw 1
> > > > + ._SS: resw 1
> > > > + resw 1
> > > > + ._DS: resw 1
> > > > + resw 1
> > > > + ._FS: resw 1
> > > > + resw 1
> > > > + ._GS: resw 1
> > > > + resw 1
> > > > + .LDT: resw 1
> > > > + resw 1
> > > > + resw 1
> > > > + resw 1
> > > > +endstruc
> > > > +
> > > > +;
> > > > +; CommonExceptionHandler()
> > > > +;
> > > > +extern ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +SECTION .data
> > > > +
> > > > +SECTION .text
> > > > +
> > > > +ALIGN 8
> > > > +
> > > > +;
> > > > +; Exception handler stub table
> > > > +;
> > > > +AsmExceptionEntryBegin:
> > > > +%assign Vector 0
> > > > +%rep 32
> > > > +
> > > > +DoIret%[Vector]:
> > > > + iretd
> > > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > > + db 0x6a ; push #VectorNum
> > > > + db %[Vector]
> > > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > + call eax
> > > > + mov esp, eax ; Restore stack top
> > > > + jmp DoIret%[Vector]
> > > > +
> > > > +%assign Vector Vector+1
> > > > +%endrep
> > > > +AsmExceptionEntryEnd:
> > > > +
> > > > +;
> > > > +; Common part of exception handler
> > > > +;
> > > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > > + ;
> > > > + ; Stack:
> > > > + ; +---------------------+ <-- EBP - 8
> > > > + ; + TSS Base +
> > > > + ; +---------------------+ <-- EBP - 4
> > > > + ; + CPUID.EDX +
> > > > + ; +---------------------+ <-- EBP
> > > > + ; + EIP +
> > > > + ; +---------------------+ <-- EBP + 4
> > > > + ; + Vector Number +
> > > > + ; +---------------------+ <-- EBP + 8
> > > > + ; + Error Code +
> > > > + ; +---------------------+
> > > > + ;
> > > > +
> > > > + mov ebp, esp ; Stack frame
> > > > +
> > > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > > + mov eax, 1
> > > > + cpuid
> > > > + push edx
> > > > +
> > > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > > +; current TSS base
> > > > + sub esp, 8
> > > > + sgdt [esp + 2]
> > > > + mov eax, [esp + 4] ; GDT base
> > > > + add esp, 8
> > > > +
> > > > + xor ebx, ebx
> > > > + str bx ; Current TR
> > > > +
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Current TSS base
> > > > + push ecx ; keep it in stack for later use
> > > > +
> > > > + movzx ebx, word [ecx] ; Previous Task Link
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Previous TSS base
> > > > +
> > > > +;
> > > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > > EFI_SYSTEM_CONTEXT_IA32
> > > > +; is 16-byte aligned
> > > > +;
> > > > + and esp, 0xfffffff0
> > > > + sub esp, 12
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + push dword [ecx + IA32_TSS._EAX]
> > > > + push dword [ecx + IA32_TSS._ECX]
> > > > + push dword [ecx + IA32_TSS._EDX]
> > > > + push dword [ecx + IA32_TSS._EBX]
> > > > + push dword [ecx + IA32_TSS._ESP]
> > > > + push dword [ecx + IA32_TSS._EBP]
> > > > + push dword [ecx + IA32_TSS._ESI]
> > > > + push dword [ecx + IA32_TSS._EDI]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > > + push eax
> > > > +
> > > > +;; UINT32 Eip;
> > > > + push dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > + sub esp, 8
> > > > + sidt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > + sub esp, 8
> > > > + sgdt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > > + push eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + mov eax, cr4
> > > > + push eax ; push cr4 firstly
> > > > +
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .1
> > > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > > +.1:
> > > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > > + jz .2
> > > > + or eax, BIT3 ; Set CR4.DE
> > > > +.2:
> > > > + mov cr4, eax
> > > > +
> > > > + mov eax, cr3
> > > > + push eax
> > > > + mov eax, cr2
> > > > + push eax
> > > > + xor eax, eax
> > > > + push eax
> > > > + mov eax, cr0
> > > > + push eax
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > + mov eax, dr7
> > > > + push eax
> > > > + mov eax, dr6
> > > > + push eax
> > > > + mov eax, dr3
> > > > + push eax
> > > > + mov eax, dr2
> > > > + push eax
> > > > + mov eax, dr1
> > > > + push eax
> > > > + mov eax, dr0
> > > > + push eax
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > > +;; when executing fxsave/fxrstor instruction
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > > + ; edx still contains result from CPUID above
> > > > + jz .3
> > > > + clts
> > > > + sub esp, 512
> > > > + mov edi, esp
> > > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > > +.3:
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + push dword [ebp + 8]
> > > > +
> > > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is
> > > clear
> > > > + cld
> > > > +
> > > > +;; call into exception handler
> > > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +;; Prepare parameter and call
> > > > + mov edx, esp
> > > > + push edx ; EFI_SYSTEM_CONTEXT
> > > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > > > +
> > > > + ;
> > > > + ; Call External Exception Handler
> > > > + ;
> > > > + call eax
> > > > + add esp, 8 ; Restore stack before calling
> > > > + mov ecx, esi ; Restore TSS base
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + add esp, 4
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .4
> > > > + mov esi, esp
> > > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > > +.4:
> > > > + add esp, 512
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > +;; Skip restoration of DRx registers to support debuggers
> > > > +;; that set breakpoints in interrupt/exception context
> > > > + add esp, 4 * 6
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + pop eax
> > > > + mov cr0, eax
> > > > + add esp, 4 ; not for Cr1
> > > > + pop eax
> > > > + mov cr2, eax
> > > > + pop eax
> > > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > > + pop eax
> > > > + mov cr4, eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + btr ebx, 9 ; Do 'cli'
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > +;; Best not let anyone mess with these particular registers...
> > > > + add esp, 24
> > > > +
> > > > +;; UINT32 Eip;
> > > > + pop dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > +;; NOTE - modified segment registers could hang the debugger... We
> > > > +;; could attempt to insulate ourselves against this possibility,
> > > > +;; but that poses risks as well.
> > > > +;;
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + pop dword [ecx + IA32_TSS._EDI]
> > > > + pop dword [ecx + IA32_TSS._ESI]
> > > > + add esp, 4 ; not for ebp
> > > > + add esp, 4 ; not for esp
> > > > + pop dword [ecx + IA32_TSS._EBX]
> > > > + pop dword [ecx + IA32_TSS._EDX]
> > > > + pop dword [ecx + IA32_TSS._ECX]
> > > > + pop dword [ecx + IA32_TSS._EAX]
> > > > +
> > > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > > +; where the exception is triggered.
> > > > +
> > > > +;; Create return context for iretd in stub function
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > > + mov [eax - 0xc], ebx ; create EIP in old
> > stack
> > > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > > + mov [eax - 0x8], ebx ; create CS in old stack
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + bts ebx, 8
> > > > + mov [eax - 0x4], ebx ; create eflags in old
> > stack
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old
> > TSS
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > + sub eax, 0xc ; minus 12 byte
> > > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> > pointer
> > > > +
> > > > +;; Replace the EIP of interrupted task with stub function
> > > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > > +
> > > > + mov ecx, [ebp - 8] ; Get current TSS base
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack
> > top
> > > > + mov esp, ebp
> > > > +
> > > > + ret
> > > > +
> > > > +global ASM_PFX(SingleStepStubFunction)
> > > > +ASM_PFX(SingleStepStubFunction):
> > > > +;
> > > > +; we need clean TS bit in CR0 to execute
> > > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > > +;
> > > > + clts
> > > > + iretd
> > > > +
> > > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > > +ASM_PFX(AsmGetTssTemplateMap):
> > > > + push ebp ; C prolog
> > > > + mov ebp, esp
> > > > + pushad
> > > > +
> > > > + mov ebx, dword [ebp + 0x8]
> > > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > AsmExceptionEntryBegin)
> > > > / 32
> > > > + mov dword [ebx + 0x8], 0
> > > > +
> > > > + popad
> > > > + pop ebp
> > > > + ret
> > > > +
> > > > diff --git
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > index 75443288a9..4c0d435136 100644
> > > > ---
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > index d70a99c100..e5c03c16c9 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > index 634ffcb21d..56b875b7c8 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > index 65f0cff680..214aafcc13 100644
> > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextX64->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > >GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + //
> > > > + // Fixup IST
> > > > + //
> > > > + Tss->IST[Index] = StackTop;
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Set the IST field to enable corresponding IST
> > > > + //
> > > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > > (UINT8)(Index + 1);
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display CPU information.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > index 906480134a..c88be46286 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > @@ -43,4 +43,7 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > > +
> > > > #endif
> > > > --
> > > > 2.14.1.windows.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 6:25 ` Yao, Jiewen
@ 2017-11-23 7:54 ` Wang, Jian J
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Jian J @ 2017-11-23 7:54 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
1) No impact at all.
2)
Page at stack base will be disabled.
If Arch == IA32,
The stack switch for handler of #PF/#DD will be setup for BSP and AP
Else
The handler of #PF/#DD keeps the same
EndIf
If StackOverFlow,
If Arch == IA32,
#PF is triggered and its handler is called with KnownGoodStack.
CPU context is dumped successfully.
Else
#PF handler is triggered but its handler is called with corrupted stack.
CPU context cannot be dumped.
EndIf
EndIf
3)
If Cpu == BSP,
Only Exceptions will be handled. Interrupts will not.
Else,
No exceptions and interrupts will be handled.
EndIf
4)
Page at stack base will be disabled.
If Cpu == BSP,
Only Exceptions will be handled. Interrupts will not.
If Arch == IA32,
The stack switch for handler of #PF/#DD will be setup for BSP
Else
The handler of #PF/#DD keeps the same
EndIf
If StackOverFlow,
If Arch == IA32,
#PF is triggered and its handler is called with KnownGoodStack.
CPU context is dumped successfully.
Else
#PF handler is triggered but its handler is called with corrupted stack.
CPU context cannot be dumped.
EndIf
EndIf
Else,
No exceptions and interrupts will be handled.
EndIf
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 2:25 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> I am ok to keep FALSE by default. But I still suggest we test existing UEFI OS
> behavior.
>
> Please help me understand below condition, if we do not change a platform
> specific CPU driver:
> 1) If PcdCpuStackGuard is FALSE, and CPU driver is still consuming existing API in
> ExceptionLib. Is there any impact?
> 2) If PcdCpuStackGuard is TRUE, and CPU driver is still consuming existing API in
> ExceptionLib. Is there any impact?
> 3) If PcdCpuStackGuard is FALSE, and CPU driver is not consuming existing API in
> ExceptionLib. Is there any impact?
> 4) If PcdCpuStackGuard is TRUE, and CPU driver is not consuming existing API in
> ExceptionLib. Is there any impact?
>
>
> Thank you
> Yao Jiewen
>
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Thursday, November 23, 2017 2:09 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> > <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch support
> >
> > If PcdCpuStackGuard is not enabled, there's no impact. If it's enabled, the only
> > issue is that the exception dump cannot be done but no other impact. From
> this
> > point of view, maybe PcdCpuStackGuard should be FALSE by default.
> >
> > > -----Original Message-----
> > > From: Yao, Jiewen
> > > Sent: Thursday, November 23, 2017 1:59 PM
> > > To: Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J
> > <jian.j.wang@intel.com>;
> > > edk2-devel@lists.01.org
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> > > <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch support
> > >
> > > One more question:
> > > I notice not all platforms are using the CpuDxe in UefiCpuPkg.
> > > If so, is there any impact to the platform whose CPU driver does not have
> such
> > > InitializeCpuExceptionStackSwitchHandlers() call?
> > > Have you tested that condition?
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > > > -----Original Message-----
> > > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> > Yao,
> > > > Jiewen
> > > > Sent: Thursday, November 23, 2017 1:50 PM
> > > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> > > > <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > > > Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib:
> Add
> > > > stack switch support
> > > >
> > > > Some thought:
> > > >
> > > > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented
> in
> > > > DxeException.c.
> > > > What about Pei/Smm instance?
> > > >
> > > > I think it is OK to not implement it at this moment. But we need make sure
> no
> > > > architecture issue if we want to enable it some time later.
> > > >
> > > > 2) #define IA32_GDT_TYPE_TSS 0x9
> > > > This is generic, can we move to BaseLib.h?
> > > >
> > > >
> > > > Thank you
> > > > Yao Jiewen
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Wang, Jian J
> > > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > > To: edk2-devel@lists.01.org
> > > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > > Yao,
> > > > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > > > <michael.d.kinney@intel.com>
> > > > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch
> > > > > support
> > > > >
> > > > > > v2:
> > > > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to
> > setup
> > > > > stack
> > > > > > switch. This can avoid allocating memory for it in this library.
> > > > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > > > phase of DXE core.
> > > > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > > > support
> > > > > > memory allocation because those memory can passed in by
> > > > parameter
> > > > > now.
> > > > > > e. Remove the nasm macro to define exception handler one by one
> > and
> > > > > add a
> > > > > > function to return the start address of each handler.
> > > > >
> > > > > If Stack Guard is enabled and there's really a stack overflow happened
> > during
> > > > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > > > usage, the exception handler, which shares the stack with normal UEFI
> > driver,
> > > > > cannot be executed and cannot dump the processor information.
> > > > >
> > > > > Without those information, it's very difficult for the BIOS developers
> locate
> > > > > the root cause of stack overflow. And without a workable stack, the
> > > developer
> > > > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > > > >
> > > > > In order to make sure the exception handler to execute normally after
> stack
> > > > > overflow. We need separate stacks for exception handlers in case of
> > > unusable
> > > > > stack.
> > > > >
> > > > > IA processor allows to switch to a new stack during handling interrupt
> and
> > > > > exception. But X64 and IA32 provides different ways to make it. X64
> > provides
> > > > > interrupt stack table (IST) to allow maximum 7 different exceptions to
> have
> > > > > new stack for its handler. IA32 doesn't have IST mechanism and can only
> use
> > > > > task gate to do it since task switch allows to load a new stack through its
> > > > > task-state segment (TSS).
> > > > >
> > > > > Cc: Star Zeng <star.zeng@intel.com>
> > > > > Cc: Eric Dong <eric.dong@intel.com>
> > > > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > > > ---
> > > > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > > > +++++++++++++++++++++
> > > > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > > > create mode 100644
> > > > >
> > > >
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > > > >
> > > > > diff --git
> > > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > index 740a58828b..30334105d2 100644
> > > > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > @@ -48,6 +48,32 @@
> > > > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9,
> > 0x2c,
> > > > 0x83 }
> > > > > \
> > > > > }
> > > > >
> > > > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > > > +
> > > > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > > > +
> > > > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > > > +
> > > > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > > > CPU_TSS_SIZE)
> > > > > +
> > > > > +#define IA32_GDT_TYPE_TSS 0x9
> > > > > +#define IA32_GDT_ALIGNMENT 8
> > > > > +
> > > > > +typedef struct {
> > > > > + UINTN StackTop;
> > > > > + UINTN StackSize;
> > > > > + UINT8 *Exceptions;
> > > > > + UINTN ExceptionNumber;
> > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > > + UINTN GdtSize;
> > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > > +
> > > > > //
> > > > > // Record exception handler information
> > > > > //
> > > > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > > > );
> > > > >
> > > > > +/**
> > > > > + Setup separate stack for specific exceptions.
> > > > > +
> > > > > + @param[in] IdtTable IDT table base.
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +ArchSetupExcpetionStack (
> > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > + );
> > > > > +
> > > > > +/**
> > > > > + Return address map of exception handler template so that C code can
> > > > > generate
> > > > > + exception tables. The template is only for exceptions using task gate
> > > > instead
> > > > > + of interrupt gate.
> > > > > +
> > > > > + @param AddressMap Pointer to a buffer where the address map is
> > > > > returned.
> > > > > +**/
> > > > > +VOID
> > > > > +EFIAPI
> > > > > +AsmGetTssTemplateMap (
> > > > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > > > + );
> > > > > +
> > > > > #endif
> > > > >
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > index f4a8d01c80..58e55a8a2e 100644
> > > > > ---
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > @@ -47,6 +48,11 @@
> > > > > PeiDxeSmmCpuException.c
> > > > > DxeException.c
> > > > >
> > > > > +[Pcd]
> > > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > > +
> > > > > [Packages]
> > > > > MdePkg/MdePkg.dec
> > > > > MdeModulePkg/MdeModulePkg.dec
> > > > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > index 31febec976..c0b2c615aa 100644
> > > > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > @@ -25,6 +25,10 @@ UINTN
> > mEnabledInterruptNum
> > > > =
> > > > > 0;
> > > > >
> > > > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > > > >
> > > > > +UINT8
> > > > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > > > +
> > > > CPU_KNOWN_GOOD_STACK_SIZE]
> > > > > = {0};
> > > > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > > > +
> > > > > /**
> > > > > Common exception handler.
> > > > >
> > > > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > > > )
> > > > > {
> > > > > + EFI_STATUS Status;
> > > > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > > > + IA32_DESCRIPTOR Idtr;
> > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > +
> > > > > mExceptionHandlerData.ReservedVectors =
> > > > > mReservedVectorsData;
> > > > > mExceptionHandlerData.ExternalInterruptHandler =
> > > > > mExternalInterruptHandlerTable;
> > > > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > > &mExceptionHandlerData);
> > > > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > > &mExceptionHandlerData);
> > > > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > > > + AsmReadIdtr (&Idtr);
> > > > > + AsmReadGdtr (&Gdtr);
> > > > > +
> > > > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > > > + StackSwitchData.ExceptionNumber =
> > > > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> > *)mNewGdt;
> > > > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > > > Gdtr.Limit + 1);
> > > > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > > > Gdtr.Limit + 1 +
> > > > > +
> > > > > CPU_TSS_DESC_SIZE);
> > > > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > > > + &StackSwitchData
> > > > > + );
> > > > > + }
> > > > > + return Status;
> > > > > }
> > > > >
> > > > > /**
> > > > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > > > {
> > > > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > > > InterruptHandler,
> > > > > &mExceptionHandlerData);
> > > > > }
> > > > > +
> > > > > +/**
> > > > > + Setup separate stack for given exceptions. This is required by
> > > > > + PcdCpuStackGuard feature.
> > > > > +
> > > > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > > > +
> > > > > + @param[in] StackSwitchData Pointer to data required for
> > setuping up
> > > > > + stack switch.
> > > > > +
> > > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > > + initialized.
> > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > > content.
> > > > > +
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +InitializeCpuExceptionStackSwitchHandlers (
> > > > > + IN VOID *StackSwitchData OPTIONAL
> > > > > + )
> > > > > +{
> > > > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > > > +}
> > > > > diff --git
> > > > >
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > index f2c39eb193..0aaf794795 100644
> > > > > ---
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > +++
> > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > > > SystemContext.SystemContextIa32->ExceptionData =
> > > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > > }
> > > > >
> > > > > +/**
> > > > > + Setup separate stack for given exceptions.
> > > > > +
> > > > > + @param[in] StackSwitchData Pointer to data required for
> > setuping
> > > > > up
> > > > > + stack switch.
> > > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > > + initialized.
> > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > > content.
> > > > > +
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +ArchSetupExcpetionStack (
> > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > + )
> > > > > +{
> > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > + IA32_DESCRIPTOR Idtr;
> > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > + UINTN StackTop;
> > > > > + UINTN Index;
> > > > > + UINTN Vector;
> > > > > + UINTN TssBase;
> > > > > + UINTN GdtSize;
> > > > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > > > +
> > > > > + if (StackSwitchData == NULL ||
> > > > > + StackSwitchData->StackTop == 0 ||
> > > > > + StackSwitchData->StackSize == 0 ||
> > > > > + StackSwitchData->Exceptions == NULL ||
> > > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > > + StackSwitchData->GdtTable == NULL ||
> > > > > + StackSwitchData->IdtTable == NULL ||
> > > > > + StackSwitchData->TssDesc == NULL ||
> > > > > + StackSwitchData->Tss == NULL) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // The caller is responsible for that the GDT table, no matter the
> existing
> > > > > + // one or newly allocated, has enough space to hold descriptors for
> > > > exception
> > > > > + // task-state segments.
> > > > > + //
> > > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> > 1)) !=
> > > 0)
> > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc <
> > > > (UINTN)(StackSwitchData->GdtTable))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > > StackSwitchData->GdtSize))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > > > + (StackSwitchData->ExceptionNumber + 1);
> > > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Initialize new GDT table and/or IDT table, if any
> > > > > + //
> > > > > + AsmReadIdtr (&Idtr);
> > > > > + AsmReadGdtr (&Gdtr);
> > > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit
> > +
> > > > 1);
> > > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Fixup current task descriptor. Task-state segment for current task
> will
> > > > > + // be filled by processor during task switching.
> > > > > + //
> > > > > + TssDesc = StackSwitchData->TssDesc;
> > > > > + Tss = StackSwitchData->Tss;
> > > > > +
> > > > > + TssBase = (UINTN)Tss;
> > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > + TssDesc->Bits.P = 1;
> > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > > +
> > > > > + //
> > > > > + // Fixup exception task descriptor and task-state segment
> > > > > + //
> > > > > + AsmGetTssTemplateMap (&TemplateMap);
> > > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > > + IdtTable = StackSwitchData->IdtTable;
> > > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > > + TssDesc += 1;
> > > > > + Tss += 1;
> > > > > +
> > > > > + //
> > > > > + // Fixup TSS descriptor
> > > > > + //
> > > > > + TssBase = (UINTN)Tss;
> > > > > +
> > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > + TssDesc->Bits.P = 1;
> > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > > +
> > > > > + //
> > > > > + // Fixup TSS
> > > > > + //
> > > > > + Vector = StackSwitchData->Exceptions[Index];
> > > > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > > > + + Vector *
> > > > > TemplateMap.ExceptionStubHeaderSize);
> > > > > + Tss->EFLAGS = 0x2;
> > > > > + Tss->ESP = StackTop;
> > > > > + Tss->CR3 = AsmReadCr3 ();
> > > > > + Tss->ES = AsmReadEs ();
> > > > > + Tss->CS = AsmReadCs ();
> > > > > + Tss->SS = AsmReadSs ();
> > > > > + Tss->DS = AsmReadDs ();
> > > > > + Tss->FS = AsmReadFs ();
> > > > > + Tss->GS = AsmReadGs ();
> > > > > +
> > > > > + StackTop -= StackSwitchData->StackSize;
> > > > > +
> > > > > + //
> > > > > + // Update IDT to use Task Gate for given exception
> > > > > + //
> > > > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> > Gdtr.Base);
> > > > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Publish GDT
> > > > > + //
> > > > > + AsmWriteGdtr (&Gdtr);
> > > > > +
> > > > > + //
> > > > > + // Load current task
> > > > > + //
> > > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > > +
> > > > > + //
> > > > > + // Publish IDT
> > > > > + //
> > > > > + AsmWriteIdtr (&Idtr);
> > > > > +
> > > > > + return EFI_SUCCESS;
> > > > > +}
> > > > > +
> > > > > /**
> > > > > Display processor context.
> > > > >
> > > > > diff --git
> > > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > index a8d3556a80..d9ded5977f 100644
> > > > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > @@ -41,4 +41,12 @@ typedef struct {
> > > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > > } RESERVED_VECTORS_DATA;
> > > > >
> > > > > +#define CPU_TSS_DESC_SIZE \
> > > > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > > +
> > > > > +#define CPU_TSS_SIZE \
> > > > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > > +
> > > > > #endif
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > m
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > m
> > > > > new file mode 100644
> > > > > index 0000000000..62bcedea1a
> > > > > --- /dev/null
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > m
> > > > > @@ -0,0 +1,398 @@
> > > > > +;------------------------------------------------------------------------------ ;
> > > > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > > > +; This program and the accompanying materials
> > > > > +; are licensed and made available under the terms and conditions of the
> > BSD
> > > > > License
> > > > > +; which accompanies this distribution. The full text of the license may
> be
> > > > found
> > > > > at
> > > > > +; http://opensource.org/licenses/bsd-license.php.
> > > > > +;
> > > > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> > > > BASIS,
> > > > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > > EXPRESS
> > > > > OR IMPLIED.
> > > > > +;
> > > > > +; Module Name:
> > > > > +;
> > > > > +; ExceptionTssEntryAsm.Asm
> > > > > +;
> > > > > +; Abstract:
> > > > > +;
> > > > > +; IA32 CPU Exception Handler with Separate Stack
> > > > > +;
> > > > > +; Notes:
> > > > > +;
> > > > > +;------------------------------------------------------------------------------
> > > > > +
> > > > > +;
> > > > > +; IA32 TSS Memory Layout Description
> > > > > +;
> > > > > +struc IA32_TSS
> > > > > + resw 1
> > > > > + resw 1
> > > > > + .ESP0: resd 1
> > > > > + .SS0: resw 1
> > > > > + resw 1
> > > > > + .ESP1: resd 1
> > > > > + .SS1: resw 1
> > > > > + resw 1
> > > > > + .ESP2: resd 1
> > > > > + .SS2: resw 1
> > > > > + resw 1
> > > > > + ._CR3: resd 1
> > > > > + .EIP: resd 1
> > > > > + .EFLAGS: resd 1
> > > > > + ._EAX: resd 1
> > > > > + ._ECX: resd 1
> > > > > + ._EDX: resd 1
> > > > > + ._EBX: resd 1
> > > > > + ._ESP: resd 1
> > > > > + ._EBP: resd 1
> > > > > + ._ESI: resd 1
> > > > > + ._EDI: resd 1
> > > > > + ._ES: resw 1
> > > > > + resw 1
> > > > > + ._CS: resw 1
> > > > > + resw 1
> > > > > + ._SS: resw 1
> > > > > + resw 1
> > > > > + ._DS: resw 1
> > > > > + resw 1
> > > > > + ._FS: resw 1
> > > > > + resw 1
> > > > > + ._GS: resw 1
> > > > > + resw 1
> > > > > + .LDT: resw 1
> > > > > + resw 1
> > > > > + resw 1
> > > > > + resw 1
> > > > > +endstruc
> > > > > +
> > > > > +;
> > > > > +; CommonExceptionHandler()
> > > > > +;
> > > > > +extern ASM_PFX(CommonExceptionHandler)
> > > > > +
> > > > > +SECTION .data
> > > > > +
> > > > > +SECTION .text
> > > > > +
> > > > > +ALIGN 8
> > > > > +
> > > > > +;
> > > > > +; Exception handler stub table
> > > > > +;
> > > > > +AsmExceptionEntryBegin:
> > > > > +%assign Vector 0
> > > > > +%rep 32
> > > > > +
> > > > > +DoIret%[Vector]:
> > > > > + iretd
> > > > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > > > + db 0x6a ; push #VectorNum
> > > > > + db %[Vector]
> > > > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > > + call eax
> > > > > + mov esp, eax ; Restore stack top
> > > > > + jmp DoIret%[Vector]
> > > > > +
> > > > > +%assign Vector Vector+1
> > > > > +%endrep
> > > > > +AsmExceptionEntryEnd:
> > > > > +
> > > > > +;
> > > > > +; Common part of exception handler
> > > > > +;
> > > > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > > > + ;
> > > > > + ; Stack:
> > > > > + ; +---------------------+ <-- EBP - 8
> > > > > + ; + TSS Base +
> > > > > + ; +---------------------+ <-- EBP - 4
> > > > > + ; + CPUID.EDX +
> > > > > + ; +---------------------+ <-- EBP
> > > > > + ; + EIP +
> > > > > + ; +---------------------+ <-- EBP + 4
> > > > > + ; + Vector Number +
> > > > > + ; +---------------------+ <-- EBP + 8
> > > > > + ; + Error Code +
> > > > > + ; +---------------------+
> > > > > + ;
> > > > > +
> > > > > + mov ebp, esp ; Stack frame
> > > > > +
> > > > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > > > + mov eax, 1
> > > > > + cpuid
> > > > > + push edx
> > > > > +
> > > > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > > > +; current TSS base
> > > > > + sub esp, 8
> > > > > + sgdt [esp + 2]
> > > > > + mov eax, [esp + 4] ; GDT base
> > > > > + add esp, 8
> > > > > +
> > > > > + xor ebx, ebx
> > > > > + str bx ; Current TR
> > > > > +
> > > > > + mov ecx, [eax + ebx + 2]
> > > > > + shl ecx, 8
> > > > > + mov cl, [eax + ebx + 7]
> > > > > + ror ecx, 8 ; ecx = Current TSS base
> > > > > + push ecx ; keep it in stack for later
> > use
> > > > > +
> > > > > + movzx ebx, word [ecx] ; Previous Task Link
> > > > > + mov ecx, [eax + ebx + 2]
> > > > > + shl ecx, 8
> > > > > + mov cl, [eax + ebx + 7]
> > > > > + ror ecx, 8 ; ecx = Previous TSS base
> > > > > +
> > > > > +;
> > > > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > > > EFI_SYSTEM_CONTEXT_IA32
> > > > > +; is 16-byte aligned
> > > > > +;
> > > > > + and esp, 0xfffffff0
> > > > > + sub esp, 12
> > > > > +
> > > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > > + push dword [ecx + IA32_TSS._EAX]
> > > > > + push dword [ecx + IA32_TSS._ECX]
> > > > > + push dword [ecx + IA32_TSS._EDX]
> > > > > + push dword [ecx + IA32_TSS._EBX]
> > > > > + push dword [ecx + IA32_TSS._ESP]
> > > > > + push dword [ecx + IA32_TSS._EBP]
> > > > > + push dword [ecx + IA32_TSS._ESI]
> > > > > + push dword [ecx + IA32_TSS._EDI]
> > > > > +
> > > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > > > + push eax
> > > > > +
> > > > > +;; UINT32 Eip;
> > > > > + push dword [ecx + IA32_TSS.EIP]
> > > > > +
> > > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > > + sub esp, 8
> > > > > + sidt [esp]
> > > > > + mov eax, [esp + 2]
> > > > > + xchg eax, [esp]
> > > > > + and eax, 0xFFFF
> > > > > + mov [esp+4], eax
> > > > > +
> > > > > + sub esp, 8
> > > > > + sgdt [esp]
> > > > > + mov eax, [esp + 2]
> > > > > + xchg eax, [esp]
> > > > > + and eax, 0xFFFF
> > > > > + mov [esp+4], eax
> > > > > +
> > > > > +;; UINT32 Ldtr, Tr;
> > > > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > > > + push eax
> > > > > +
> > > > > +;; UINT32 EFlags;
> > > > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > > > +
> > > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > > + mov eax, cr4
> > > > > + push eax ; push cr4 firstly
> > > > > +
> > > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > > + jz .1
> > > > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > > > +.1:
> > > > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > > > + jz .2
> > > > > + or eax, BIT3 ; Set CR4.DE
> > > > > +.2:
> > > > > + mov cr4, eax
> > > > > +
> > > > > + mov eax, cr3
> > > > > + push eax
> > > > > + mov eax, cr2
> > > > > + push eax
> > > > > + xor eax, eax
> > > > > + push eax
> > > > > + mov eax, cr0
> > > > > + push eax
> > > > > +
> > > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > > + mov eax, dr7
> > > > > + push eax
> > > > > + mov eax, dr6
> > > > > + push eax
> > > > > + mov eax, dr3
> > > > > + push eax
> > > > > + mov eax, dr2
> > > > > + push eax
> > > > > + mov eax, dr1
> > > > > + push eax
> > > > > + mov eax, dr0
> > > > > + push eax
> > > > > +
> > > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > > > +;; when executing fxsave/fxrstor instruction
> > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > > > + ; edx still contains result from CPUID above
> > > > > + jz .3
> > > > > + clts
> > > > > + sub esp, 512
> > > > > + mov edi, esp
> > > > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > > > +.3:
> > > > > +
> > > > > +;; UINT32 ExceptionData;
> > > > > + push dword [ebp + 8]
> > > > > +
> > > > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs
> is
> > > clear
> > > > > + cld
> > > > > +
> > > > > +;; call into exception handler
> > > > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > > > +
> > > > > +;; Prepare parameter and call
> > > > > + mov edx, esp
> > > > > + push edx ; EFI_SYSTEM_CONTEXT
> > > > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector
> > number)
> > > > > +
> > > > > + ;
> > > > > + ; Call External Exception Handler
> > > > > + ;
> > > > > + call eax
> > > > > + add esp, 8 ; Restore stack before calling
> > > > > + mov ecx, esi ; Restore TSS base
> > > > > +
> > > > > +;; UINT32 ExceptionData;
> > > > > + add esp, 4
> > > > > +
> > > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > > + jz .4
> > > > > + mov esi, esp
> > > > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > > > +.4:
> > > > > + add esp, 512
> > > > > +
> > > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > > +;; Skip restoration of DRx registers to support debuggers
> > > > > +;; that set breakpoints in interrupt/exception context
> > > > > + add esp, 4 * 6
> > > > > +
> > > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > > + pop eax
> > > > > + mov cr0, eax
> > > > > + add esp, 4 ; not for Cr1
> > > > > + pop eax
> > > > > + mov cr2, eax
> > > > > + pop eax
> > > > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > > > + pop eax
> > > > > + mov cr4, eax
> > > > > +
> > > > > +;; UINT32 EFlags;
> > > > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > > + btr ebx, 9 ; Do 'cli'
> > > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > > > +
> > > > > +;; UINT32 Ldtr, Tr;
> > > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > > +;; Best not let anyone mess with these particular registers...
> > > > > + add esp, 24
> > > > > +
> > > > > +;; UINT32 Eip;
> > > > > + pop dword [ecx + IA32_TSS.EIP]
> > > > > +
> > > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > > +;; NOTE - modified segment registers could hang the debugger... We
> > > > > +;; could attempt to insulate ourselves against this possibility,
> > > > > +;; but that poses risks as well.
> > > > > +;;
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > > > +
> > > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > > + pop dword [ecx + IA32_TSS._EDI]
> > > > > + pop dword [ecx + IA32_TSS._ESI]
> > > > > + add esp, 4 ; not for ebp
> > > > > + add esp, 4 ; not for esp
> > > > > + pop dword [ecx + IA32_TSS._EBX]
> > > > > + pop dword [ecx + IA32_TSS._EDX]
> > > > > + pop dword [ecx + IA32_TSS._ECX]
> > > > > + pop dword [ecx + IA32_TSS._EAX]
> > > > > +
> > > > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > > > +; where the exception is triggered.
> > > > > +
> > > > > +;; Create return context for iretd in stub function
> > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > > > + mov [eax - 0xc], ebx ; create EIP in old
> > stack
> > > > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > > > + mov [eax - 0x8], ebx ; create CS in old
> > stack
> > > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > > + bts ebx, 8
> > > > > + mov [eax - 0x4], ebx ; create eflags in old
> > > > stack
> > > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in
> > old
> > > > TSS
> > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > > + sub eax, 0xc ; minus 12 byte
> > > > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> > pointer
> > > > > +
> > > > > +;; Replace the EIP of interrupted task with stub function
> > > > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > > > +
> > > > > + mov ecx, [ebp - 8] ; Get current TSS
> > base
> > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current
> > stack
> > > > top
> > > > > + mov esp, ebp
> > > > > +
> > > > > + ret
> > > > > +
> > > > > +global ASM_PFX(SingleStepStubFunction)
> > > > > +ASM_PFX(SingleStepStubFunction):
> > > > > +;
> > > > > +; we need clean TS bit in CR0 to execute
> > > > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > > > +;
> > > > > + clts
> > > > > + iretd
> > > > > +
> > > > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > > > +ASM_PFX(AsmGetTssTemplateMap):
> > > > > + push ebp ; C prolog
> > > > > + mov ebp, esp
> > > > > + pushad
> > > > > +
> > > > > + mov ebx, dword [ebp + 0x8]
> > > > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > > > AsmExceptionEntryBegin)
> > > > > / 32
> > > > > + mov dword [ebx + 0x8], 0
> > > > > +
> > > > > + popad
> > > > > + pop ebp
> > > > > + ret
> > > > > +
> > > > > diff --git
> > > > >
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > index 75443288a9..4c0d435136 100644
> > > > > ---
> > > > >
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > +++
> > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > > index d70a99c100..e5c03c16c9 100644
> > > > > ---
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > > index 634ffcb21d..56b875b7c8 100644
> > > > > ---
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > diff --git
> > > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > index 65f0cff680..214aafcc13 100644
> > > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > +++
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > > > SystemContext.SystemContextX64->ExceptionData =
> > > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > > }
> > > > >
> > > > > +/**
> > > > > + Setup separate stack for given exceptions.
> > > > > +
> > > > > + @param[in] StackSwitchData Pointer to data required for
> > setuping up
> > > > > + stack switch.
> > > > > +
> > > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > > + initialized.
> > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > > content.
> > > > > +
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +ArchSetupExcpetionStack (
> > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > + )
> > > > > +{
> > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > + IA32_DESCRIPTOR Idtr;
> > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > + UINTN StackTop;
> > > > > + UINTN Index;
> > > > > + UINTN TssBase;
> > > > > + UINTN GdtSize;
> > > > > +
> > > > > + if (StackSwitchData == NULL ||
> > > > > + StackSwitchData->StackTop == 0 ||
> > > > > + StackSwitchData->StackSize == 0 ||
> > > > > + StackSwitchData->Exceptions == NULL ||
> > > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > > + StackSwitchData->GdtTable == NULL ||
> > > > > + StackSwitchData->IdtTable == NULL ||
> > > > > + StackSwitchData->TssDesc == NULL ||
> > > > > + StackSwitchData->Tss == NULL) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // The caller is responsible for that the GDT table, no matter the
> existing
> > > > > + // one or newly allocated, has enough space to hold descriptors for
> > > > exception
> > > > > + // task-state segments.
> > > > > + //
> > > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> > 1)) !=
> > > 0)
> > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc <
> > > > (UINTN)(StackSwitchData->GdtTable))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > > StackSwitchData->GdtSize))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Initialize new GDT table and/or IDT table, if any
> > > > > + //
> > > > > + AsmReadIdtr (&Idtr);
> > > > > + AsmReadGdtr (&Gdtr);
> > > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit
> > +
> > > > 1);
> > > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Fixup current task descriptor. Task-state segment for current task
> will
> > > > > + // be filled by processor during task switching.
> > > > > + //
> > > > > + TssDesc = StackSwitchData->TssDesc;
> > > > > + Tss = StackSwitchData->Tss;
> > > > > +
> > > > > + TssBase = (UINTN)Tss;
> > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > + TssDesc->Bits.P = 1;
> > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > > > +
> > > > > + //
> > > > > + // Fixup exception task descriptor and task-state segment
> > > > > + //
> > > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > > + IdtTable = StackSwitchData->IdtTable;
> > > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > > + //
> > > > > + // Fixup IST
> > > > > + //
> > > > > + Tss->IST[Index] = StackTop;
> > > > > + StackTop -= StackSwitchData->StackSize;
> > > > > +
> > > > > + //
> > > > > + // Set the IST field to enable corresponding IST
> > > > > + //
> > > > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > > > (UINT8)(Index + 1);
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Publish GDT
> > > > > + //
> > > > > + AsmWriteGdtr (&Gdtr);
> > > > > +
> > > > > + //
> > > > > + // Load current task
> > > > > + //
> > > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > > +
> > > > > + //
> > > > > + // Publish IDT
> > > > > + //
> > > > > + AsmWriteIdtr (&Idtr);
> > > > > +
> > > > > + return EFI_SUCCESS;
> > > > > +}
> > > > > +
> > > > > /**
> > > > > Display CPU information.
> > > > >
> > > > > diff --git
> > > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > index 906480134a..c88be46286 100644
> > > > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > @@ -43,4 +43,7 @@ typedef struct {
> > > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > > } RESERVED_VECTORS_DATA;
> > > > >
> > > > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > > > +
> > > > > #endif
> > > > > --
> > > > > 2.14.1.windows.1
> > > >
> > > > _______________________________________________
> > > > edk2-devel mailing list
> > > > edk2-devel@lists.01.org
> > > > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* 答复: [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
2017-11-23 5:06 ` Wang, Jian J
@ 2017-11-25 13:17 ` Fan Jeff
2017-11-27 2:20 ` Wang, Jian J
0 siblings, 1 reply; 35+ messages in thread
From: Fan Jeff @ 2017-11-25 13:17 UTC (permalink / raw)
To: Wang, Jian J, Yao, Jiewen, edk2-devel@lists.01.org; +Cc: Dong, Eric, Zeng, Star
Hi,
I am not sure if this is good idea to define such arch specific definitions in MdeModulePkg. Moreover, we don’t know how ARM or other processors define this definition, either.
Jeff
________________________________
From: edk2-devel <edk2-devel-bounces@lists.01.org> on behalf of Wang, Jian J <jian.j.wang@intel.com>
Sent: Thursday, November 23, 2017 1:06:53 PM
To: Yao, Jiewen; edk2-devel@lists.01.org
Cc: Dong, Eric; Zeng, Star
Subject: Re: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
Good idea. I think it should be defined in also in following file besides the new API
MdeModulePkg\Include\Library\CpuExceptionHandlerLib.h
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 12:08 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: RE: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h:
> Add a new API
>
> Hi
> I am a little worried about the way to use VOID * to pass arch dependent data.
>
> Can we define it clearly in each ARCH in the header file, and use a UNION to
> include all arch?
>
> I think both the caller and the callee need parse it. As such, VOID * is not a good
> way.
>
> Thank you
> Yao Jiewen
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian
> J
> > Wang
> > Sent: Wednesday, November 22, 2017 4:46 PM
> > To: edk2-devel@lists.01.org
> > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Zeng, Star <star.zeng@intel.com>
> > Subject: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h:
> Add
> > a new API
> >
> > > v2:
> > > Add prototype definition of InitializeCpuExceptionStackSwitchHandlers()
> >
> > A new API InitializeCpuExceptionStackSwitchHandlers() is introduced to
> support
> > initializing exception handlers being able to switch stack. StackSwitchData is
> > arch dependent and required by IA32 processor to convey resources reserved
> in
> > advance. This is necessary because the CpuExceptionHandlerLib will be linked
> > in different phases, in which there's no common way to reserve resources.
> >
> > EFI_STATUS
> > EFIAPI
> > InitializeCpuExceptionStackSwitchHandlers (
> > IN VOID *StackSwitchData OPTIONAL
> > );
> >
> > Cc: Star Zeng <star.zeng@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > ---
> > MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h | 18
> > ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > index 6cd8230127..68de4850e1 100644
> > --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > @@ -41,6 +41,24 @@ InitializeCpuExceptionHandlers (
> > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > );
> >
> > +/**
> > + Setup separate stack for given exceptions. StackSwitchData is optional and
> its
> > + content depends one the specific arch of CPU.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping up
> > + stack switch.
> > +
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +InitializeCpuExceptionStackSwitchHandlers (
> > + IN VOID *StackSwitchData OPTIONAL
> > + );
> > +
> > /**
> > Initializes all CPU interrupt/exceptions entries and provides the default
> > interrupt/exception handlers.
> >
> > --
> > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* 答复: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 6:43 ` Wang, Jian J
@ 2017-11-25 13:27 ` Fan Jeff
2017-11-27 2:21 ` Wang, Jian J
2017-11-28 1:38 ` Wang, Jian J
1 sibling, 1 reply; 35+ messages in thread
From: Fan Jeff @ 2017-11-25 13:27 UTC (permalink / raw)
To: Wang, Jian J, Yao, Jiewen, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
Hi,
About 1.1), I agree with Jiewen’s suggestion. Besides it, we also need to provide dummy function of InitializeCpuExceptionStackSwitchHandlers() in NULL instance in MdeModulePkg/Library/CpuExceptionHandlerLibNull.
But we need to think about the return status carefully. For example, if return EFI_UNSUPPORTED in Pei/SMM instrance, we need to update public header file to add this return type.
Jeff
________________________________
From: edk2-devel <edk2-devel-bounces@lists.01.org> on behalf of Wang, Jian J <jian.j.wang@intel.com>
Sent: Thursday, November 23, 2017 2:43:44 PM
To: Yao, Jiewen; edk2-devel@lists.01.org
Cc: Kinney, Michael D; Dong, Eric; Zeng, Star
Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
1.1) Got your point. I'll add dummy function in this patch.
1.2) Yep, we're on the same page.
1.3) Here's my opinion:
Actually almost all MP code has such assumption: any AP configuration will copy
from BSP. If we allow AP to call InitializeCpuExceptionHandlers(), we have to do a lot
of other changes than just updating InitializeCpuExceptionHandlers(). If so, it may
be premature to figure out a solution at this patch.
In addition, CpuDxe actually calls InitializeCpuInterruptHandlers() which covers the
functionalities of InitializeCpuExceptionHandlers() (its settings will be overwritten).
If we want AP to initialize interrupt and exception individually, maybe we should
let AP call InitializeCpuInterruptHandlers() instead.
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 2:16 PM
> To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Here is my thought for 1)
>
> 1.1) We must provide the InitializeCpuExceptionStackSwitchHandlers()
> implementation in Pei instance and Smm instance.
>
> The basic requirement is a library instance must provide symbol for functions
> declared in header file.
> It is ok to return unsupported. But we MUST provide the symbol.
>
> 1.2) For SMM, I think our ultimate goal is to remove SMM specific stack guard,
> and use the common one. Duplicating code is completely unnecessary, and it is
> easy to introduce bug. And unfortunately, we already have bug in existing SMM
> exception handler. -- That is a good reason to remove duplication.
>
> Again, it is not necessary to do it in this patch. I am totally OK to do it in another
> patch.
>
> 1.3) For PEI, I do not think we can use current way to allocate stack in data
> section, because it might be readonly in pre-mem phase. We must use some
> other way.
>
> 1.4) I believe this patch has a hidden assumption is that:
> InitializeCpuExceptionHandlers() won't be called by multiple APs.
> If 2 or more APs call the it at same time, it might be broken because you use
> mNewStack for all the callers....
> Is that right?
>
>
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Thursday, November 23, 2017 2:06 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Kinney,
> > Michael D <michael.d.kinney@intel.com>
> > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch support
> >
> >
> >
> > > -----Original Message-----
> > > From: Yao, Jiewen
> > > Sent: Thursday, November 23, 2017 1:50 PM
> > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > > Kinney, Michael D <michael.d.kinney@intel.com>
> > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch support
> > >
> > > Some thought:
> > >
> > > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented
> in
> > > DxeException.c.
> > > What about Pei/Smm instance?
> > >
> > > I think it is OK to not implement it at this moment. But we need make sure no
> > > architecture issue if we want to enable it some time later.
> > >
> > Like what we discussed before, this series of patch is for Stack Guard feature
> > which
> > is only available for DXE (because Stack Guard needs paging to work). Stack
> > switch
> > is enabled for the sake of Stack Guard feature. So I think it's enough to
> > implement
> > it in DxeException.c. In addition, SMM has its own implementation of stack
> guard
> > and stack switch. It's not necessary to do it again.
> >
> > I agree with you that we should merge those common code but I think we
> should
> > do
> > it in a separate patch series since it's not Stack Guard relevant. And I've
> removed
> > all architecture issues I can think of. Current stack switch initialization should
> work
> > for both PEI and SMM as well.
> >
> > > 2) #define IA32_GDT_TYPE_TSS 0x9
> > > This is generic, can we move to BaseLib.h?
> > >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > >
> > > > -----Original Message-----
> > > > From: Wang, Jian J
> > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > To: edk2-devel@lists.01.org
> > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Yao,
> > > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > > <michael.d.kinney@intel.com>
> > > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch
> > > > support
> > > >
> > > > > v2:
> > > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to
> > setup
> > > > stack
> > > > > switch. This can avoid allocating memory for it in this library.
> > > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > > phase of DXE core.
> > > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > > support
> > > > > memory allocation because those memory can passed in by
> > parameter
> > > > now.
> > > > > e. Remove the nasm macro to define exception handler one by one
> > and
> > > > add a
> > > > > function to return the start address of each handler.
> > > >
> > > > If Stack Guard is enabled and there's really a stack overflow happened
> during
> > > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > > usage, the exception handler, which shares the stack with normal UEFI
> driver,
> > > > cannot be executed and cannot dump the processor information.
> > > >
> > > > Without those information, it's very difficult for the BIOS developers locate
> > > > the root cause of stack overflow. And without a workable stack, the
> > developer
> > > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > > >
> > > > In order to make sure the exception handler to execute normally after
> stack
> > > > overflow. We need separate stacks for exception handlers in case of
> unusable
> > > > stack.
> > > >
> > > > IA processor allows to switch to a new stack during handling interrupt and
> > > > exception. But X64 and IA32 provides different ways to make it. X64
> provides
> > > > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > > > new stack for its handler. IA32 doesn't have IST mechanism and can only
> use
> > > > task gate to do it since task switch allows to load a new stack through its
> > > > task-state segment (TSS).
> > > >
> > > > Cc: Star Zeng <star.zeng@intel.com>
> > > > Cc: Eric Dong <eric.dong@intel.com>
> > > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > > ---
> > > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > > +++++++++++++++++++++
> > > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > > create mode 100644
> > > >
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > index 740a58828b..30334105d2 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > @@ -48,6 +48,32 @@
> > > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c,
> > > 0x83 }
> > > > \
> > > > }
> > > >
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > > +
> > > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > > CPU_TSS_SIZE)
> > > > +
> > > > +#define IA32_GDT_TYPE_TSS 0x9
> > > > +#define IA32_GDT_ALIGNMENT 8
> > > > +
> > > > +typedef struct {
> > > > + UINTN StackTop;
> > > > + UINTN StackSize;
> > > > + UINT8 *Exceptions;
> > > > + UINTN ExceptionNumber;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > + UINTN GdtSize;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > +
> > > > //
> > > > // Record exception handler information
> > > > //
> > > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > > );
> > > >
> > > > +/**
> > > > + Setup separate stack for specific exceptions.
> > > > +
> > > > + @param[in] IdtTable IDT table base.
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + );
> > > > +
> > > > +/**
> > > > + Return address map of exception handler template so that C code can
> > > > generate
> > > > + exception tables. The template is only for exceptions using task gate
> > instead
> > > > + of interrupt gate.
> > > > +
> > > > + @param AddressMap Pointer to a buffer where the address map is
> > > > returned.
> > > > +**/
> > > > +VOID
> > > > +EFIAPI
> > > > +AsmGetTssTemplateMap (
> > > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > > + );
> > > > +
> > > > #endif
> > > >
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > index f4a8d01c80..58e55a8a2e 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > @@ -47,6 +48,11 @@
> > > > PeiDxeSmmCpuException.c
> > > > DxeException.c
> > > >
> > > > +[Pcd]
> > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > +
> > > > [Packages]
> > > > MdePkg/MdePkg.dec
> > > > MdeModulePkg/MdeModulePkg.dec
> > > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > index 31febec976..c0b2c615aa 100644
> > > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > @@ -25,6 +25,10 @@ UINTN
> > mEnabledInterruptNum =
> > > > 0;
> > > >
> > > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > > >
> > > > +UINT8
> > > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > > +
> > CPU_KNOWN_GOOD_STACK_SIZE]
> > > > = {0};
> > > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > > +
> > > > /**
> > > > Common exception handler.
> > > >
> > > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > > )
> > > > {
> > > > + EFI_STATUS Status;
> > > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > +
> > > > mExceptionHandlerData.ReservedVectors =
> > > > mReservedVectorsData;
> > > > mExceptionHandlerData.ExternalInterruptHandler =
> > > > mExternalInterruptHandlerTable;
> > > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > +
> > > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > > + StackSwitchData.ExceptionNumber =
> > > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> > *)mNewGdt;
> > > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > > Gdtr.Limit + 1);
> > > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > > Gdtr.Limit + 1 +
> > > > +
> > > > CPU_TSS_DESC_SIZE);
> > > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > > + &StackSwitchData
> > > > + );
> > > > + }
> > > > + return Status;
> > > > }
> > > >
> > > > /**
> > > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > > {
> > > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > InterruptHandler,
> > > > &mExceptionHandlerData);
> > > > }
> > > > +
> > > > +/**
> > > > + Setup separate stack for given exceptions. This is required by
> > > > + PcdCpuStackGuard feature.
> > > > +
> > > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +InitializeCpuExceptionStackSwitchHandlers (
> > > > + IN VOID *StackSwitchData OPTIONAL
> > > > + )
> > > > +{
> > > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > > +}
> > > > diff --git
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > index f2c39eb193..0aaf794795 100644
> > > > ---
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > +++
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextIa32->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for
> > setuping
> > > > up
> > > > + stack switch.
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN Vector;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > >GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > > + (StackSwitchData->ExceptionNumber + 1);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + AsmGetTssTemplateMap (&TemplateMap);
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + TssDesc += 1;
> > > > + Tss += 1;
> > > > +
> > > > + //
> > > > + // Fixup TSS descriptor
> > > > + //
> > > > + TssBase = (UINTN)Tss;
> > > > +
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup TSS
> > > > + //
> > > > + Vector = StackSwitchData->Exceptions[Index];
> > > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > > + + Vector *
> > > > TemplateMap.ExceptionStubHeaderSize);
> > > > + Tss->EFLAGS = 0x2;
> > > > + Tss->ESP = StackTop;
> > > > + Tss->CR3 = AsmReadCr3 ();
> > > > + Tss->ES = AsmReadEs ();
> > > > + Tss->CS = AsmReadCs ();
> > > > + Tss->SS = AsmReadSs ();
> > > > + Tss->DS = AsmReadDs ();
> > > > + Tss->FS = AsmReadFs ();
> > > > + Tss->GS = AsmReadGs ();
> > > > +
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Update IDT to use Task Gate for given exception
> > > > + //
> > > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> > Gdtr.Base);
> > > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display processor context.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > index a8d3556a80..d9ded5977f 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > @@ -41,4 +41,12 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE \
> > > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > +#define CPU_TSS_SIZE \
> > > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > #endif
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > new file mode 100644
> > > > index 0000000000..62bcedea1a
> > > > --- /dev/null
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > @@ -0,0 +1,398 @@
> > > > +;------------------------------------------------------------------------------ ;
> > > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > > +; This program and the accompanying materials
> > > > +; are licensed and made available under the terms and conditions of the
> BSD
> > > > License
> > > > +; which accompanies this distribution. The full text of the license may be
> > > found
> > > > at
> > > > +; http://opensource.org/licenses/bsd-license.php.
> > > > +;
> > > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > > BASIS,
> > > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > > EXPRESS
> > > > OR IMPLIED.
> > > > +;
> > > > +; Module Name:
> > > > +;
> > > > +; ExceptionTssEntryAsm.Asm
> > > > +;
> > > > +; Abstract:
> > > > +;
> > > > +; IA32 CPU Exception Handler with Separate Stack
> > > > +;
> > > > +; Notes:
> > > > +;
> > > > +;------------------------------------------------------------------------------
> > > > +
> > > > +;
> > > > +; IA32 TSS Memory Layout Description
> > > > +;
> > > > +struc IA32_TSS
> > > > + resw 1
> > > > + resw 1
> > > > + .ESP0: resd 1
> > > > + .SS0: resw 1
> > > > + resw 1
> > > > + .ESP1: resd 1
> > > > + .SS1: resw 1
> > > > + resw 1
> > > > + .ESP2: resd 1
> > > > + .SS2: resw 1
> > > > + resw 1
> > > > + ._CR3: resd 1
> > > > + .EIP: resd 1
> > > > + .EFLAGS: resd 1
> > > > + ._EAX: resd 1
> > > > + ._ECX: resd 1
> > > > + ._EDX: resd 1
> > > > + ._EBX: resd 1
> > > > + ._ESP: resd 1
> > > > + ._EBP: resd 1
> > > > + ._ESI: resd 1
> > > > + ._EDI: resd 1
> > > > + ._ES: resw 1
> > > > + resw 1
> > > > + ._CS: resw 1
> > > > + resw 1
> > > > + ._SS: resw 1
> > > > + resw 1
> > > > + ._DS: resw 1
> > > > + resw 1
> > > > + ._FS: resw 1
> > > > + resw 1
> > > > + ._GS: resw 1
> > > > + resw 1
> > > > + .LDT: resw 1
> > > > + resw 1
> > > > + resw 1
> > > > + resw 1
> > > > +endstruc
> > > > +
> > > > +;
> > > > +; CommonExceptionHandler()
> > > > +;
> > > > +extern ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +SECTION .data
> > > > +
> > > > +SECTION .text
> > > > +
> > > > +ALIGN 8
> > > > +
> > > > +;
> > > > +; Exception handler stub table
> > > > +;
> > > > +AsmExceptionEntryBegin:
> > > > +%assign Vector 0
> > > > +%rep 32
> > > > +
> > > > +DoIret%[Vector]:
> > > > + iretd
> > > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > > + db 0x6a ; push #VectorNum
> > > > + db %[Vector]
> > > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > + call eax
> > > > + mov esp, eax ; Restore stack top
> > > > + jmp DoIret%[Vector]
> > > > +
> > > > +%assign Vector Vector+1
> > > > +%endrep
> > > > +AsmExceptionEntryEnd:
> > > > +
> > > > +;
> > > > +; Common part of exception handler
> > > > +;
> > > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > > + ;
> > > > + ; Stack:
> > > > + ; +---------------------+ <-- EBP - 8
> > > > + ; + TSS Base +
> > > > + ; +---------------------+ <-- EBP - 4
> > > > + ; + CPUID.EDX +
> > > > + ; +---------------------+ <-- EBP
> > > > + ; + EIP +
> > > > + ; +---------------------+ <-- EBP + 4
> > > > + ; + Vector Number +
> > > > + ; +---------------------+ <-- EBP + 8
> > > > + ; + Error Code +
> > > > + ; +---------------------+
> > > > + ;
> > > > +
> > > > + mov ebp, esp ; Stack frame
> > > > +
> > > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > > + mov eax, 1
> > > > + cpuid
> > > > + push edx
> > > > +
> > > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > > +; current TSS base
> > > > + sub esp, 8
> > > > + sgdt [esp + 2]
> > > > + mov eax, [esp + 4] ; GDT base
> > > > + add esp, 8
> > > > +
> > > > + xor ebx, ebx
> > > > + str bx ; Current TR
> > > > +
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Current TSS base
> > > > + push ecx ; keep it in stack for later use
> > > > +
> > > > + movzx ebx, word [ecx] ; Previous Task Link
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Previous TSS base
> > > > +
> > > > +;
> > > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > > EFI_SYSTEM_CONTEXT_IA32
> > > > +; is 16-byte aligned
> > > > +;
> > > > + and esp, 0xfffffff0
> > > > + sub esp, 12
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + push dword [ecx + IA32_TSS._EAX]
> > > > + push dword [ecx + IA32_TSS._ECX]
> > > > + push dword [ecx + IA32_TSS._EDX]
> > > > + push dword [ecx + IA32_TSS._EBX]
> > > > + push dword [ecx + IA32_TSS._ESP]
> > > > + push dword [ecx + IA32_TSS._EBP]
> > > > + push dword [ecx + IA32_TSS._ESI]
> > > > + push dword [ecx + IA32_TSS._EDI]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > > + push eax
> > > > +
> > > > +;; UINT32 Eip;
> > > > + push dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > + sub esp, 8
> > > > + sidt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > + sub esp, 8
> > > > + sgdt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > > + push eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + mov eax, cr4
> > > > + push eax ; push cr4 firstly
> > > > +
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .1
> > > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > > +.1:
> > > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > > + jz .2
> > > > + or eax, BIT3 ; Set CR4.DE
> > > > +.2:
> > > > + mov cr4, eax
> > > > +
> > > > + mov eax, cr3
> > > > + push eax
> > > > + mov eax, cr2
> > > > + push eax
> > > > + xor eax, eax
> > > > + push eax
> > > > + mov eax, cr0
> > > > + push eax
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > + mov eax, dr7
> > > > + push eax
> > > > + mov eax, dr6
> > > > + push eax
> > > > + mov eax, dr3
> > > > + push eax
> > > > + mov eax, dr2
> > > > + push eax
> > > > + mov eax, dr1
> > > > + push eax
> > > > + mov eax, dr0
> > > > + push eax
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > > +;; when executing fxsave/fxrstor instruction
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > > + ; edx still contains result from CPUID above
> > > > + jz .3
> > > > + clts
> > > > + sub esp, 512
> > > > + mov edi, esp
> > > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > > +.3:
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + push dword [ebp + 8]
> > > > +
> > > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is
> > > clear
> > > > + cld
> > > > +
> > > > +;; call into exception handler
> > > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +;; Prepare parameter and call
> > > > + mov edx, esp
> > > > + push edx ; EFI_SYSTEM_CONTEXT
> > > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > > > +
> > > > + ;
> > > > + ; Call External Exception Handler
> > > > + ;
> > > > + call eax
> > > > + add esp, 8 ; Restore stack before calling
> > > > + mov ecx, esi ; Restore TSS base
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + add esp, 4
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .4
> > > > + mov esi, esp
> > > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > > +.4:
> > > > + add esp, 512
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > +;; Skip restoration of DRx registers to support debuggers
> > > > +;; that set breakpoints in interrupt/exception context
> > > > + add esp, 4 * 6
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + pop eax
> > > > + mov cr0, eax
> > > > + add esp, 4 ; not for Cr1
> > > > + pop eax
> > > > + mov cr2, eax
> > > > + pop eax
> > > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > > + pop eax
> > > > + mov cr4, eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + btr ebx, 9 ; Do 'cli'
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > +;; Best not let anyone mess with these particular registers...
> > > > + add esp, 24
> > > > +
> > > > +;; UINT32 Eip;
> > > > + pop dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > +;; NOTE - modified segment registers could hang the debugger... We
> > > > +;; could attempt to insulate ourselves against this possibility,
> > > > +;; but that poses risks as well.
> > > > +;;
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + pop dword [ecx + IA32_TSS._EDI]
> > > > + pop dword [ecx + IA32_TSS._ESI]
> > > > + add esp, 4 ; not for ebp
> > > > + add esp, 4 ; not for esp
> > > > + pop dword [ecx + IA32_TSS._EBX]
> > > > + pop dword [ecx + IA32_TSS._EDX]
> > > > + pop dword [ecx + IA32_TSS._ECX]
> > > > + pop dword [ecx + IA32_TSS._EAX]
> > > > +
> > > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > > +; where the exception is triggered.
> > > > +
> > > > +;; Create return context for iretd in stub function
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > > + mov [eax - 0xc], ebx ; create EIP in old
> > stack
> > > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > > + mov [eax - 0x8], ebx ; create CS in old stack
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + bts ebx, 8
> > > > + mov [eax - 0x4], ebx ; create eflags in old
> > stack
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old
> > TSS
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > + sub eax, 0xc ; minus 12 byte
> > > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> > pointer
> > > > +
> > > > +;; Replace the EIP of interrupted task with stub function
> > > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > > +
> > > > + mov ecx, [ebp - 8] ; Get current TSS base
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack
> > top
> > > > + mov esp, ebp
> > > > +
> > > > + ret
> > > > +
> > > > +global ASM_PFX(SingleStepStubFunction)
> > > > +ASM_PFX(SingleStepStubFunction):
> > > > +;
> > > > +; we need clean TS bit in CR0 to execute
> > > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > > +;
> > > > + clts
> > > > + iretd
> > > > +
> > > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > > +ASM_PFX(AsmGetTssTemplateMap):
> > > > + push ebp ; C prolog
> > > > + mov ebp, esp
> > > > + pushad
> > > > +
> > > > + mov ebx, dword [ebp + 0x8]
> > > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > AsmExceptionEntryBegin)
> > > > / 32
> > > > + mov dword [ebx + 0x8], 0
> > > > +
> > > > + popad
> > > > + pop ebp
> > > > + ret
> > > > +
> > > > diff --git
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > index 75443288a9..4c0d435136 100644
> > > > ---
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > index d70a99c100..e5c03c16c9 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > index 634ffcb21d..56b875b7c8 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > index 65f0cff680..214aafcc13 100644
> > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextX64->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > >GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + //
> > > > + // Fixup IST
> > > > + //
> > > > + Tss->IST[Index] = StackTop;
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Set the IST field to enable corresponding IST
> > > > + //
> > > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > > (UINT8)(Index + 1);
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display CPU information.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > index 906480134a..c88be46286 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > @@ -43,4 +43,7 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > > +
> > > > #endif
> > > > --
> > > > 2.14.1.windows.1
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* 答复: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-22 8:45 ` [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support Jian J Wang
2017-11-23 5:50 ` Yao, Jiewen
@ 2017-11-25 13:35 ` Fan Jeff
1 sibling, 0 replies; 35+ messages in thread
From: Fan Jeff @ 2017-11-25 13:35 UTC (permalink / raw)
To: Jian J Wang, edk2-devel@lists.01.org
Cc: Michael Kinney, Jiewen Yao, Eric Dong, Star Zeng
Jian,
EFIAPI is not required for ArchSetupExcpetionStack().
Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
Jeff
________________________________
From: edk2-devel <edk2-devel-bounces@lists.01.org> on behalf of Jian J Wang <jian.j.wang@intel.com>
Sent: Wednesday, November 22, 2017 4:45:47 PM
To: edk2-devel@lists.01.org
Cc: Michael Kinney; Jiewen Yao; Eric Dong; Star Zeng
Subject: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
> v2:
> a. Move common TSS structure and API definitions to BaseLib.h
> b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to setup stack
> switch. This can avoid allocating memory for it in this library.
> c. Add globals to reserve memory for stack switch initialized in early
> phase of DXE core.
> d. Remove the filter code used to exclude boot modes which doesn't support
> memory allocation because those memory can passed in by parameter now.
> e. Remove the nasm macro to define exception handler one by one and add a
> function to return the start address of each handler.
If Stack Guard is enabled and there's really a stack overflow happened during
boot, a Page Fault exception will be triggered. Because the stack is out of
usage, the exception handler, which shares the stack with normal UEFI driver,
cannot be executed and cannot dump the processor information.
Without those information, it's very difficult for the BIOS developers locate
the root cause of stack overflow. And without a workable stack, the developer
cannot event use single step to debug the UEFI driver with JTAG debugger.
In order to make sure the exception handler to execute normally after stack
overflow. We need separate stacks for exception handlers in case of unusable
stack.
IA processor allows to switch to a new stack during handling interrupt and
exception. But X64 and IA32 provides different ways to make it. X64 provides
interrupt stack table (IST) to allow maximum 7 different exceptions to have
new stack for its handler. IA32 doesn't have IST mechanism and can only use
task gate to do it since task switch allows to load a new stack through its
task-state segment (TSS).
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
---
.../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
.../DxeCpuExceptionHandlerLib.inf | 6 +
.../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
.../Ia32/ArchExceptionHandler.c | 167 +++++++++
.../Ia32/ArchInterruptDefs.h | 8 +
.../Ia32/ExceptionTssEntryAsm.nasm | 398 +++++++++++++++++++++
.../PeiCpuExceptionHandlerLib.inf | 1 +
.../SecPeiCpuExceptionHandlerLib.inf | 1 +
.../SmmCpuExceptionHandlerLib.inf | 1 +
.../X64/ArchExceptionHandler.c | 133 +++++++
.../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
11 files changed, 820 insertions(+), 1 deletion(-)
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 740a58828b..30334105d2 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -48,6 +48,32 @@
0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c, 0x83 } \
}
+#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
+ FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
+
+#define CPU_STACK_SWITCH_EXCEPTION_LIST \
+ FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
+
+#define CPU_KNOWN_GOOD_STACK_SIZE \
+ FixedPcdGet32 (PcdCpuKnownGoodStackSize)
+
+#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)
+
+#define IA32_GDT_TYPE_TSS 0x9
+#define IA32_GDT_ALIGNMENT 8
+
+typedef struct {
+ UINTN StackTop;
+ UINTN StackSize;
+ UINT8 *Exceptions;
+ UINTN ExceptionNumber;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_SEGMENT_DESCRIPTOR *GdtTable;
+ UINTN GdtSize;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+} EXCEPTION_STACK_SWITCH_DATA;
+
//
// Record exception handler information
//
@@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
);
+/**
+ Setup separate stack for specific exceptions.
+
+ @param[in] IdtTable IDT table base.
+**/
+EFI_STATUS
+EFIAPI
+ArchSetupExcpetionStack (
+ IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
+ );
+
+/**
+ Return address map of exception handler template so that C code can generate
+ exception tables. The template is only for exceptions using task gate instead
+ of interrupt gate.
+
+ @param AddressMap Pointer to a buffer where the address map is returned.
+**/
+VOID
+EFIAPI
+AsmGetTssTemplateMap (
+ OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+ );
+
#endif
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index f4a8d01c80..58e55a8a2e 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
@@ -47,6 +48,11 @@
PeiDxeSmmCpuException.c
DxeException.c
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index 31febec976..c0b2c615aa 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -25,6 +25,10 @@ UINTN mEnabledInterruptNum = 0;
EXCEPTION_HANDLER_DATA mExceptionHandlerData;
+UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
+ CPU_KNOWN_GOOD_STACK_SIZE] = {0};
+UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
+
/**
Common exception handler.
@@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
+ EFI_STATUS Status;
+ EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
+ IA32_DESCRIPTOR Idtr;
+ IA32_DESCRIPTOR Gdtr;
+
mExceptionHandlerData.ReservedVectors = mReservedVectorsData;
mExceptionHandlerData.ExternalInterruptHandler = mExternalInterruptHandlerTable;
InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
- return InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData);
+ Status = InitializeCpuExceptionHandlersWorker (VectorInfo, &mExceptionHandlerData);
+ if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
+ AsmReadIdtr (&Idtr);
+ AsmReadGdtr (&Gdtr);
+
+ StackSwitchData.StackTop = (UINTN)mNewStack;
+ StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
+ StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
+ StackSwitchData.ExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;
+ StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
+ StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR *)mNewGdt;
+ StackSwitchData.GdtSize = sizeof (mNewGdt);
+ StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt + Gdtr.Limit + 1);
+ StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt + Gdtr.Limit + 1 +
+ CPU_TSS_DESC_SIZE);
+ Status = InitializeCpuExceptionStackSwitchHandlers (
+ &StackSwitchData
+ );
+ }
+ return Status;
}
/**
@@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
{
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);
}
+
+/**
+ Setup separate stack for given exceptions. This is required by
+ PcdCpuStackGuard feature.
+
+ Note: For IA32 processor, StackSwitchData is a required parameter.
+
+ @param[in] StackSwitchData Pointer to data required for setuping up
+ stack switch.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionStackSwitchHandlers (
+ IN VOID *StackSwitchData OPTIONAL
+ )
+{
+ return ArchSetupExcpetionStack (StackSwitchData);
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index f2c39eb193..0aaf794795 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
SystemContext.SystemContextIa32->ExceptionData = ReservedVectors[ExceptionType].ExceptionData;
}
+/**
+ Setup separate stack for given exceptions.
+
+ @param[in] StackSwitchData Pointer to data required for setuping up
+ stack switch.
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.
+
+**/
+EFI_STATUS
+EFIAPI
+ArchSetupExcpetionStack (
+ IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
+ )
+{
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+ UINTN StackTop;
+ UINTN Index;
+ UINTN Vector;
+ UINTN TssBase;
+ UINTN GdtSize;
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
+
+ if (StackSwitchData == NULL ||
+ StackSwitchData->StackTop == 0 ||
+ StackSwitchData->StackSize == 0 ||
+ StackSwitchData->Exceptions == NULL ||
+ StackSwitchData->ExceptionNumber == 0 ||
+ StackSwitchData->GdtTable == NULL ||
+ StackSwitchData->IdtTable == NULL ||
+ StackSwitchData->TssDesc == NULL ||
+ StackSwitchData->Tss == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // The caller is responsible for that the GDT table, no matter the existing
+ // one or newly allocated, has enough space to hold descriptors for exception
+ // task-state segments.
+ //
+ if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc >=
+ ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GdtSize = (UINTN)StackSwitchData->TssDesc -
+ (UINTN)(StackSwitchData->GdtTable) +
+ sizeof (IA32_TSS_DESCRIPTOR) *
+ (StackSwitchData->ExceptionNumber + 1);
+ if (GdtSize > StackSwitchData->GdtSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize new GDT table and/or IDT table, if any
+ //
+ AsmReadIdtr (&Idtr);
+ AsmReadGdtr (&Gdtr);
+ if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
+ CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
+ Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
+ Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
+ }
+
+ if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
+ Idtr.Base = (UINTN)StackSwitchData->IdtTable;
+ }
+
+ //
+ // Fixup current task descriptor. Task-state segment for current task will
+ // be filled by processor during task switching.
+ //
+ TssDesc = StackSwitchData->TssDesc;
+ Tss = StackSwitchData->Tss;
+
+ TssBase = (UINTN)Tss;
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
+
+ //
+ // Fixup exception task descriptor and task-state segment
+ //
+ AsmGetTssTemplateMap (&TemplateMap);
+ StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
+ StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
+ IdtTable = StackSwitchData->IdtTable;
+ for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
+ TssDesc += 1;
+ Tss += 1;
+
+ //
+ // Fixup TSS descriptor
+ //
+ TssBase = (UINTN)Tss;
+
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
+
+ //
+ // Fixup TSS
+ //
+ Vector = StackSwitchData->Exceptions[Index];
+ Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
+ + Vector * TemplateMap.ExceptionStubHeaderSize);
+ Tss->EFLAGS = 0x2;
+ Tss->ESP = StackTop;
+ Tss->CR3 = AsmReadCr3 ();
+ Tss->ES = AsmReadEs ();
+ Tss->CS = AsmReadCs ();
+ Tss->SS = AsmReadSs ();
+ Tss->DS = AsmReadDs ();
+ Tss->FS = AsmReadFs ();
+ Tss->GS = AsmReadGs ();
+
+ StackTop -= StackSwitchData->StackSize;
+
+ //
+ // Update IDT to use Task Gate for given exception
+ //
+ IdtTable[Vector].Bits.OffsetLow = 0;
+ IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc - Gdtr.Base);
+ IdtTable[Vector].Bits.Reserved_0 = 0;
+ IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
+ IdtTable[Vector].Bits.OffsetHigh = 0;
+ }
+
+ //
+ // Publish GDT
+ //
+ AsmWriteGdtr (&Gdtr);
+
+ //
+ // Load current task
+ //
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
+
+ //
+ // Publish IDT
+ //
+ AsmWriteIdtr (&Idtr);
+
+ return EFI_SUCCESS;
+}
+
/**
Display processor context.
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
index a8d3556a80..d9ded5977f 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
@@ -41,4 +41,12 @@ typedef struct {
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA;
+#define CPU_TSS_DESC_SIZE \
+ (sizeof (IA32_TSS_DESCRIPTOR) * \
+ (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
+
+#define CPU_TSS_SIZE \
+ (sizeof (IA32_TASK_STATE_SEGMENT) * \
+ (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
+
#endif
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
new file mode 100644
index 0000000000..62bcedea1a
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
@@ -0,0 +1,398 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; ExceptionTssEntryAsm.Asm
+;
+; Abstract:
+;
+; IA32 CPU Exception Handler with Separate Stack
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+;
+; IA32 TSS Memory Layout Description
+;
+struc IA32_TSS
+ resw 1
+ resw 1
+ .ESP0: resd 1
+ .SS0: resw 1
+ resw 1
+ .ESP1: resd 1
+ .SS1: resw 1
+ resw 1
+ .ESP2: resd 1
+ .SS2: resw 1
+ resw 1
+ ._CR3: resd 1
+ .EIP: resd 1
+ .EFLAGS: resd 1
+ ._EAX: resd 1
+ ._ECX: resd 1
+ ._EDX: resd 1
+ ._EBX: resd 1
+ ._ESP: resd 1
+ ._EBP: resd 1
+ ._ESI: resd 1
+ ._EDI: resd 1
+ ._ES: resw 1
+ resw 1
+ ._CS: resw 1
+ resw 1
+ ._SS: resw 1
+ resw 1
+ ._DS: resw 1
+ resw 1
+ ._FS: resw 1
+ resw 1
+ ._GS: resw 1
+ resw 1
+ .LDT: resw 1
+ resw 1
+ resw 1
+ resw 1
+endstruc
+
+;
+; CommonExceptionHandler()
+;
+extern ASM_PFX(CommonExceptionHandler)
+
+SECTION .data
+
+SECTION .text
+
+ALIGN 8
+
+;
+; Exception handler stub table
+;
+AsmExceptionEntryBegin:
+%assign Vector 0
+%rep 32
+
+DoIret%[Vector]:
+ iretd
+ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
+ db 0x6a ; push #VectorNum
+ db %[Vector]
+ mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
+ call eax
+ mov esp, eax ; Restore stack top
+ jmp DoIret%[Vector]
+
+%assign Vector Vector+1
+%endrep
+AsmExceptionEntryEnd:
+
+;
+; Common part of exception handler
+;
+global ASM_PFX(CommonTaskSwtichEntryPoint)
+ASM_PFX(CommonTaskSwtichEntryPoint):
+ ;
+ ; Stack:
+ ; +---------------------+ <-- EBP - 8
+ ; + TSS Base +
+ ; +---------------------+ <-- EBP - 4
+ ; + CPUID.EDX +
+ ; +---------------------+ <-- EBP
+ ; + EIP +
+ ; +---------------------+ <-- EBP + 4
+ ; + Vector Number +
+ ; +---------------------+ <-- EBP + 8
+ ; + Error Code +
+ ; +---------------------+
+ ;
+
+ mov ebp, esp ; Stack frame
+
+; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
+ mov eax, 1
+ cpuid
+ push edx
+
+; Get TSS base of interrupted task through PreviousTaskLink field in
+; current TSS base
+ sub esp, 8
+ sgdt [esp + 2]
+ mov eax, [esp + 4] ; GDT base
+ add esp, 8
+
+ xor ebx, ebx
+ str bx ; Current TR
+
+ mov ecx, [eax + ebx + 2]
+ shl ecx, 8
+ mov cl, [eax + ebx + 7]
+ ror ecx, 8 ; ecx = Current TSS base
+ push ecx ; keep it in stack for later use
+
+ movzx ebx, word [ecx] ; Previous Task Link
+ mov ecx, [eax + ebx + 2]
+ shl ecx, 8
+ mov cl, [eax + ebx + 7]
+ ror ecx, 8 ; ecx = Previous TSS base
+
+;
+; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
+; is 16-byte aligned
+;
+ and esp, 0xfffffff0
+ sub esp, 12
+
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ push dword [ecx + IA32_TSS._EAX]
+ push dword [ecx + IA32_TSS._ECX]
+ push dword [ecx + IA32_TSS._EDX]
+ push dword [ecx + IA32_TSS._EBX]
+ push dword [ecx + IA32_TSS._ESP]
+ push dword [ecx + IA32_TSS._EBP]
+ push dword [ecx + IA32_TSS._ESI]
+ push dword [ecx + IA32_TSS._EDI]
+
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+ movzx eax, word [ecx + IA32_TSS._SS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._CS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._DS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._ES]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._FS]
+ push eax
+ movzx eax, word [ecx + IA32_TSS._GS]
+ push eax
+
+;; UINT32 Eip;
+ push dword [ecx + IA32_TSS.EIP]
+
+;; UINT32 Gdtr[2], Idtr[2];
+ sub esp, 8
+ sidt [esp]
+ mov eax, [esp + 2]
+ xchg eax, [esp]
+ and eax, 0xFFFF
+ mov [esp+4], eax
+
+ sub esp, 8
+ sgdt [esp]
+ mov eax, [esp + 2]
+ xchg eax, [esp]
+ and eax, 0xFFFF
+ mov [esp+4], eax
+
+;; UINT32 Ldtr, Tr;
+ mov eax, ebx ; ebx still keeps selector of interrupted task
+ push eax
+ movzx eax, word [ecx + IA32_TSS.LDT]
+ push eax
+
+;; UINT32 EFlags;
+ push dword [ecx + IA32_TSS.EFLAGS]
+
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ mov eax, cr4
+ push eax ; push cr4 firstly
+
+ mov edx, [ebp - 4] ; cpuid.edx
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
+ jz .1
+ or eax, BIT9 ; Set CR4.OSFXSR
+.1:
+ test edx, BIT2 ; Test for Debugging Extensions support
+ jz .2
+ or eax, BIT3 ; Set CR4.DE
+.2:
+ mov cr4, eax
+
+ mov eax, cr3
+ push eax
+ mov eax, cr2
+ push eax
+ xor eax, eax
+ push eax
+ mov eax, cr0
+ push eax
+
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+ mov eax, dr7
+ push eax
+ mov eax, dr6
+ push eax
+ mov eax, dr3
+ push eax
+ mov eax, dr2
+ push eax
+ mov eax, dr1
+ push eax
+ mov eax, dr0
+ push eax
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
+;; when executing fxsave/fxrstor instruction
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
+ ; edx still contains result from CPUID above
+ jz .3
+ clts
+ sub esp, 512
+ mov edi, esp
+ db 0xf, 0xae, 0x7 ;fxsave [edi]
+.3:
+
+;; UINT32 ExceptionData;
+ push dword [ebp + 8]
+
+;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
+ cld
+
+;; call into exception handler
+ mov esi, ecx ; Keep TSS base to avoid overwrite
+ mov eax, ASM_PFX(CommonExceptionHandler)
+
+;; Prepare parameter and call
+ mov edx, esp
+ push edx ; EFI_SYSTEM_CONTEXT
+ push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
+
+ ;
+ ; Call External Exception Handler
+ ;
+ call eax
+ add esp, 8 ; Restore stack before calling
+ mov ecx, esi ; Restore TSS base
+
+;; UINT32 ExceptionData;
+ add esp, 4
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+ mov edx, [ebp - 4] ; cpuid.edx
+ test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
+ jz .4
+ mov esi, esp
+ db 0xf, 0xae, 0xe ; fxrstor [esi]
+.4:
+ add esp, 512
+
+;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+;; Skip restoration of DRx registers to support debuggers
+;; that set breakpoints in interrupt/exception context
+ add esp, 4 * 6
+
+;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
+ pop eax
+ mov cr0, eax
+ add esp, 4 ; not for Cr1
+ pop eax
+ mov cr2, eax
+ pop eax
+ mov dword [ecx + IA32_TSS._CR3], eax
+ pop eax
+ mov cr4, eax
+
+;; UINT32 EFlags;
+ pop dword [ecx + IA32_TSS.EFLAGS]
+ mov ebx, dword [ecx + IA32_TSS.EFLAGS]
+ btr ebx, 9 ; Do 'cli'
+ mov dword [ecx + IA32_TSS.EFLAGS], ebx
+
+;; UINT32 Ldtr, Tr;
+;; UINT32 Gdtr[2], Idtr[2];
+;; Best not let anyone mess with these particular registers...
+ add esp, 24
+
+;; UINT32 Eip;
+ pop dword [ecx + IA32_TSS.EIP]
+
+;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
+;; NOTE - modified segment registers could hang the debugger... We
+;; could attempt to insulate ourselves against this possibility,
+;; but that poses risks as well.
+;;
+ pop eax
+o16 mov [ecx + IA32_TSS._GS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._FS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._ES], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._DS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._CS], ax
+ pop eax
+o16 mov [ecx + IA32_TSS._SS], ax
+
+;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+ pop dword [ecx + IA32_TSS._EDI]
+ pop dword [ecx + IA32_TSS._ESI]
+ add esp, 4 ; not for ebp
+ add esp, 4 ; not for esp
+ pop dword [ecx + IA32_TSS._EBX]
+ pop dword [ecx + IA32_TSS._EDX]
+ pop dword [ecx + IA32_TSS._ECX]
+ pop dword [ecx + IA32_TSS._EAX]
+
+; Set single step DB# to allow debugger to able to go back to the EIP
+; where the exception is triggered.
+
+;; Create return context for iretd in stub function
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
+ mov ebx, dword [ecx + IA32_TSS.EIP]
+ mov [eax - 0xc], ebx ; create EIP in old stack
+ movzx ebx, word [ecx + IA32_TSS._CS]
+ mov [eax - 0x8], ebx ; create CS in old stack
+ mov ebx, dword [ecx + IA32_TSS.EFLAGS]
+ bts ebx, 8
+ mov [eax - 0x4], ebx ; create eflags in old stack
+ mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
+ sub eax, 0xc ; minus 12 byte
+ mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
+
+;; Replace the EIP of interrupted task with stub function
+ mov eax, ASM_PFX(SingleStepStubFunction)
+ mov dword [ecx + IA32_TSS.EIP], eax
+
+ mov ecx, [ebp - 8] ; Get current TSS base
+ mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack top
+ mov esp, ebp
+
+ ret
+
+global ASM_PFX(SingleStepStubFunction)
+ASM_PFX(SingleStepStubFunction):
+;
+; we need clean TS bit in CR0 to execute
+; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
+;
+ clts
+ iretd
+
+global ASM_PFX(AsmGetTssTemplateMap)
+ASM_PFX(AsmGetTssTemplateMap):
+ push ebp ; C prolog
+ mov ebp, esp
+ pushad
+
+ mov ebx, dword [ebp + 0x8]
+ mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
+ mov dword [ebx + 0x4], (AsmExceptionEntryEnd - AsmExceptionEntryBegin) / 32
+ mov dword [ebx + 0x8], 0
+
+ popad
+ pop ebp
+ ret
+
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
index 75443288a9..4c0d435136 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index d70a99c100..e5c03c16c9 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
index 634ffcb21d..56b875b7c8 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
@@ -30,6 +30,7 @@
[Sources.Ia32]
Ia32/ExceptionHandlerAsm.asm
Ia32/ExceptionHandlerAsm.nasm
+ Ia32/ExceptionTssEntryAsm.nasm
Ia32/ExceptionHandlerAsm.S
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index 65f0cff680..214aafcc13 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
SystemContext.SystemContextX64->ExceptionData = ReservedVectors[ExceptionType].ExceptionData;
}
+/**
+ Setup separate stack for given exceptions.
+
+ @param[in] StackSwitchData Pointer to data required for setuping up
+ stack switch.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.
+
+**/
+EFI_STATUS
+EFIAPI
+ArchSetupExcpetionStack (
+ IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
+ )
+{
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+ UINTN StackTop;
+ UINTN Index;
+ UINTN TssBase;
+ UINTN GdtSize;
+
+ if (StackSwitchData == NULL ||
+ StackSwitchData->StackTop == 0 ||
+ StackSwitchData->StackSize == 0 ||
+ StackSwitchData->Exceptions == NULL ||
+ StackSwitchData->ExceptionNumber == 0 ||
+ StackSwitchData->GdtTable == NULL ||
+ StackSwitchData->IdtTable == NULL ||
+ StackSwitchData->TssDesc == NULL ||
+ StackSwitchData->Tss == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // The caller is responsible for that the GDT table, no matter the existing
+ // one or newly allocated, has enough space to hold descriptors for exception
+ // task-state segments.
+ //
+ if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData->GdtTable)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((UINTN)StackSwitchData->TssDesc >=
+ ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtSize)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GdtSize = (UINTN)StackSwitchData->TssDesc -
+ (UINTN)(StackSwitchData->GdtTable) +
+ sizeof (IA32_TSS_DESCRIPTOR);
+ if (GdtSize > StackSwitchData->GdtSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize new GDT table and/or IDT table, if any
+ //
+ AsmReadIdtr (&Idtr);
+ AsmReadGdtr (&Gdtr);
+ if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
+ CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
+ Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
+ Gdtr.Limit = (UINT16)GdtSize - 1;
+ }
+
+ if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
+ Idtr.Base = (UINTN)StackSwitchData->IdtTable;
+ }
+
+ //
+ // Fixup current task descriptor. Task-state segment for current task will
+ // be filled by processor during task switching.
+ //
+ TssDesc = StackSwitchData->TssDesc;
+ Tss = StackSwitchData->Tss;
+
+ TssBase = (UINTN)Tss;
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
+ TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
+
+ //
+ // Fixup exception task descriptor and task-state segment
+ //
+ StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
+ StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
+ IdtTable = StackSwitchData->IdtTable;
+ for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
+ //
+ // Fixup IST
+ //
+ Tss->IST[Index] = StackTop;
+ StackTop -= StackSwitchData->StackSize;
+
+ //
+ // Set the IST field to enable corresponding IST
+ //
+ IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 = (UINT8)(Index + 1);
+ }
+
+ //
+ // Publish GDT
+ //
+ AsmWriteGdtr (&Gdtr);
+
+ //
+ // Load current task
+ //
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
+
+ //
+ // Publish IDT
+ //
+ AsmWriteIdtr (&Idtr);
+
+ return EFI_SUCCESS;
+}
+
/**
Display CPU information.
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
index 906480134a..c88be46286 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
@@ -43,4 +43,7 @@ typedef struct {
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA;
+#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
+#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
+
#endif
--
2.14.1.windows.1
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply related [flat|nested] 35+ messages in thread
* 答复: [PATCH v2 0/8] Implement stack guard feature
2017-11-23 5:40 ` Yao, Jiewen
@ 2017-11-25 13:44 ` Fan Jeff
2017-11-25 13:55 ` Yao, Jiewen
0 siblings, 1 reply; 35+ messages in thread
From: Fan Jeff @ 2017-11-25 13:44 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
Jian,
I reviewed your patches and sent my minimal comments in other separate mail. They should not impact the functionality.
I am ok if you push the v2 patches now and do the updating based on my comments in separate patches later.
Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
Thanks!
Jeff
> > > -----Original Message-----
> > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Jian
> > J
> > > Wang
> > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > To: edk2-devel@lists.01.org
> > > Subject: [edk2] [PATCH v2 0/8] Implement stack guard feature
> > >
> > > Stack guard feature makes use of paging mechanism to monitor if there's a
> > > stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added
> > to
> > > enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and
> > > PcdCpuKnownGoodStackSize are introduced to configure the required
> > > exceptions
> > > and stack size.
> > >
> > > If this feature is enabled, DxeIpl will setup page tables and set page where
> > > the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page
> > > Fault exception will be triggered.
> > >
> > > In order to make sure exception handler works normally even when the stack
> > > is corrupted, stack switching is implemented in exception library.
> > >
> > > Due to the mechanism behind Stack Guard, this feature is only avaiable for
> > > UEFI drivers (memory avaiable). That also means it doesn't support NT32
> > > emulated platform (paging not supported).
> > >
> > > Validation works include:
> > > a. OVMF emulated platform: boot to shell (IA32/X64)
> > > b. Intel real platform: boot to shell (IA32/X64)
> > >
> > > Jian J Wang (8):
> > > MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
> > > MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
> > > MdePkg/BaseLib: Add stack switch related definitions for IA32
> > > MdeModulePkg/DxeIpl: Enable paging for Stack Guard
> > > UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch
> > > UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data
> > > UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
> > > UefiCpuPkg/CpuDxe: Initialize stack switch for MP
> > >
> > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +-
> > > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +
> > > MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 +
> > > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++-
> > > .../Include/Library/CpuExceptionHandlerLib.h | 18 +
> > > MdeModulePkg/MdeModulePkg.dec | 7 +
> > > MdeModulePkg/MdeModulePkg.uni | 7 +
> > > MdePkg/Include/Library/BaseLib.h | 115 ++++++
> > > MdePkg/Library/BaseLib/BaseLib.inf | 3 +
> > > MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++
> > > MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++
> > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
> > > UefiCpuPkg/CpuDxe/CpuMp.c | 168
> +++++++++
> > > UefiCpuPkg/CpuDxe/CpuMp.h | 12 +
> > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > +++++++++++++++++++++
> > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +
> > > UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +
> > > UefiCpuPkg/UefiCpuPkg.dec | 12 +
> > > 28 files changed, 1304 insertions(+), 16 deletions(-)
> > > create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
> > > create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm
> > > create mode 100644
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > >
> > > --
> > > 2.14.1.windows.1
> > >
> > > _______________________________________________
> > > edk2-devel mailing list
> > > edk2-devel@lists.01.org
> > > https://lists.01.org/mailman/listinfo/edk2-devel
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 答复: [PATCH v2 0/8] Implement stack guard feature
2017-11-25 13:44 ` 答复: " Fan Jeff
@ 2017-11-25 13:55 ` Yao, Jiewen
0 siblings, 0 replies; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-25 13:55 UTC (permalink / raw)
To: Fan Jeff; +Cc: Wang, Jian J, edk2-devel@lists.01.org
I do not think it is a good idea to push it now.
I think we need more thought on API design especially for pei/smm in the future. (My comment for 1.2/1.3/1.4)
thank you!
Yao, Jiewen
> 在 2017年11月25日，下午9:44，Fan Jeff <vanjeff_919@hotmail.com> 写道：
>
> Jian,
>
> I reviewed your patches and sent my minimal comments in other separate mail. They should not impact the functionality.
>
> I am ok if you push the v2 patches now and do the updating based on my comments in separate patches later.
>
> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
>
> Thanks!
> Jeff
>
>>>> -----Original Message-----
>>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>> Jian
>>> J
>>>> Wang
>>>> Sent: Wednesday, November 22, 2017 4:46 PM
>>>> To: edk2-devel@lists.01.org
>>>> Subject: [edk2] [PATCH v2 0/8] Implement stack guard feature
>>>>
>>>> Stack guard feature makes use of paging mechanism to monitor if there's a
>>>> stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added
>>> to
>>>> enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and
>>>> PcdCpuKnownGoodStackSize are introduced to configure the required
>>>> exceptions
>>>> and stack size.
>>>>
>>>> If this feature is enabled, DxeIpl will setup page tables and set page where
>>>> the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page
>>>> Fault exception will be triggered.
>>>>
>>>> In order to make sure exception handler works normally even when the stack
>>>> is corrupted, stack switching is implemented in exception library.
>>>>
>>>> Due to the mechanism behind Stack Guard, this feature is only avaiable for
>>>> UEFI drivers (memory avaiable). That also means it doesn't support NT32
>>>> emulated platform (paging not supported).
>>>>
>>>> Validation works include:
>>>> a. OVMF emulated platform: boot to shell (IA32/X64)
>>>> b. Intel real platform: boot to shell (IA32/X64)
>>>>
>>>> Jian J Wang (8):
>>>> MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
>>>> MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
>>>> MdePkg/BaseLib: Add stack switch related definitions for IA32
>>>> MdeModulePkg/DxeIpl: Enable paging for Stack Guard
>>>> UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch
>>>> UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data
>>>> UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
>>>> UefiCpuPkg/CpuDxe: Initialize stack switch for MP
>>>>
>>>> MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +-
>>>> MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +
>>>> MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 +
>>>> MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++-
>>>> .../Include/Library/CpuExceptionHandlerLib.h | 18 +
>>>> MdeModulePkg/MdeModulePkg.dec | 7 +
>>>> MdeModulePkg/MdeModulePkg.uni | 7 +
>>>> MdePkg/Include/Library/BaseLib.h | 115 ++++++
>>>> MdePkg/Library/BaseLib/BaseLib.inf | 3 +
>>>> MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++
>>>> MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++
>>>> UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +
>>>> UefiCpuPkg/CpuDxe/CpuMp.c | 168
>> +++++++++
>>>> UefiCpuPkg/CpuDxe/CpuMp.h | 12 +
>>>> .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
>>>> .../DxeCpuExceptionHandlerLib.inf | 6 +
>>>> .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
>>>> .../Ia32/ArchExceptionHandler.c | 167 +++++++++
>>>> .../Ia32/ArchInterruptDefs.h | 8 +
>>>> .../Ia32/ExceptionTssEntryAsm.nasm | 398
>>>> +++++++++++++++++++++
>>>> .../PeiCpuExceptionHandlerLib.inf | 1 +
>>>> .../SecPeiCpuExceptionHandlerLib.inf | 1 +
>>>> .../SmmCpuExceptionHandlerLib.inf | 1 +
>>>> .../X64/ArchExceptionHandler.c | 133 +++++++
>>>> .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
>>>> UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +
>>>> UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +
>>>> UefiCpuPkg/UefiCpuPkg.dec | 12 +
>>>> 28 files changed, 1304 insertions(+), 16 deletions(-)
>>>> create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm
>>>> create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm
>>>> create mode 100644
>>>>
>>>
>> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
>>>>
>>>> --
>>>> 2.14.1.windows.1
>>>>
>>>> _______________________________________________
>>>> edk2-devel mailing list
>>>> edk2-devel@lists.01.org
>>>> https://lists.01.org/mailman/listinfo/edk2-devel
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
2017-11-25 13:17 ` 答复: " Fan Jeff
@ 2017-11-27 2:20 ` Wang, Jian J
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Jian J @ 2017-11-27 2:20 UTC (permalink / raw)
To: Fan Jeff, Yao, Jiewen, edk2-devel@lists.01.org; +Cc: Dong, Eric, Zeng, Star
If we use union data, other arch of processors can add their own definitions in it without interfering ours. Is the MdeModulePkg for IA32 only?
This data is used to reserve resources in different boot phases. Unless we can limit its uses in just UefiCpuPkg, maybe MdeModulePkg is the only choice. But at least in my current implementation, we can just put it in UefiCpuPkg. I’m just not sure of any future impact.
From: Fan Jeff [mailto:vanjeff_919@hotmail.com]
Sent: Saturday, November 25, 2017 9:18 PM
To: Wang, Jian J <jian.j.wang@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
Cc: Dong, Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
Subject: 答复: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
Hi,
I am not sure if this is good idea to define such arch specific definitions in MdeModulePkg. Moreover, we don’t know how ARM or other processors define this definition, either.
Jeff
________________________________
From: edk2-devel <edk2-devel-bounces@lists.01.org<mailto:edk2-devel-bounces@lists.01.org>> on behalf of Wang, Jian J <jian.j.wang@intel.com<mailto:jian.j.wang@intel.com>>
Sent: Thursday, November 23, 2017 1:06:53 PM
To: Yao, Jiewen; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
Cc: Dong, Eric; Zeng, Star
Subject: Re: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API
Good idea. I think it should be defined in also in following file besides the new API
MdeModulePkg\Include\Library\CpuExceptionHandlerLib.h
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 12:08 PM
> To: Wang, Jian J <jian.j.wang@intel.com<mailto:jian.j.wang@intel.com>>; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> Cc: Dong, Eric <eric.dong@intel.com<mailto:eric.dong@intel.com>>; Zeng, Star <star.zeng@intel.com<mailto:star.zeng@intel.com>>
> Subject: RE: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h:
> Add a new API
>
> Hi
> I am a little worried about the way to use VOID * to pass arch dependent data.
>
> Can we define it clearly in each ARCH in the header file, and use a UNION to
> include all arch?
>
> I think both the caller and the callee need parse it. As such, VOID * is not a good
> way.
>
> Thank you
> Yao Jiewen
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jian
> J
> > Wang
> > Sent: Wednesday, November 22, 2017 4:46 PM
> > To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> > Cc: Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Dong, Eric <eric.dong@intel.com<mailto:eric.dong@intel.com>>;
> > Zeng, Star <star.zeng@intel.com<mailto:star.zeng@intel.com>>
> > Subject: [edk2] [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h:
> Add
> > a new API
> >
> > > v2:
> > > Add prototype definition of InitializeCpuExceptionStackSwitchHandlers()
> >
> > A new API InitializeCpuExceptionStackSwitchHandlers() is introduced to
> support
> > initializing exception handlers being able to switch stack. StackSwitchData is
> > arch dependent and required by IA32 processor to convey resources reserved
> in
> > advance. This is necessary because the CpuExceptionHandlerLib will be linked
> > in different phases, in which there's no common way to reserve resources.
> >
> > EFI_STATUS
> > EFIAPI
> > InitializeCpuExceptionStackSwitchHandlers (
> > IN VOID *StackSwitchData OPTIONAL
> > );
> >
> > Cc: Star Zeng <star.zeng@intel.com<mailto:star.zeng@intel.com>>
> > Cc: Eric Dong <eric.dong@intel.com<mailto:eric.dong@intel.com>>
> > Cc: Jiewen Yao <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
> > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com<mailto:ayellet.wolman@intel.com>>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang <jian.j.wang@intel.com<mailto:jian.j.wang@intel.com>>
> > ---
> > MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h | 18
> > ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > index 6cd8230127..68de4850e1 100644
> > --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> > @@ -41,6 +41,24 @@ InitializeCpuExceptionHandlers (
> > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > );
> >
> > +/**
> > + Setup separate stack for given exceptions. StackSwitchData is optional and
> its
> > + content depends one the specific arch of CPU.
> > +
> > + @param[in] StackSwitchData Pointer to data required for setuping up
> > + stack switch.
> > +
> > + @retval EFI_SUCCESS The exceptions have been successfully
> > + initialized.
> > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > content.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +InitializeCpuExceptionStackSwitchHandlers (
> > + IN VOID *StackSwitchData OPTIONAL
> > + );
> > +
> > /**
> > Initializes all CPU interrupt/exceptions entries and provides the default
> > interrupt/exception handlers.
> >
> > --
> > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> > https://lists.01.org/mailman/listinfo/edk2-devel
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-25 13:27 ` 答复: " Fan Jeff
@ 2017-11-27 2:21 ` Wang, Jian J
0 siblings, 0 replies; 35+ messages in thread
From: Wang, Jian J @ 2017-11-27 2:21 UTC (permalink / raw)
To: Fan Jeff, Yao, Jiewen, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
Good catch. I’ll add them. Thanks.
From: Fan Jeff [mailto:vanjeff_919@hotmail.com]
Sent: Saturday, November 25, 2017 9:28 PM
To: Wang, Jian J <jian.j.wang@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
Subject: 答复: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
Hi,
About 1.1), I agree with Jiewen’s suggestion. Besides it, we also need to provide dummy function of InitializeCpuExceptionStackSwitchHandlers() in NULL instance in MdeModulePkg/Library/CpuExceptionHandlerLibNull.
But we need to think about the return status carefully. For example, if return EFI_UNSUPPORTED in Pei/SMM instrance, we need to update public header file to add this return type.
Jeff
________________________________
From: edk2-devel <edk2-devel-bounces@lists.01.org<mailto:edk2-devel-bounces@lists.01.org>> on behalf of Wang, Jian J <jian.j.wang@intel.com<mailto:jian.j.wang@intel.com>>
Sent: Thursday, November 23, 2017 2:43:44 PM
To: Yao, Jiewen; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
Cc: Kinney, Michael D; Dong, Eric; Zeng, Star
Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
1.1) Got your point. I'll add dummy function in this patch.
1.2) Yep, we're on the same page.
1.3) Here's my opinion:
Actually almost all MP code has such assumption: any AP configuration will copy
from BSP. If we allow AP to call InitializeCpuExceptionHandlers(), we have to do a lot
of other changes than just updating InitializeCpuExceptionHandlers(). If so, it may
be premature to figure out a solution at this patch.
In addition, CpuDxe actually calls InitializeCpuInterruptHandlers() which covers the
functionalities of InitializeCpuExceptionHandlers() (its settings will be overwritten).
If we want AP to initialize interrupt and exception individually, maybe we should
let AP call InitializeCpuInterruptHandlers() instead.
> -----Original Message-----
> From: Yao, Jiewen
> Sent: Thursday, November 23, 2017 2:16 PM
> To: Wang, Jian J <jian.j.wang@intel.com<mailto:jian.j.wang@intel.com>>; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> Cc: Zeng, Star <star.zeng@intel.com<mailto:star.zeng@intel.com>>; Dong, Eric <eric.dong@intel.com<mailto:eric.dong@intel.com>>;
> Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Here is my thought for 1)
>
> 1.1) We must provide the InitializeCpuExceptionStackSwitchHandlers()
> implementation in Pei instance and Smm instance.
>
> The basic requirement is a library instance must provide symbol for functions
> declared in header file.
> It is ok to return unsupported. But we MUST provide the symbol.
>
> 1.2) For SMM, I think our ultimate goal is to remove SMM specific stack guard,
> and use the common one. Duplicating code is completely unnecessary, and it is
> easy to introduce bug. And unfortunately, we already have bug in existing SMM
> exception handler. -- That is a good reason to remove duplication.
>
> Again, it is not necessary to do it in this patch. I am totally OK to do it in another
> patch.
>
> 1.3) For PEI, I do not think we can use current way to allocate stack in data
> section, because it might be readonly in pre-mem phase. We must use some
> other way.
>
> 1.4) I believe this patch has a hidden assumption is that:
> InitializeCpuExceptionHandlers() won't be called by multiple APs.
> If 2 or more APs call the it at same time, it might be broken because you use
> mNewStack for all the callers....
> Is that right?
>
>
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: Wang, Jian J
> > Sent: Thursday, November 23, 2017 2:06 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> > Cc: Zeng, Star <star.zeng@intel.com<mailto:star.zeng@intel.com>>; Dong, Eric <eric.dong@intel.com<mailto:eric.dong@intel.com>>;
> Kinney,
> > Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
> > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch support
> >
> >
> >
> > > -----Original Message-----
> > > From: Yao, Jiewen
> > > Sent: Thursday, November 23, 2017 1:50 PM
> > > To: Wang, Jian J <jian.j.wang@intel.com<mailto:jian.j.wang@intel.com>>; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> > > Cc: Zeng, Star <star.zeng@intel.com<mailto:star.zeng@intel.com>>; Dong, Eric <eric.dong@intel.com<mailto:eric.dong@intel.com>>;
> > > Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
> > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch support
> > >
> > > Some thought:
> > >
> > > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented
> in
> > > DxeException.c.
> > > What about Pei/Smm instance?
> > >
> > > I think it is OK to not implement it at this moment. But we need make sure no
> > > architecture issue if we want to enable it some time later.
> > >
> > Like what we discussed before, this series of patch is for Stack Guard feature
> > which
> > is only available for DXE (because Stack Guard needs paging to work). Stack
> > switch
> > is enabled for the sake of Stack Guard feature. So I think it's enough to
> > implement
> > it in DxeException.c. In addition, SMM has its own implementation of stack
> guard
> > and stack switch. It's not necessary to do it again.
> >
> > I agree with you that we should merge those common code but I think we
> should
> > do
> > it in a separate patch series since it's not Stack Guard relevant. And I've
> removed
> > all architecture issues I can think of. Current stack switch initialization should
> work
> > for both PEI and SMM as well.
> >
> > > 2) #define IA32_GDT_TYPE_TSS 0x9
> > > This is generic, can we move to BaseLib.h?
> > >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > >
> > > > -----Original Message-----
> > > > From: Wang, Jian J
> > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> > > > Cc: Zeng, Star <star.zeng@intel.com<mailto:star.zeng@intel.com>>; Dong, Eric <eric.dong@intel.com<mailto:eric.dong@intel.com>>;
> Yao,
> > > > Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Kinney, Michael D
> > > > <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
> > > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch
> > > > support
> > > >
> > > > > v2:
> > > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to
> > setup
> > > > stack
> > > > > switch. This can avoid allocating memory for it in this library.
> > > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > > phase of DXE core.
> > > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > > support
> > > > > memory allocation because those memory can passed in by
> > parameter
> > > > now.
> > > > > e. Remove the nasm macro to define exception handler one by one
> > and
> > > > add a
> > > > > function to return the start address of each handler.
> > > >
> > > > If Stack Guard is enabled and there's really a stack overflow happened
> during
> > > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > > usage, the exception handler, which shares the stack with normal UEFI
> driver,
> > > > cannot be executed and cannot dump the processor information.
> > > >
> > > > Without those information, it's very difficult for the BIOS developers locate
> > > > the root cause of stack overflow. And without a workable stack, the
> > developer
> > > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > > >
> > > > In order to make sure the exception handler to execute normally after
> stack
> > > > overflow. We need separate stacks for exception handlers in case of
> unusable
> > > > stack.
> > > >
> > > > IA processor allows to switch to a new stack during handling interrupt and
> > > > exception. But X64 and IA32 provides different ways to make it. X64
> provides
> > > > interrupt stack table (IST) to allow maximum 7 different exceptions to have
> > > > new stack for its handler. IA32 doesn't have IST mechanism and can only
> use
> > > > task gate to do it since task switch allows to load a new stack through its
> > > > task-state segment (TSS).
> > > >
> > > > Cc: Star Zeng <star.zeng@intel.com<mailto:star.zeng@intel.com>>
> > > > Cc: Eric Dong <eric.dong@intel.com<mailto:eric.dong@intel.com>>
> > > > Cc: Jiewen Yao <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
> > > > Cc: Michael Kinney <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
> > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com<mailto:ayellet.wolman@intel.com>>
> > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com<mailto:jian.j.wang@intel.com>>
> > > > ---
> > > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > > +++++++++++++++++++++
> > > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > > create mode 100644
> > > >
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > index 740a58828b..30334105d2 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > @@ -48,6 +48,32 @@
> > > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9, 0x2c,
> > > 0x83 }
> > > > \
> > > > }
> > > >
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > > +
> > > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > > +
> > > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > > CPU_TSS_SIZE)
> > > > +
> > > > +#define IA32_GDT_TYPE_TSS 0x9
> > > > +#define IA32_GDT_ALIGNMENT 8
> > > > +
> > > > +typedef struct {
> > > > + UINTN StackTop;
> > > > + UINTN StackSize;
> > > > + UINT8 *Exceptions;
> > > > + UINTN ExceptionNumber;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > + UINTN GdtSize;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > +
> > > > //
> > > > // Record exception handler information
> > > > //
> > > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > > );
> > > >
> > > > +/**
> > > > + Setup separate stack for specific exceptions.
> > > > +
> > > > + @param[in] IdtTable IDT table base.
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + );
> > > > +
> > > > +/**
> > > > + Return address map of exception handler template so that C code can
> > > > generate
> > > > + exception tables. The template is only for exceptions using task gate
> > instead
> > > > + of interrupt gate.
> > > > +
> > > > + @param AddressMap Pointer to a buffer where the address map is
> > > > returned.
> > > > +**/
> > > > +VOID
> > > > +EFIAPI
> > > > +AsmGetTssTemplateMap (
> > > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > > + );
> > > > +
> > > > #endif
> > > >
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > index f4a8d01c80..58e55a8a2e 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > @@ -47,6 +48,11 @@
> > > > PeiDxeSmmCpuException.c
> > > > DxeException.c
> > > >
> > > > +[Pcd]
> > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > +
> > > > [Packages]
> > > > MdePkg/MdePkg.dec
> > > > MdeModulePkg/MdeModulePkg.dec
> > > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > index 31febec976..c0b2c615aa 100644
> > > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > @@ -25,6 +25,10 @@ UINTN
> > mEnabledInterruptNum =
> > > > 0;
> > > >
> > > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > > >
> > > > +UINT8
> > > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > > +
> > CPU_KNOWN_GOOD_STACK_SIZE]
> > > > = {0};
> > > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > > +
> > > > /**
> > > > Common exception handler.
> > > >
> > > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > > )
> > > > {
> > > > + EFI_STATUS Status;
> > > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > +
> > > > mExceptionHandlerData.ReservedVectors =
> > > > mReservedVectorsData;
> > > > mExceptionHandlerData.ExternalInterruptHandler =
> > > > mExternalInterruptHandlerTable;
> > > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > &mExceptionHandlerData);
> > > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > +
> > > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > > + StackSwitchData.ExceptionNumber =
> > > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> > *)mNewGdt;
> > > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > > Gdtr.Limit + 1);
> > > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > > Gdtr.Limit + 1 +
> > > > +
> > > > CPU_TSS_DESC_SIZE);
> > > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > > + &StackSwitchData
> > > > + );
> > > > + }
> > > > + return Status;
> > > > }
> > > >
> > > > /**
> > > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > > {
> > > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > InterruptHandler,
> > > > &mExceptionHandlerData);
> > > > }
> > > > +
> > > > +/**
> > > > + Setup separate stack for given exceptions. This is required by
> > > > + PcdCpuStackGuard feature.
> > > > +
> > > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +InitializeCpuExceptionStackSwitchHandlers (
> > > > + IN VOID *StackSwitchData OPTIONAL
> > > > + )
> > > > +{
> > > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > > +}
> > > > diff --git
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > index f2c39eb193..0aaf794795 100644
> > > > ---
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > +++
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextIa32->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for
> > setuping
> > > > up
> > > > + stack switch.
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN Vector;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > >GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > > + (StackSwitchData->ExceptionNumber + 1);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + AsmGetTssTemplateMap (&TemplateMap);
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + TssDesc += 1;
> > > > + Tss += 1;
> > > > +
> > > > + //
> > > > + // Fixup TSS descriptor
> > > > + //
> > > > + TssBase = (UINTN)Tss;
> > > > +
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > +
> > > > + //
> > > > + // Fixup TSS
> > > > + //
> > > > + Vector = StackSwitchData->Exceptions[Index];
> > > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > > + + Vector *
> > > > TemplateMap.ExceptionStubHeaderSize);
> > > > + Tss->EFLAGS = 0x2;
> > > > + Tss->ESP = StackTop;
> > > > + Tss->CR3 = AsmReadCr3 ();
> > > > + Tss->ES = AsmReadEs ();
> > > > + Tss->CS = AsmReadCs ();
> > > > + Tss->SS = AsmReadSs ();
> > > > + Tss->DS = AsmReadDs ();
> > > > + Tss->FS = AsmReadFs ();
> > > > + Tss->GS = AsmReadGs ();
> > > > +
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Update IDT to use Task Gate for given exception
> > > > + //
> > > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> > Gdtr.Base);
> > > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display processor context.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > index a8d3556a80..d9ded5977f 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > @@ -41,4 +41,12 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE \
> > > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > +#define CPU_TSS_SIZE \
> > > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > +
> > > > #endif
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > new file mode 100644
> > > > index 0000000000..62bcedea1a
> > > > --- /dev/null
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > m
> > > > @@ -0,0 +1,398 @@
> > > > +;------------------------------------------------------------------------------ ;
> > > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > > +; This program and the accompanying materials
> > > > +; are licensed and made available under the terms and conditions of the
> BSD
> > > > License
> > > > +; which accompanies this distribution. The full text of the license may be
> > > found
> > > > at
> > > > +; http://opensource.org/licenses/bsd-license.php.
> > > > +;
> > > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > > BASIS,
> > > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > > EXPRESS
> > > > OR IMPLIED.
> > > > +;
> > > > +; Module Name:
> > > > +;
> > > > +; ExceptionTssEntryAsm.Asm
> > > > +;
> > > > +; Abstract:
> > > > +;
> > > > +; IA32 CPU Exception Handler with Separate Stack
> > > > +;
> > > > +; Notes:
> > > > +;
> > > > +;------------------------------------------------------------------------------
> > > > +
> > > > +;
> > > > +; IA32 TSS Memory Layout Description
> > > > +;
> > > > +struc IA32_TSS
> > > > + resw 1
> > > > + resw 1
> > > > + .ESP0: resd 1
> > > > + .SS0: resw 1
> > > > + resw 1
> > > > + .ESP1: resd 1
> > > > + .SS1: resw 1
> > > > + resw 1
> > > > + .ESP2: resd 1
> > > > + .SS2: resw 1
> > > > + resw 1
> > > > + ._CR3: resd 1
> > > > + .EIP: resd 1
> > > > + .EFLAGS: resd 1
> > > > + ._EAX: resd 1
> > > > + ._ECX: resd 1
> > > > + ._EDX: resd 1
> > > > + ._EBX: resd 1
> > > > + ._ESP: resd 1
> > > > + ._EBP: resd 1
> > > > + ._ESI: resd 1
> > > > + ._EDI: resd 1
> > > > + ._ES: resw 1
> > > > + resw 1
> > > > + ._CS: resw 1
> > > > + resw 1
> > > > + ._SS: resw 1
> > > > + resw 1
> > > > + ._DS: resw 1
> > > > + resw 1
> > > > + ._FS: resw 1
> > > > + resw 1
> > > > + ._GS: resw 1
> > > > + resw 1
> > > > + .LDT: resw 1
> > > > + resw 1
> > > > + resw 1
> > > > + resw 1
> > > > +endstruc
> > > > +
> > > > +;
> > > > +; CommonExceptionHandler()
> > > > +;
> > > > +extern ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +SECTION .data
> > > > +
> > > > +SECTION .text
> > > > +
> > > > +ALIGN 8
> > > > +
> > > > +;
> > > > +; Exception handler stub table
> > > > +;
> > > > +AsmExceptionEntryBegin:
> > > > +%assign Vector 0
> > > > +%rep 32
> > > > +
> > > > +DoIret%[Vector]:
> > > > + iretd
> > > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > > + db 0x6a ; push #VectorNum
> > > > + db %[Vector]
> > > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > + call eax
> > > > + mov esp, eax ; Restore stack top
> > > > + jmp DoIret%[Vector]
> > > > +
> > > > +%assign Vector Vector+1
> > > > +%endrep
> > > > +AsmExceptionEntryEnd:
> > > > +
> > > > +;
> > > > +; Common part of exception handler
> > > > +;
> > > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > > + ;
> > > > + ; Stack:
> > > > + ; +---------------------+ <-- EBP - 8
> > > > + ; + TSS Base +
> > > > + ; +---------------------+ <-- EBP - 4
> > > > + ; + CPUID.EDX +
> > > > + ; +---------------------+ <-- EBP
> > > > + ; + EIP +
> > > > + ; +---------------------+ <-- EBP + 4
> > > > + ; + Vector Number +
> > > > + ; +---------------------+ <-- EBP + 8
> > > > + ; + Error Code +
> > > > + ; +---------------------+
> > > > + ;
> > > > +
> > > > + mov ebp, esp ; Stack frame
> > > > +
> > > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > > + mov eax, 1
> > > > + cpuid
> > > > + push edx
> > > > +
> > > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > > +; current TSS base
> > > > + sub esp, 8
> > > > + sgdt [esp + 2]
> > > > + mov eax, [esp + 4] ; GDT base
> > > > + add esp, 8
> > > > +
> > > > + xor ebx, ebx
> > > > + str bx ; Current TR
> > > > +
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Current TSS base
> > > > + push ecx ; keep it in stack for later use
> > > > +
> > > > + movzx ebx, word [ecx] ; Previous Task Link
> > > > + mov ecx, [eax + ebx + 2]
> > > > + shl ecx, 8
> > > > + mov cl, [eax + ebx + 7]
> > > > + ror ecx, 8 ; ecx = Previous TSS base
> > > > +
> > > > +;
> > > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > > EFI_SYSTEM_CONTEXT_IA32
> > > > +; is 16-byte aligned
> > > > +;
> > > > + and esp, 0xfffffff0
> > > > + sub esp, 12
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + push dword [ecx + IA32_TSS._EAX]
> > > > + push dword [ecx + IA32_TSS._ECX]
> > > > + push dword [ecx + IA32_TSS._EDX]
> > > > + push dword [ecx + IA32_TSS._EBX]
> > > > + push dword [ecx + IA32_TSS._ESP]
> > > > + push dword [ecx + IA32_TSS._EBP]
> > > > + push dword [ecx + IA32_TSS._ESI]
> > > > + push dword [ecx + IA32_TSS._EDI]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > > + push eax
> > > > +
> > > > +;; UINT32 Eip;
> > > > + push dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > + sub esp, 8
> > > > + sidt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > + sub esp, 8
> > > > + sgdt [esp]
> > > > + mov eax, [esp + 2]
> > > > + xchg eax, [esp]
> > > > + and eax, 0xFFFF
> > > > + mov [esp+4], eax
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > > + push eax
> > > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > > + push eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + mov eax, cr4
> > > > + push eax ; push cr4 firstly
> > > > +
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .1
> > > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > > +.1:
> > > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > > + jz .2
> > > > + or eax, BIT3 ; Set CR4.DE
> > > > +.2:
> > > > + mov cr4, eax
> > > > +
> > > > + mov eax, cr3
> > > > + push eax
> > > > + mov eax, cr2
> > > > + push eax
> > > > + xor eax, eax
> > > > + push eax
> > > > + mov eax, cr0
> > > > + push eax
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > + mov eax, dr7
> > > > + push eax
> > > > + mov eax, dr6
> > > > + push eax
> > > > + mov eax, dr3
> > > > + push eax
> > > > + mov eax, dr2
> > > > + push eax
> > > > + mov eax, dr1
> > > > + push eax
> > > > + mov eax, dr0
> > > > + push eax
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > > +;; when executing fxsave/fxrstor instruction
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > > + ; edx still contains result from CPUID above
> > > > + jz .3
> > > > + clts
> > > > + sub esp, 512
> > > > + mov edi, esp
> > > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > > +.3:
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + push dword [ebp + 8]
> > > > +
> > > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is
> > > clear
> > > > + cld
> > > > +
> > > > +;; call into exception handler
> > > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > > +
> > > > +;; Prepare parameter and call
> > > > + mov edx, esp
> > > > + push edx ; EFI_SYSTEM_CONTEXT
> > > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > > > +
> > > > + ;
> > > > + ; Call External Exception Handler
> > > > + ;
> > > > + call eax
> > > > + add esp, 8 ; Restore stack before calling
> > > > + mov ecx, esi ; Restore TSS base
> > > > +
> > > > +;; UINT32 ExceptionData;
> > > > + add esp, 4
> > > > +
> > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > + jz .4
> > > > + mov esi, esp
> > > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > > +.4:
> > > > + add esp, 512
> > > > +
> > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > +;; Skip restoration of DRx registers to support debuggers
> > > > +;; that set breakpoints in interrupt/exception context
> > > > + add esp, 4 * 6
> > > > +
> > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > + pop eax
> > > > + mov cr0, eax
> > > > + add esp, 4 ; not for Cr1
> > > > + pop eax
> > > > + mov cr2, eax
> > > > + pop eax
> > > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > > + pop eax
> > > > + mov cr4, eax
> > > > +
> > > > +;; UINT32 EFlags;
> > > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + btr ebx, 9 ; Do 'cli'
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > > +
> > > > +;; UINT32 Ldtr, Tr;
> > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > +;; Best not let anyone mess with these particular registers...
> > > > + add esp, 24
> > > > +
> > > > +;; UINT32 Eip;
> > > > + pop dword [ecx + IA32_TSS.EIP]
> > > > +
> > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > +;; NOTE - modified segment registers could hang the debugger... We
> > > > +;; could attempt to insulate ourselves against this possibility,
> > > > +;; but that poses risks as well.
> > > > +;;
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > > + pop eax
> > > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > > +
> > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > + pop dword [ecx + IA32_TSS._EDI]
> > > > + pop dword [ecx + IA32_TSS._ESI]
> > > > + add esp, 4 ; not for ebp
> > > > + add esp, 4 ; not for esp
> > > > + pop dword [ecx + IA32_TSS._EBX]
> > > > + pop dword [ecx + IA32_TSS._EDX]
> > > > + pop dword [ecx + IA32_TSS._ECX]
> > > > + pop dword [ecx + IA32_TSS._EAX]
> > > > +
> > > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > > +; where the exception is triggered.
> > > > +
> > > > +;; Create return context for iretd in stub function
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > > + mov [eax - 0xc], ebx ; create EIP in old
> > stack
> > > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > > + mov [eax - 0x8], ebx ; create CS in old stack
> > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > + bts ebx, 8
> > > > + mov [eax - 0x4], ebx ; create eflags in old
> > stack
> > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old
> > TSS
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > pointer
> > > > + sub eax, 0xc ; minus 12 byte
> > > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> > pointer
> > > > +
> > > > +;; Replace the EIP of interrupted task with stub function
> > > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > > +
> > > > + mov ecx, [ebp - 8] ; Get current TSS base
> > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack
> > top
> > > > + mov esp, ebp
> > > > +
> > > > + ret
> > > > +
> > > > +global ASM_PFX(SingleStepStubFunction)
> > > > +ASM_PFX(SingleStepStubFunction):
> > > > +;
> > > > +; we need clean TS bit in CR0 to execute
> > > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > > +;
> > > > + clts
> > > > + iretd
> > > > +
> > > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > > +ASM_PFX(AsmGetTssTemplateMap):
> > > > + push ebp ; C prolog
> > > > + mov ebp, esp
> > > > + pushad
> > > > +
> > > > + mov ebx, dword [ebp + 0x8]
> > > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > AsmExceptionEntryBegin)
> > > > / 32
> > > > + mov dword [ebx + 0x8], 0
> > > > +
> > > > + popad
> > > > + pop ebp
> > > > + ret
> > > > +
> > > > diff --git
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > index 75443288a9..4c0d435136 100644
> > > > ---
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > index d70a99c100..e5c03c16c9 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > nf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > index 634ffcb21d..56b875b7c8 100644
> > > > ---
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > +++
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > @@ -30,6 +30,7 @@
> > > > [Sources.Ia32]
> > > > Ia32/ExceptionHandlerAsm.asm
> > > > Ia32/ExceptionHandlerAsm.nasm
> > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > Ia32/ExceptionHandlerAsm.S
> > > > Ia32/ArchExceptionHandler.c
> > > > Ia32/ArchInterruptDefs.h
> > > > diff --git
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > index 65f0cff680..214aafcc13 100644
> > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > > SystemContext.SystemContextX64->ExceptionData =
> > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > }
> > > >
> > > > +/**
> > > > + Setup separate stack for given exceptions.
> > > > +
> > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > up
> > > > + stack switch.
> > > > +
> > > > + @retval EFI_SUCCESS The exceptions have been
> > successfully
> > > > + initialized.
> > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > content.
> > > > +
> > > > +**/
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +ArchSetupExcpetionStack (
> > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > + )
> > > > +{
> > > > + IA32_DESCRIPTOR Gdtr;
> > > > + IA32_DESCRIPTOR Idtr;
> > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > + UINTN StackTop;
> > > > + UINTN Index;
> > > > + UINTN TssBase;
> > > > + UINTN GdtSize;
> > > > +
> > > > + if (StackSwitchData == NULL ||
> > > > + StackSwitchData->StackTop == 0 ||
> > > > + StackSwitchData->StackSize == 0 ||
> > > > + StackSwitchData->Exceptions == NULL ||
> > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > + StackSwitchData->GdtTable == NULL ||
> > > > + StackSwitchData->IdtTable == NULL ||
> > > > + StackSwitchData->TssDesc == NULL ||
> > > > + StackSwitchData->Tss == NULL) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // The caller is responsible for that the GDT table, no matter the existing
> > > > + // one or newly allocated, has enough space to hold descriptors for
> > > exception
> > > > + // task-state segments.
> > > > + //
> > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> 1)) !=
> > 0)
> > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > >GdtTable))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > StackSwitchData->GdtSize))
> > > > {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > + return EFI_INVALID_PARAMETER;
> > > > + }
> > > > +
> > > > + //
> > > > + // Initialize new GDT table and/or IDT table, if any
> > > > + //
> > > > + AsmReadIdtr (&Idtr);
> > > > + AsmReadGdtr (&Gdtr);
> > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit +
> > 1);
> > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > > + }
> > > > +
> > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > + }
> > > > +
> > > > + //
> > > > + // Fixup current task descriptor. Task-state segment for current task will
> > > > + // be filled by processor during task switching.
> > > > + //
> > > > + TssDesc = StackSwitchData->TssDesc;
> > > > + Tss = StackSwitchData->Tss;
> > > > +
> > > > + TssBase = (UINTN)Tss;
> > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > + TssDesc->Bits.P = 1;
> > > > + TssDesc->Bits.LimitHigh = 0;
> > > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > > +
> > > > + //
> > > > + // Fixup exception task descriptor and task-state segment
> > > > + //
> > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > CPU_STACK_ALIGNMENT);
> > > > + IdtTable = StackSwitchData->IdtTable;
> > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > + //
> > > > + // Fixup IST
> > > > + //
> > > > + Tss->IST[Index] = StackTop;
> > > > + StackTop -= StackSwitchData->StackSize;
> > > > +
> > > > + //
> > > > + // Set the IST field to enable corresponding IST
> > > > + //
> > > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > > (UINT8)(Index + 1);
> > > > + }
> > > > +
> > > > + //
> > > > + // Publish GDT
> > > > + //
> > > > + AsmWriteGdtr (&Gdtr);
> > > > +
> > > > + //
> > > > + // Load current task
> > > > + //
> > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > +
> > > > + //
> > > > + // Publish IDT
> > > > + //
> > > > + AsmWriteIdtr (&Idtr);
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > /**
> > > > Display CPU information.
> > > >
> > > > diff --git
> > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > index 906480134a..c88be46286 100644
> > > > ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > @@ -43,4 +43,7 @@ typedef struct {
> > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > } RESERVED_VECTORS_DATA;
> > > >
> > > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > > +
> > > > #endif
> > > > --
> > > > 2.14.1.windows.1
_______________________________________________
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^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-23 6:43 ` Wang, Jian J
2017-11-25 13:27 ` 答复: " Fan Jeff
@ 2017-11-28 1:38 ` Wang, Jian J
2017-11-28 2:06 ` Yao, Jiewen
1 sibling, 1 reply; 35+ messages in thread
From: Wang, Jian J @ 2017-11-28 1:38 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
Sorry, 1.3 should be for your 1.4. I just noticed I missed your 1.3 comment.
Here's my opinion for it:
Current changes (use global variables to reserve resources) to
InitializeCpuExceptionHandlers() is for DXE only. For PEI, if we really need to worry
about the stack overflow and stack switch, we can have a different way to do it. For
example, we don't need to call InitializeCpuExceptionStackSwitchHandlers() inside
InitializeCpuExceptionHandlers(). We could call it whenever we can reserve memory blocks
and pass them to InitializeCpuExceptionStackSwitchHandlers() via parameter. I think this
is one of reason we have a separate method to initialize the exception handlers for the
sake of stack switch.
Calling InitializeCpuExceptionStackSwitchHandlers() inside InitializeCpuExceptionHandlers()
is just for the consideration of backward compatibility. Because this new API is just
implemented for IA32 processor at this time, calling it in DXE core will break the build of
other type of processors. This is another reason we have a separate method to do
exception handler initialization in a different way.
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Wang,
> Jian J
> Sent: Thursday, November 23, 2017 2:44 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> stack switch support
>
> 1.1) Got your point. I'll add dummy function in this patch.
> 1.2) Yep, we're on the same page.
> 1.3) Here's my opinion:
>
> Actually almost all MP code has such assumption: any AP configuration will copy
> from BSP. If we allow AP to call InitializeCpuExceptionHandlers(), we have to do
> a lot
> of other changes than just updating InitializeCpuExceptionHandlers(). If so, it
> may
> be premature to figure out a solution at this patch.
>
> In addition, CpuDxe actually calls InitializeCpuInterruptHandlers() which covers
> the
> functionalities of InitializeCpuExceptionHandlers() (its settings will be
> overwritten).
> If we want AP to initialize interrupt and exception individually, maybe we should
> let AP call InitializeCpuInterruptHandlers() instead.
>
> > -----Original Message-----
> > From: Yao, Jiewen
> > Sent: Thursday, November 23, 2017 2:16 PM
> > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Kinney, Michael D <michael.d.kinney@intel.com>
> > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > switch support
> >
> > Here is my thought for 1)
> >
> > 1.1) We must provide the InitializeCpuExceptionStackSwitchHandlers()
> > implementation in Pei instance and Smm instance.
> >
> > The basic requirement is a library instance must provide symbol for functions
> > declared in header file.
> > It is ok to return unsupported. But we MUST provide the symbol.
> >
> > 1.2) For SMM, I think our ultimate goal is to remove SMM specific stack guard,
> > and use the common one. Duplicating code is completely unnecessary, and it is
> > easy to introduce bug. And unfortunately, we already have bug in existing
> SMM
> > exception handler. -- That is a good reason to remove duplication.
> >
> > Again, it is not necessary to do it in this patch. I am totally OK to do it in
> another
> > patch.
> >
> > 1.3) For PEI, I do not think we can use current way to allocate stack in data
> > section, because it might be readonly in pre-mem phase. We must use some
> > other way.
> >
> > 1.4) I believe this patch has a hidden assumption is that:
> > InitializeCpuExceptionHandlers() won't be called by multiple APs.
> > If 2 or more APs call the it at same time, it might be broken because you use
> > mNewStack for all the callers....
> > Is that right?
> >
> >
> > Thank you
> > Yao Jiewen
> >
> >
> > > -----Original Message-----
> > > From: Wang, Jian J
> > > Sent: Thursday, November 23, 2017 2:06 PM
> > > To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Kinney,
> > > Michael D <michael.d.kinney@intel.com>
> > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch support
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Yao, Jiewen
> > > > Sent: Thursday, November 23, 2017 1:50 PM
> > > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > > > Kinney, Michael D <michael.d.kinney@intel.com>
> > > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> stack
> > > > switch support
> > > >
> > > > Some thought:
> > > >
> > > > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only implemented
> > in
> > > > DxeException.c.
> > > > What about Pei/Smm instance?
> > > >
> > > > I think it is OK to not implement it at this moment. But we need make sure
> no
> > > > architecture issue if we want to enable it some time later.
> > > >
> > > Like what we discussed before, this series of patch is for Stack Guard feature
> > > which
> > > is only available for DXE (because Stack Guard needs paging to work). Stack
> > > switch
> > > is enabled for the sake of Stack Guard feature. So I think it's enough to
> > > implement
> > > it in DxeException.c. In addition, SMM has its own implementation of stack
> > guard
> > > and stack switch. It's not necessary to do it again.
> > >
> > > I agree with you that we should merge those common code but I think we
> > should
> > > do
> > > it in a separate patch series since it's not Stack Guard relevant. And I've
> > removed
> > > all architecture issues I can think of. Current stack switch initialization should
> > work
> > > for both PEI and SMM as well.
> > >
> > > > 2) #define IA32_GDT_TYPE_TSS 0x9
> > > > This is generic, can we move to BaseLib.h?
> > > >
> > > >
> > > > Thank you
> > > > Yao Jiewen
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Wang, Jian J
> > > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > > To: edk2-devel@lists.01.org
> > > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Yao,
> > > > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > > > <michael.d.kinney@intel.com>
> > > > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > > switch
> > > > > support
> > > > >
> > > > > > v2:
> > > > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used to
> > > setup
> > > > > stack
> > > > > > switch. This can avoid allocating memory for it in this library.
> > > > > > c. Add globals to reserve memory for stack switch initialized in early
> > > > > > phase of DXE core.
> > > > > > d. Remove the filter code used to exclude boot modes which doesn't
> > > > > support
> > > > > > memory allocation because those memory can passed in by
> > > parameter
> > > > > now.
> > > > > > e. Remove the nasm macro to define exception handler one by one
> > > and
> > > > > add a
> > > > > > function to return the start address of each handler.
> > > > >
> > > > > If Stack Guard is enabled and there's really a stack overflow happened
> > during
> > > > > boot, a Page Fault exception will be triggered. Because the stack is out of
> > > > > usage, the exception handler, which shares the stack with normal UEFI
> > driver,
> > > > > cannot be executed and cannot dump the processor information.
> > > > >
> > > > > Without those information, it's very difficult for the BIOS developers
> locate
> > > > > the root cause of stack overflow. And without a workable stack, the
> > > developer
> > > > > cannot event use single step to debug the UEFI driver with JTAG debugger.
> > > > >
> > > > > In order to make sure the exception handler to execute normally after
> > stack
> > > > > overflow. We need separate stacks for exception handlers in case of
> > unusable
> > > > > stack.
> > > > >
> > > > > IA processor allows to switch to a new stack during handling interrupt
> and
> > > > > exception. But X64 and IA32 provides different ways to make it. X64
> > provides
> > > > > interrupt stack table (IST) to allow maximum 7 different exceptions to
> have
> > > > > new stack for its handler. IA32 doesn't have IST mechanism and can only
> > use
> > > > > task gate to do it since task switch allows to load a new stack through its
> > > > > task-state segment (TSS).
> > > > >
> > > > > Cc: Star Zeng <star.zeng@intel.com>
> > > > > Cc: Eric Dong <eric.dong@intel.com>
> > > > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > > > ---
> > > > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > > > .../Ia32/ArchExceptionHandler.c | 167 +++++++++
> > > > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > > > +++++++++++++++++++++
> > > > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > > > .../X64/ArchExceptionHandler.c | 133 +++++++
> > > > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > > > create mode 100644
> > > > >
> > > >
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > > > >
> > > > > diff --git
> > > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > index 740a58828b..30334105d2 100644
> > > > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > @@ -48,6 +48,32 @@
> > > > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89, 0xc9,
> 0x2c,
> > > > 0x83 }
> > > > > \
> > > > > }
> > > > >
> > > > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > > > +
> > > > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > > > +
> > > > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > > > +
> > > > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > > > CPU_TSS_SIZE)
> > > > > +
> > > > > +#define IA32_GDT_TYPE_TSS 0x9
> > > > > +#define IA32_GDT_ALIGNMENT 8
> > > > > +
> > > > > +typedef struct {
> > > > > + UINTN StackTop;
> > > > > + UINTN StackSize;
> > > > > + UINT8 *Exceptions;
> > > > > + UINTN ExceptionNumber;
> > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > > + UINTN GdtSize;
> > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > > +
> > > > > //
> > > > > // Record exception handler information
> > > > > //
> > > > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > > > );
> > > > >
> > > > > +/**
> > > > > + Setup separate stack for specific exceptions.
> > > > > +
> > > > > + @param[in] IdtTable IDT table base.
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +ArchSetupExcpetionStack (
> > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > + );
> > > > > +
> > > > > +/**
> > > > > + Return address map of exception handler template so that C code can
> > > > > generate
> > > > > + exception tables. The template is only for exceptions using task gate
> > > instead
> > > > > + of interrupt gate.
> > > > > +
> > > > > + @param AddressMap Pointer to a buffer where the address map is
> > > > > returned.
> > > > > +**/
> > > > > +VOID
> > > > > +EFIAPI
> > > > > +AsmGetTssTemplateMap (
> > > > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > > > + );
> > > > > +
> > > > > #endif
> > > > >
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > index f4a8d01c80..58e55a8a2e 100644
> > > > > ---
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > @@ -47,6 +48,11 @@
> > > > > PeiDxeSmmCpuException.c
> > > > > DxeException.c
> > > > >
> > > > > +[Pcd]
> > > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > > +
> > > > > [Packages]
> > > > > MdePkg/MdePkg.dec
> > > > > MdeModulePkg/MdeModulePkg.dec
> > > > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > index 31febec976..c0b2c615aa 100644
> > > > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > @@ -25,6 +25,10 @@ UINTN
> > > mEnabledInterruptNum =
> > > > > 0;
> > > > >
> > > > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > > > >
> > > > > +UINT8
> > > > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > > > +
> > > CPU_KNOWN_GOOD_STACK_SIZE]
> > > > > = {0};
> > > > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] = {0};
> > > > > +
> > > > > /**
> > > > > Common exception handler.
> > > > >
> > > > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > > > )
> > > > > {
> > > > > + EFI_STATUS Status;
> > > > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > > > + IA32_DESCRIPTOR Idtr;
> > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > +
> > > > > mExceptionHandlerData.ReservedVectors =
> > > > > mReservedVectorsData;
> > > > > mExceptionHandlerData.ExternalInterruptHandler =
> > > > > mExternalInterruptHandlerTable;
> > > > > InitializeSpinLock (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > > &mExceptionHandlerData);
> > > > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > > &mExceptionHandlerData);
> > > > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > > > + AsmReadIdtr (&Idtr);
> > > > > + AsmReadGdtr (&Gdtr);
> > > > > +
> > > > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > > > + StackSwitchData.Exceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > > > + StackSwitchData.ExceptionNumber =
> > > > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)Idtr.Base;
> > > > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> > > *)mNewGdt;
> > > > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt +
> > > > > Gdtr.Limit + 1);
> > > > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT *)(mNewGdt +
> > > > > Gdtr.Limit + 1 +
> > > > > +
> > > > > CPU_TSS_DESC_SIZE);
> > > > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > > > + &StackSwitchData
> > > > > + );
> > > > > + }
> > > > > + return Status;
> > > > > }
> > > > >
> > > > > /**
> > > > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > > > {
> > > > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > > InterruptHandler,
> > > > > &mExceptionHandlerData);
> > > > > }
> > > > > +
> > > > > +/**
> > > > > + Setup separate stack for given exceptions. This is required by
> > > > > + PcdCpuStackGuard feature.
> > > > > +
> > > > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > > > +
> > > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > > up
> > > > > + stack switch.
> > > > > +
> > > > > + @retval EFI_SUCCESS The exceptions have been
> > > successfully
> > > > > + initialized.
> > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > > content.
> > > > > +
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +InitializeCpuExceptionStackSwitchHandlers (
> > > > > + IN VOID *StackSwitchData OPTIONAL
> > > > > + )
> > > > > +{
> > > > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > > > +}
> > > > > diff --git
> > > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > index f2c39eb193..0aaf794795 100644
> > > > > ---
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > +++
> > > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > > > SystemContext.SystemContextIa32->ExceptionData =
> > > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > > }
> > > > >
> > > > > +/**
> > > > > + Setup separate stack for given exceptions.
> > > > > +
> > > > > + @param[in] StackSwitchData Pointer to data required for
> > > setuping
> > > > > up
> > > > > + stack switch.
> > > > > + @retval EFI_SUCCESS The exceptions have been
> > > successfully
> > > > > + initialized.
> > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > > content.
> > > > > +
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +ArchSetupExcpetionStack (
> > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > + )
> > > > > +{
> > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > + IA32_DESCRIPTOR Idtr;
> > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > + UINTN StackTop;
> > > > > + UINTN Index;
> > > > > + UINTN Vector;
> > > > > + UINTN TssBase;
> > > > > + UINTN GdtSize;
> > > > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > > > +
> > > > > + if (StackSwitchData == NULL ||
> > > > > + StackSwitchData->StackTop == 0 ||
> > > > > + StackSwitchData->StackSize == 0 ||
> > > > > + StackSwitchData->Exceptions == NULL ||
> > > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > > + StackSwitchData->GdtTable == NULL ||
> > > > > + StackSwitchData->IdtTable == NULL ||
> > > > > + StackSwitchData->TssDesc == NULL ||
> > > > > + StackSwitchData->Tss == NULL) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // The caller is responsible for that the GDT table, no matter the
> existing
> > > > > + // one or newly allocated, has enough space to hold descriptors for
> > > > exception
> > > > > + // task-state segments.
> > > > > + //
> > > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> > 1)) !=
> > > 0)
> > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > > >GdtTable))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > StackSwitchData->GdtSize))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > > > + (StackSwitchData->ExceptionNumber + 1);
> > > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Initialize new GDT table and/or IDT table, if any
> > > > > + //
> > > > > + AsmReadIdtr (&Idtr);
> > > > > + AsmReadGdtr (&Gdtr);
> > > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit
> +
> > > 1);
> > > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Fixup current task descriptor. Task-state segment for current task
> will
> > > > > + // be filled by processor during task switching.
> > > > > + //
> > > > > + TssDesc = StackSwitchData->TssDesc;
> > > > > + Tss = StackSwitchData->Tss;
> > > > > +
> > > > > + TssBase = (UINTN)Tss;
> > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > + TssDesc->Bits.P = 1;
> > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > > +
> > > > > + //
> > > > > + // Fixup exception task descriptor and task-state segment
> > > > > + //
> > > > > + AsmGetTssTemplateMap (&TemplateMap);
> > > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > > CPU_STACK_ALIGNMENT);
> > > > > + IdtTable = StackSwitchData->IdtTable;
> > > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > > + TssDesc += 1;
> > > > > + Tss += 1;
> > > > > +
> > > > > + //
> > > > > + // Fixup TSS descriptor
> > > > > + //
> > > > > + TssBase = (UINTN)Tss;
> > > > > +
> > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > + TssDesc->Bits.P = 1;
> > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > > +
> > > > > + //
> > > > > + // Fixup TSS
> > > > > + //
> > > > > + Vector = StackSwitchData->Exceptions[Index];
> > > > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > > > + + Vector *
> > > > > TemplateMap.ExceptionStubHeaderSize);
> > > > > + Tss->EFLAGS = 0x2;
> > > > > + Tss->ESP = StackTop;
> > > > > + Tss->CR3 = AsmReadCr3 ();
> > > > > + Tss->ES = AsmReadEs ();
> > > > > + Tss->CS = AsmReadCs ();
> > > > > + Tss->SS = AsmReadSs ();
> > > > > + Tss->DS = AsmReadDs ();
> > > > > + Tss->FS = AsmReadFs ();
> > > > > + Tss->GS = AsmReadGs ();
> > > > > +
> > > > > + StackTop -= StackSwitchData->StackSize;
> > > > > +
> > > > > + //
> > > > > + // Update IDT to use Task Gate for given exception
> > > > > + //
> > > > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> > > Gdtr.Base);
> > > > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Publish GDT
> > > > > + //
> > > > > + AsmWriteGdtr (&Gdtr);
> > > > > +
> > > > > + //
> > > > > + // Load current task
> > > > > + //
> > > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > > +
> > > > > + //
> > > > > + // Publish IDT
> > > > > + //
> > > > > + AsmWriteIdtr (&Idtr);
> > > > > +
> > > > > + return EFI_SUCCESS;
> > > > > +}
> > > > > +
> > > > > /**
> > > > > Display processor context.
> > > > >
> > > > > diff --git
> > > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > index a8d3556a80..d9ded5977f 100644
> > > > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > @@ -41,4 +41,12 @@ typedef struct {
> > > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > > } RESERVED_VECTORS_DATA;
> > > > >
> > > > > +#define CPU_TSS_DESC_SIZE \
> > > > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > > +
> > > > > +#define CPU_TSS_SIZE \
> > > > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > > +
> > > > > #endif
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > m
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > m
> > > > > new file mode 100644
> > > > > index 0000000000..62bcedea1a
> > > > > --- /dev/null
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > m
> > > > > @@ -0,0 +1,398 @@
> > > > > +;------------------------------------------------------------------------------ ;
> > > > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > > > +; This program and the accompanying materials
> > > > > +; are licensed and made available under the terms and conditions of the
> > BSD
> > > > > License
> > > > > +; which accompanies this distribution. The full text of the license may
> be
> > > > found
> > > > > at
> > > > > +; http://opensource.org/licenses/bsd-license.php.
> > > > > +;
> > > > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> > > > BASIS,
> > > > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > > > EXPRESS
> > > > > OR IMPLIED.
> > > > > +;
> > > > > +; Module Name:
> > > > > +;
> > > > > +; ExceptionTssEntryAsm.Asm
> > > > > +;
> > > > > +; Abstract:
> > > > > +;
> > > > > +; IA32 CPU Exception Handler with Separate Stack
> > > > > +;
> > > > > +; Notes:
> > > > > +;
> > > > > +;------------------------------------------------------------------------------
> > > > > +
> > > > > +;
> > > > > +; IA32 TSS Memory Layout Description
> > > > > +;
> > > > > +struc IA32_TSS
> > > > > + resw 1
> > > > > + resw 1
> > > > > + .ESP0: resd 1
> > > > > + .SS0: resw 1
> > > > > + resw 1
> > > > > + .ESP1: resd 1
> > > > > + .SS1: resw 1
> > > > > + resw 1
> > > > > + .ESP2: resd 1
> > > > > + .SS2: resw 1
> > > > > + resw 1
> > > > > + ._CR3: resd 1
> > > > > + .EIP: resd 1
> > > > > + .EFLAGS: resd 1
> > > > > + ._EAX: resd 1
> > > > > + ._ECX: resd 1
> > > > > + ._EDX: resd 1
> > > > > + ._EBX: resd 1
> > > > > + ._ESP: resd 1
> > > > > + ._EBP: resd 1
> > > > > + ._ESI: resd 1
> > > > > + ._EDI: resd 1
> > > > > + ._ES: resw 1
> > > > > + resw 1
> > > > > + ._CS: resw 1
> > > > > + resw 1
> > > > > + ._SS: resw 1
> > > > > + resw 1
> > > > > + ._DS: resw 1
> > > > > + resw 1
> > > > > + ._FS: resw 1
> > > > > + resw 1
> > > > > + ._GS: resw 1
> > > > > + resw 1
> > > > > + .LDT: resw 1
> > > > > + resw 1
> > > > > + resw 1
> > > > > + resw 1
> > > > > +endstruc
> > > > > +
> > > > > +;
> > > > > +; CommonExceptionHandler()
> > > > > +;
> > > > > +extern ASM_PFX(CommonExceptionHandler)
> > > > > +
> > > > > +SECTION .data
> > > > > +
> > > > > +SECTION .text
> > > > > +
> > > > > +ALIGN 8
> > > > > +
> > > > > +;
> > > > > +; Exception handler stub table
> > > > > +;
> > > > > +AsmExceptionEntryBegin:
> > > > > +%assign Vector 0
> > > > > +%rep 32
> > > > > +
> > > > > +DoIret%[Vector]:
> > > > > + iretd
> > > > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > > > + db 0x6a ; push #VectorNum
> > > > > + db %[Vector]
> > > > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > > + call eax
> > > > > + mov esp, eax ; Restore stack top
> > > > > + jmp DoIret%[Vector]
> > > > > +
> > > > > +%assign Vector Vector+1
> > > > > +%endrep
> > > > > +AsmExceptionEntryEnd:
> > > > > +
> > > > > +;
> > > > > +; Common part of exception handler
> > > > > +;
> > > > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > > > + ;
> > > > > + ; Stack:
> > > > > + ; +---------------------+ <-- EBP - 8
> > > > > + ; + TSS Base +
> > > > > + ; +---------------------+ <-- EBP - 4
> > > > > + ; + CPUID.EDX +
> > > > > + ; +---------------------+ <-- EBP
> > > > > + ; + EIP +
> > > > > + ; +---------------------+ <-- EBP + 4
> > > > > + ; + Vector Number +
> > > > > + ; +---------------------+ <-- EBP + 8
> > > > > + ; + Error Code +
> > > > > + ; +---------------------+
> > > > > + ;
> > > > > +
> > > > > + mov ebp, esp ; Stack frame
> > > > > +
> > > > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > > > + mov eax, 1
> > > > > + cpuid
> > > > > + push edx
> > > > > +
> > > > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > > > +; current TSS base
> > > > > + sub esp, 8
> > > > > + sgdt [esp + 2]
> > > > > + mov eax, [esp + 4] ; GDT base
> > > > > + add esp, 8
> > > > > +
> > > > > + xor ebx, ebx
> > > > > + str bx ; Current TR
> > > > > +
> > > > > + mov ecx, [eax + ebx + 2]
> > > > > + shl ecx, 8
> > > > > + mov cl, [eax + ebx + 7]
> > > > > + ror ecx, 8 ; ecx = Current TSS base
> > > > > + push ecx ; keep it in stack for later use
> > > > > +
> > > > > + movzx ebx, word [ecx] ; Previous Task Link
> > > > > + mov ecx, [eax + ebx + 2]
> > > > > + shl ecx, 8
> > > > > + mov cl, [eax + ebx + 7]
> > > > > + ror ecx, 8 ; ecx = Previous TSS base
> > > > > +
> > > > > +;
> > > > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > > > EFI_SYSTEM_CONTEXT_IA32
> > > > > +; is 16-byte aligned
> > > > > +;
> > > > > + and esp, 0xfffffff0
> > > > > + sub esp, 12
> > > > > +
> > > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > > + push dword [ecx + IA32_TSS._EAX]
> > > > > + push dword [ecx + IA32_TSS._ECX]
> > > > > + push dword [ecx + IA32_TSS._EDX]
> > > > > + push dword [ecx + IA32_TSS._EBX]
> > > > > + push dword [ecx + IA32_TSS._ESP]
> > > > > + push dword [ecx + IA32_TSS._EBP]
> > > > > + push dword [ecx + IA32_TSS._ESI]
> > > > > + push dword [ecx + IA32_TSS._EDI]
> > > > > +
> > > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > > > + push eax
> > > > > +
> > > > > +;; UINT32 Eip;
> > > > > + push dword [ecx + IA32_TSS.EIP]
> > > > > +
> > > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > > + sub esp, 8
> > > > > + sidt [esp]
> > > > > + mov eax, [esp + 2]
> > > > > + xchg eax, [esp]
> > > > > + and eax, 0xFFFF
> > > > > + mov [esp+4], eax
> > > > > +
> > > > > + sub esp, 8
> > > > > + sgdt [esp]
> > > > > + mov eax, [esp + 2]
> > > > > + xchg eax, [esp]
> > > > > + and eax, 0xFFFF
> > > > > + mov [esp+4], eax
> > > > > +
> > > > > +;; UINT32 Ldtr, Tr;
> > > > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > > > + push eax
> > > > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > > > + push eax
> > > > > +
> > > > > +;; UINT32 EFlags;
> > > > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > > > +
> > > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > > + mov eax, cr4
> > > > > + push eax ; push cr4 firstly
> > > > > +
> > > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > > + jz .1
> > > > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > > > +.1:
> > > > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > > > + jz .2
> > > > > + or eax, BIT3 ; Set CR4.DE
> > > > > +.2:
> > > > > + mov cr4, eax
> > > > > +
> > > > > + mov eax, cr3
> > > > > + push eax
> > > > > + mov eax, cr2
> > > > > + push eax
> > > > > + xor eax, eax
> > > > > + push eax
> > > > > + mov eax, cr0
> > > > > + push eax
> > > > > +
> > > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > > + mov eax, dr7
> > > > > + push eax
> > > > > + mov eax, dr6
> > > > > + push eax
> > > > > + mov eax, dr3
> > > > > + push eax
> > > > > + mov eax, dr2
> > > > > + push eax
> > > > > + mov eax, dr1
> > > > > + push eax
> > > > > + mov eax, dr0
> > > > > + push eax
> > > > > +
> > > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > > > +;; when executing fxsave/fxrstor instruction
> > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > > > + ; edx still contains result from CPUID above
> > > > > + jz .3
> > > > > + clts
> > > > > + sub esp, 512
> > > > > + mov edi, esp
> > > > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > > > +.3:
> > > > > +
> > > > > +;; UINT32 ExceptionData;
> > > > > + push dword [ebp + 8]
> > > > > +
> > > > > +;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs
> is
> > > > clear
> > > > > + cld
> > > > > +
> > > > > +;; call into exception handler
> > > > > + mov esi, ecx ; Keep TSS base to avoid overwrite
> > > > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > > > +
> > > > > +;; Prepare parameter and call
> > > > > + mov edx, esp
> > > > > + push edx ; EFI_SYSTEM_CONTEXT
> > > > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
> > > > > +
> > > > > + ;
> > > > > + ; Call External Exception Handler
> > > > > + ;
> > > > > + call eax
> > > > > + add esp, 8 ; Restore stack before calling
> > > > > + mov ecx, esi ; Restore TSS base
> > > > > +
> > > > > +;; UINT32 ExceptionData;
> > > > > + add esp, 4
> > > > > +
> > > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > > + jz .4
> > > > > + mov esi, esp
> > > > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > > > +.4:
> > > > > + add esp, 512
> > > > > +
> > > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > > +;; Skip restoration of DRx registers to support debuggers
> > > > > +;; that set breakpoints in interrupt/exception context
> > > > > + add esp, 4 * 6
> > > > > +
> > > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > > + pop eax
> > > > > + mov cr0, eax
> > > > > + add esp, 4 ; not for Cr1
> > > > > + pop eax
> > > > > + mov cr2, eax
> > > > > + pop eax
> > > > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > > > + pop eax
> > > > > + mov cr4, eax
> > > > > +
> > > > > +;; UINT32 EFlags;
> > > > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > > + btr ebx, 9 ; Do 'cli'
> > > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > > > +
> > > > > +;; UINT32 Ldtr, Tr;
> > > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > > +;; Best not let anyone mess with these particular registers...
> > > > > + add esp, 24
> > > > > +
> > > > > +;; UINT32 Eip;
> > > > > + pop dword [ecx + IA32_TSS.EIP]
> > > > > +
> > > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > > +;; NOTE - modified segment registers could hang the debugger... We
> > > > > +;; could attempt to insulate ourselves against this possibility,
> > > > > +;; but that poses risks as well.
> > > > > +;;
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > > > + pop eax
> > > > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > > > +
> > > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > > + pop dword [ecx + IA32_TSS._EDI]
> > > > > + pop dword [ecx + IA32_TSS._ESI]
> > > > > + add esp, 4 ; not for ebp
> > > > > + add esp, 4 ; not for esp
> > > > > + pop dword [ecx + IA32_TSS._EBX]
> > > > > + pop dword [ecx + IA32_TSS._EDX]
> > > > > + pop dword [ecx + IA32_TSS._ECX]
> > > > > + pop dword [ecx + IA32_TSS._EAX]
> > > > > +
> > > > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > > > +; where the exception is triggered.
> > > > > +
> > > > > +;; Create return context for iretd in stub function
> > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > > pointer
> > > > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > > > + mov [eax - 0xc], ebx ; create EIP in old
> > > stack
> > > > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > > > + mov [eax - 0x8], ebx ; create CS in old stack
> > > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > > + bts ebx, 8
> > > > > + mov [eax - 0x4], ebx ; create eflags in old
> > > stack
> > > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old
> > > TSS
> > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > > pointer
> > > > > + sub eax, 0xc ; minus 12 byte
> > > > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> > > pointer
> > > > > +
> > > > > +;; Replace the EIP of interrupted task with stub function
> > > > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > > > +
> > > > > + mov ecx, [ebp - 8] ; Get current TSS base
> > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack
> > > top
> > > > > + mov esp, ebp
> > > > > +
> > > > > + ret
> > > > > +
> > > > > +global ASM_PFX(SingleStepStubFunction)
> > > > > +ASM_PFX(SingleStepStubFunction):
> > > > > +;
> > > > > +; we need clean TS bit in CR0 to execute
> > > > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > > > +;
> > > > > + clts
> > > > > + iretd
> > > > > +
> > > > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > > > +ASM_PFX(AsmGetTssTemplateMap):
> > > > > + push ebp ; C prolog
> > > > > + mov ebp, esp
> > > > > + pushad
> > > > > +
> > > > > + mov ebx, dword [ebp + 0x8]
> > > > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > > AsmExceptionEntryBegin)
> > > > > / 32
> > > > > + mov dword [ebx + 0x8], 0
> > > > > +
> > > > > + popad
> > > > > + pop ebp
> > > > > + ret
> > > > > +
> > > > > diff --git
> > > > >
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > index 75443288a9..4c0d435136 100644
> > > > > ---
> > > > >
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > +++
> > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > > index d70a99c100..e5c03c16c9 100644
> > > > > ---
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > nf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > diff --git
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > > index 634ffcb21d..56b875b7c8 100644
> > > > > ---
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > > +++
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
> > > > > @@ -30,6 +30,7 @@
> > > > > [Sources.Ia32]
> > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > Ia32/ExceptionHandlerAsm.S
> > > > > Ia32/ArchExceptionHandler.c
> > > > > Ia32/ArchInterruptDefs.h
> > > > > diff --git
> > > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > index 65f0cff680..214aafcc13 100644
> > > > > ---
> > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > +++
> > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > > > SystemContext.SystemContextX64->ExceptionData =
> > > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > > }
> > > > >
> > > > > +/**
> > > > > + Setup separate stack for given exceptions.
> > > > > +
> > > > > + @param[in] StackSwitchData Pointer to data required for setuping
> > > up
> > > > > + stack switch.
> > > > > +
> > > > > + @retval EFI_SUCCESS The exceptions have been
> > > successfully
> > > > > + initialized.
> > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid
> > > > > content.
> > > > > +
> > > > > +**/
> > > > > +EFI_STATUS
> > > > > +EFIAPI
> > > > > +ArchSetupExcpetionStack (
> > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > + )
> > > > > +{
> > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > + IA32_DESCRIPTOR Idtr;
> > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > + UINTN StackTop;
> > > > > + UINTN Index;
> > > > > + UINTN TssBase;
> > > > > + UINTN GdtSize;
> > > > > +
> > > > > + if (StackSwitchData == NULL ||
> > > > > + StackSwitchData->StackTop == 0 ||
> > > > > + StackSwitchData->StackSize == 0 ||
> > > > > + StackSwitchData->Exceptions == NULL ||
> > > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > > + StackSwitchData->GdtTable == NULL ||
> > > > > + StackSwitchData->IdtTable == NULL ||
> > > > > + StackSwitchData->TssDesc == NULL ||
> > > > > + StackSwitchData->Tss == NULL) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // The caller is responsible for that the GDT table, no matter the
> existing
> > > > > + // one or newly allocated, has enough space to hold descriptors for
> > > > exception
> > > > > + // task-state segments.
> > > > > + //
> > > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT -
> > 1)) !=
> > > 0)
> > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > > >GdtTable))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > StackSwitchData->GdtSize))
> > > > > {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > > + return EFI_INVALID_PARAMETER;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Initialize new GDT table and/or IDT table, if any
> > > > > + //
> > > > > + AsmReadIdtr (&Idtr);
> > > > > + AsmReadGdtr (&Gdtr);
> > > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit
> +
> > > 1);
> > > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > > > + }
> > > > > +
> > > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Fixup current task descriptor. Task-state segment for current task
> will
> > > > > + // be filled by processor during task switching.
> > > > > + //
> > > > > + TssDesc = StackSwitchData->TssDesc;
> > > > > + Tss = StackSwitchData->Tss;
> > > > > +
> > > > > + TssBase = (UINTN)Tss;
> > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
> > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > + TssDesc->Bits.P = 1;
> > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > > > +
> > > > > + //
> > > > > + // Fixup exception task descriptor and task-state segment
> > > > > + //
> > > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > > CPU_STACK_ALIGNMENT);
> > > > > + IdtTable = StackSwitchData->IdtTable;
> > > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber; ++Index) {
> > > > > + //
> > > > > + // Fixup IST
> > > > > + //
> > > > > + Tss->IST[Index] = StackTop;
> > > > > + StackTop -= StackSwitchData->StackSize;
> > > > > +
> > > > > + //
> > > > > + // Set the IST field to enable corresponding IST
> > > > > + //
> > > > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > > > (UINT8)(Index + 1);
> > > > > + }
> > > > > +
> > > > > + //
> > > > > + // Publish GDT
> > > > > + //
> > > > > + AsmWriteGdtr (&Gdtr);
> > > > > +
> > > > > + //
> > > > > + // Load current task
> > > > > + //
> > > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc - Gdtr.Base));
> > > > > +
> > > > > + //
> > > > > + // Publish IDT
> > > > > + //
> > > > > + AsmWriteIdtr (&Idtr);
> > > > > +
> > > > > + return EFI_SUCCESS;
> > > > > +}
> > > > > +
> > > > > /**
> > > > > Display CPU information.
> > > > >
> > > > > diff --git
> > > > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > index 906480134a..c88be46286 100644
> > > > > ---
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > +++
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > @@ -43,4 +43,7 @@ typedef struct {
> > > > > UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > > } RESERVED_VECTORS_DATA;
> > > > >
> > > > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > > > +
> > > > > #endif
> > > > > --
> > > > > 2.14.1.windows.1
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support
2017-11-28 1:38 ` Wang, Jian J
@ 2017-11-28 2:06 ` Yao, Jiewen
0 siblings, 0 replies; 35+ messages in thread
From: Yao, Jiewen @ 2017-11-28 2:06 UTC (permalink / raw)
To: Wang, Jian J, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Dong, Eric, Zeng, Star
Thanks Jian.
I just talked to some other person, who think it is valuable to have stack guard in PEI as well, because they have seen stack overflow issue in PEI. I do think we need consider that, although it is not implemented in this patch series.
My thought for API is that the API design for PEI/DXE/SMM should be consistent.
When people look at the MdeModulePkg\Include\Library\CpuExceptionHandlerLib.h, he can know clearly on which API should be called and what is done in each API.
If we call InitializeCpuExceptionStackSwitchHandlers() inside InitializeCpuExceptionHandlers(), we should document this in .H file and make PEI/DXE/SMM version all implement in this way.
If we did one way for DXE, the other way for PEI, and another way for SMM, it might bring confusing.
Thank you
Yao Jiewen
> -----Original Message-----
> From: Wang, Jian J
> Sent: Tuesday, November 28, 2017 9:39 AM
> To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> switch support
>
> Sorry, 1.3 should be for your 1.4. I just noticed I missed your 1.3 comment.
> Here's my opinion for it:
>
> Current changes (use global variables to reserve resources) to
> InitializeCpuExceptionHandlers() is for DXE only. For PEI, if we really need to
> worry
> about the stack overflow and stack switch, we can have a different way to do it.
> For
> example, we don't need to call InitializeCpuExceptionStackSwitchHandlers()
> inside
> InitializeCpuExceptionHandlers(). We could call it whenever we can reserve
> memory blocks
> and pass them to InitializeCpuExceptionStackSwitchHandlers() via parameter. I
> think this
> is one of reason we have a separate method to initialize the exception handlers
> for the
> sake of stack switch.
>
> Calling InitializeCpuExceptionStackSwitchHandlers() inside
> InitializeCpuExceptionHandlers()
> is just for the consideration of backward compatibility. Because this new API is
> just
> implemented for IA32 processor at this time, calling it in DXE core will break the
> build of
> other type of processors. This is another reason we have a separate method to
> do
> exception handler initialization in a different way.
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Wang,
> > Jian J
> > Sent: Thursday, November 23, 2017 2:44 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Dong, Eric
> > <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> > Subject: Re: [edk2] [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> > stack switch support
> >
> > 1.1) Got your point. I'll add dummy function in this patch.
> > 1.2) Yep, we're on the same page.
> > 1.3) Here's my opinion:
> >
> > Actually almost all MP code has such assumption: any AP configuration will
> copy
> > from BSP. If we allow AP to call InitializeCpuExceptionHandlers(), we have to
> do
> > a lot
> > of other changes than just updating InitializeCpuExceptionHandlers(). If so, it
> > may
> > be premature to figure out a solution at this patch.
> >
> > In addition, CpuDxe actually calls InitializeCpuInterruptHandlers() which covers
> > the
> > functionalities of InitializeCpuExceptionHandlers() (its settings will be
> > overwritten).
> > If we want AP to initialize interrupt and exception individually, maybe we
> should
> > let AP call InitializeCpuInterruptHandlers() instead.
> >
> > > -----Original Message-----
> > > From: Yao, Jiewen
> > > Sent: Thursday, November 23, 2017 2:16 PM
> > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > > Kinney, Michael D <michael.d.kinney@intel.com>
> > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack
> > > switch support
> > >
> > > Here is my thought for 1)
> > >
> > > 1.1) We must provide the InitializeCpuExceptionStackSwitchHandlers()
> > > implementation in Pei instance and Smm instance.
> > >
> > > The basic requirement is a library instance must provide symbol for functions
> > > declared in header file.
> > > It is ok to return unsupported. But we MUST provide the symbol.
> > >
> > > 1.2) For SMM, I think our ultimate goal is to remove SMM specific stack
> guard,
> > > and use the common one. Duplicating code is completely unnecessary, and it
> is
> > > easy to introduce bug. And unfortunately, we already have bug in existing
> > SMM
> > > exception handler. -- That is a good reason to remove duplication.
> > >
> > > Again, it is not necessary to do it in this patch. I am totally OK to do it in
> > another
> > > patch.
> > >
> > > 1.3) For PEI, I do not think we can use current way to allocate stack in data
> > > section, because it might be readonly in pre-mem phase. We must use some
> > > other way.
> > >
> > > 1.4) I believe this patch has a hidden assumption is that:
> > > InitializeCpuExceptionHandlers() won't be called by multiple APs.
> > > If 2 or more APs call the it at same time, it might be broken because you use
> > > mNewStack for all the callers....
> > > Is that right?
> > >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > >
> > > > -----Original Message-----
> > > > From: Wang, Jian J
> > > > Sent: Thursday, November 23, 2017 2:06 PM
> > > > To: Yao, Jiewen <jiewen.yao@intel.com>; edk2-devel@lists.01.org
> > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > > Kinney,
> > > > Michael D <michael.d.kinney@intel.com>
> > > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> stack
> > > > switch support
> > > >
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Yao, Jiewen
> > > > > Sent: Thursday, November 23, 2017 1:50 PM
> > > > > To: Wang, Jian J <jian.j.wang@intel.com>; edk2-devel@lists.01.org
> > > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > > > > Kinney, Michael D <michael.d.kinney@intel.com>
> > > > > Subject: RE: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> > stack
> > > > > switch support
> > > > >
> > > > > Some thought:
> > > > >
> > > > > 1) I found InitializeCpuExceptionStackSwitchHandlers() is only
> implemented
> > > in
> > > > > DxeException.c.
> > > > > What about Pei/Smm instance?
> > > > >
> > > > > I think it is OK to not implement it at this moment. But we need make sure
> > no
> > > > > architecture issue if we want to enable it some time later.
> > > > >
> > > > Like what we discussed before, this series of patch is for Stack Guard
> feature
> > > > which
> > > > is only available for DXE (because Stack Guard needs paging to work). Stack
> > > > switch
> > > > is enabled for the sake of Stack Guard feature. So I think it's enough to
> > > > implement
> > > > it in DxeException.c. In addition, SMM has its own implementation of stack
> > > guard
> > > > and stack switch. It's not necessary to do it again.
> > > >
> > > > I agree with you that we should merge those common code but I think we
> > > should
> > > > do
> > > > it in a separate patch series since it's not Stack Guard relevant. And I've
> > > removed
> > > > all architecture issues I can think of. Current stack switch initialization
> should
> > > work
> > > > for both PEI and SMM as well.
> > > >
> > > > > 2) #define IA32_GDT_TYPE_TSS 0x9
> > > > > This is generic, can we move to BaseLib.h?
> > > > >
> > > > >
> > > > > Thank you
> > > > > Yao Jiewen
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Wang, Jian J
> > > > > > Sent: Wednesday, November 22, 2017 4:46 PM
> > > > > > To: edk2-devel@lists.01.org
> > > > > > Cc: Zeng, Star <star.zeng@intel.com>; Dong, Eric
> <eric.dong@intel.com>;
> > > Yao,
> > > > > > Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
> > > > > > <michael.d.kinney@intel.com>
> > > > > > Subject: [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add
> stack
> > > > > switch
> > > > > > support
> > > > > >
> > > > > > > v2:
> > > > > > > a. Move common TSS structure and API definitions to BaseLib.h
> > > > > > > b. Add EXCEPTION_STACK_SWITCH_DATA to convery data used
> to
> > > > setup
> > > > > > stack
> > > > > > > switch. This can avoid allocating memory for it in this library.
> > > > > > > c. Add globals to reserve memory for stack switch initialized in
> early
> > > > > > > phase of DXE core.
> > > > > > > d. Remove the filter code used to exclude boot modes which
> doesn't
> > > > > > support
> > > > > > > memory allocation because those memory can passed in by
> > > > parameter
> > > > > > now.
> > > > > > > e. Remove the nasm macro to define exception handler one by
> one
> > > > and
> > > > > > add a
> > > > > > > function to return the start address of each handler.
> > > > > >
> > > > > > If Stack Guard is enabled and there's really a stack overflow happened
> > > during
> > > > > > boot, a Page Fault exception will be triggered. Because the stack is out
> of
> > > > > > usage, the exception handler, which shares the stack with normal UEFI
> > > driver,
> > > > > > cannot be executed and cannot dump the processor information.
> > > > > >
> > > > > > Without those information, it's very difficult for the BIOS developers
> > locate
> > > > > > the root cause of stack overflow. And without a workable stack, the
> > > > developer
> > > > > > cannot event use single step to debug the UEFI driver with JTAG
> debugger.
> > > > > >
> > > > > > In order to make sure the exception handler to execute normally after
> > > stack
> > > > > > overflow. We need separate stacks for exception handlers in case of
> > > unusable
> > > > > > stack.
> > > > > >
> > > > > > IA processor allows to switch to a new stack during handling interrupt
> > and
> > > > > > exception. But X64 and IA32 provides different ways to make it. X64
> > > provides
> > > > > > interrupt stack table (IST) to allow maximum 7 different exceptions to
> > have
> > > > > > new stack for its handler. IA32 doesn't have IST mechanism and can
> only
> > > use
> > > > > > task gate to do it since task switch allows to load a new stack through its
> > > > > > task-state segment (TSS).
> > > > > >
> > > > > > Cc: Star Zeng <star.zeng@intel.com>
> > > > > > Cc: Eric Dong <eric.dong@intel.com>
> > > > > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > > > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > > > > Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
> > > > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > > > Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
> > > > > > ---
> > > > > > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 50 +++
> > > > > > .../DxeCpuExceptionHandlerLib.inf | 6 +
> > > > > > .../Library/CpuExceptionHandlerLib/DxeException.c | 53 ++-
> > > > > > .../Ia32/ArchExceptionHandler.c | 167
> +++++++++
> > > > > > .../Ia32/ArchInterruptDefs.h | 8 +
> > > > > > .../Ia32/ExceptionTssEntryAsm.nasm | 398
> > > > > > +++++++++++++++++++++
> > > > > > .../PeiCpuExceptionHandlerLib.inf | 1 +
> > > > > > .../SecPeiCpuExceptionHandlerLib.inf | 1 +
> > > > > > .../SmmCpuExceptionHandlerLib.inf | 1 +
> > > > > > .../X64/ArchExceptionHandler.c | 133
> +++++++
> > > > > > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 +
> > > > > > 11 files changed, 820 insertions(+), 1 deletion(-)
> > > > > > create mode 100644
> > > > > >
> > > > >
> > > >
> > >
> >
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
> > > > > >
> > > > > > diff --git
> > > > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > > index 740a58828b..30334105d2 100644
> > > > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > > +++
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
> > > > > > @@ -48,6 +48,32 @@
> > > > > > 0xb21d9148, 0x9211, 0x4d8f, { 0xad, 0xd3, 0x66, 0xb1, 0x89,
> 0xc9,
> > 0x2c,
> > > > > 0x83 }
> > > > > > \
> > > > > > }
> > > > > >
> > > > > > +#define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
> > > > > > + FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
> > > > > > +
> > > > > > +#define CPU_STACK_SWITCH_EXCEPTION_LIST \
> > > > > > + FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
> > > > > > +
> > > > > > +#define CPU_KNOWN_GOOD_STACK_SIZE \
> > > > > > + FixedPcdGet32 (PcdCpuKnownGoodStackSize)
> > > > > > +
> > > > > > +#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE +
> > > > > CPU_TSS_SIZE)
> > > > > > +
> > > > > > +#define IA32_GDT_TYPE_TSS 0x9
> > > > > > +#define IA32_GDT_ALIGNMENT 8
> > > > > > +
> > > > > > +typedef struct {
> > > > > > + UINTN StackTop;
> > > > > > + UINTN StackSize;
> > > > > > + UINT8 *Exceptions;
> > > > > > + UINTN ExceptionNumber;
> > > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > > + IA32_SEGMENT_DESCRIPTOR *GdtTable;
> > > > > > + UINTN GdtSize;
> > > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > > +} EXCEPTION_STACK_SWITCH_DATA;
> > > > > > +
> > > > > > //
> > > > > > // Record exception handler information
> > > > > > //
> > > > > > @@ -288,5 +314,29 @@ CommonExceptionHandlerWorker (
> > > > > > IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
> > > > > > );
> > > > > >
> > > > > > +/**
> > > > > > + Setup separate stack for specific exceptions.
> > > > > > +
> > > > > > + @param[in] IdtTable IDT table base.
> > > > > > +**/
> > > > > > +EFI_STATUS
> > > > > > +EFIAPI
> > > > > > +ArchSetupExcpetionStack (
> > > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > > + );
> > > > > > +
> > > > > > +/**
> > > > > > + Return address map of exception handler template so that C code
> can
> > > > > > generate
> > > > > > + exception tables. The template is only for exceptions using task gate
> > > > instead
> > > > > > + of interrupt gate.
> > > > > > +
> > > > > > + @param AddressMap Pointer to a buffer where the address map
> is
> > > > > > returned.
> > > > > > +**/
> > > > > > +VOID
> > > > > > +EFIAPI
> > > > > > +AsmGetTssTemplateMap (
> > > > > > + OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
> > > > > > + );
> > > > > > +
> > > > > > #endif
> > > > > >
> > > > > > diff --git
> > > > > >
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > > index f4a8d01c80..58e55a8a2e 100644
> > > > > > ---
> > > > > >
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > > +++
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
> > > > > > @@ -30,6 +30,7 @@
> > > > > > [Sources.Ia32]
> > > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > > Ia32/ExceptionHandlerAsm.S
> > > > > > Ia32/ArchExceptionHandler.c
> > > > > > Ia32/ArchInterruptDefs.h
> > > > > > @@ -47,6 +48,11 @@
> > > > > > PeiDxeSmmCpuException.c
> > > > > > DxeException.c
> > > > > >
> > > > > > +[Pcd]
> > > > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
> > > > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
> > > > > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize
> > > > > > +
> > > > > > [Packages]
> > > > > > MdePkg/MdePkg.dec
> > > > > > MdeModulePkg/MdeModulePkg.dec
> > > > > > diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > > index 31febec976..c0b2c615aa 100644
> > > > > > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> > > > > > @@ -25,6 +25,10 @@ UINTN
> > > > mEnabledInterruptNum =
> > > > > > 0;
> > > > > >
> > > > > > EXCEPTION_HANDLER_DATA mExceptionHandlerData;
> > > > > >
> > > > > > +UINT8
> > > > > > mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
> > > > > > +
> > > > CPU_KNOWN_GOOD_STACK_SIZE]
> > > > > > = {0};
> > > > > > +UINT8 mNewGdt[CPU_TSS_GDT_SIZE] =
> {0};
> > > > > > +
> > > > > > /**
> > > > > > Common exception handler.
> > > > > >
> > > > > > @@ -63,10 +67,34 @@ InitializeCpuExceptionHandlers (
> > > > > > IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
> > > > > > )
> > > > > > {
> > > > > > + EFI_STATUS Status;
> > > > > > + EXCEPTION_STACK_SWITCH_DATA StackSwitchData;
> > > > > > + IA32_DESCRIPTOR Idtr;
> > > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > > +
> > > > > > mExceptionHandlerData.ReservedVectors =
> > > > > > mReservedVectorsData;
> > > > > > mExceptionHandlerData.ExternalInterruptHandler =
> > > > > > mExternalInterruptHandlerTable;
> > > > > > InitializeSpinLock
> (&mExceptionHandlerData.DisplayMessageSpinLock);
> > > > > > - return InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > > > &mExceptionHandlerData);
> > > > > > + Status = InitializeCpuExceptionHandlersWorker (VectorInfo,
> > > > > > &mExceptionHandlerData);
> > > > > > + if (!EFI_ERROR (Status) && PcdGetBool (PcdCpuStackGuard)) {
> > > > > > + AsmReadIdtr (&Idtr);
> > > > > > + AsmReadGdtr (&Gdtr);
> > > > > > +
> > > > > > + StackSwitchData.StackTop = (UINTN)mNewStack;
> > > > > > + StackSwitchData.StackSize = CPU_KNOWN_GOOD_STACK_SIZE;
> > > > > > + StackSwitchData.Exceptions =
> CPU_STACK_SWITCH_EXCEPTION_LIST;
> > > > > > + StackSwitchData.ExceptionNumber =
> > > > > > CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> > > > > > + StackSwitchData.IdtTable = (IA32_IDT_GATE_DESCRIPTOR
> *)Idtr.Base;
> > > > > > + StackSwitchData.GdtTable = (IA32_SEGMENT_DESCRIPTOR
> > > > *)mNewGdt;
> > > > > > + StackSwitchData.GdtSize = sizeof (mNewGdt);
> > > > > > + StackSwitchData.TssDesc = (IA32_TSS_DESCRIPTOR *)(mNewGdt
> +
> > > > > > Gdtr.Limit + 1);
> > > > > > + StackSwitchData.Tss = (IA32_TASK_STATE_SEGMENT
> *)(mNewGdt +
> > > > > > Gdtr.Limit + 1 +
> > > > > > +
> > > > > > CPU_TSS_DESC_SIZE);
> > > > > > + Status = InitializeCpuExceptionStackSwitchHandlers (
> > > > > > + &StackSwitchData
> > > > > > + );
> > > > > > + }
> > > > > > + return Status;
> > > > > > }
> > > > > >
> > > > > > /**
> > > > > > @@ -197,3 +225,26 @@ RegisterCpuInterruptHandler (
> > > > > > {
> > > > > > return RegisterCpuInterruptHandlerWorker (InterruptType,
> > > > InterruptHandler,
> > > > > > &mExceptionHandlerData);
> > > > > > }
> > > > > > +
> > > > > > +/**
> > > > > > + Setup separate stack for given exceptions. This is required by
> > > > > > + PcdCpuStackGuard feature.
> > > > > > +
> > > > > > + Note: For IA32 processor, StackSwitchData is a required parameter.
> > > > > > +
> > > > > > + @param[in] StackSwitchData Pointer to data required for
> setuping
> > > > up
> > > > > > + stack switch.
> > > > > > +
> > > > > > + @retval EFI_SUCCESS The exceptions have been
> > > > successfully
> > > > > > + initialized.
> > > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains
> invalid
> > > > > > content.
> > > > > > +
> > > > > > +**/
> > > > > > +EFI_STATUS
> > > > > > +EFIAPI
> > > > > > +InitializeCpuExceptionStackSwitchHandlers (
> > > > > > + IN VOID *StackSwitchData OPTIONAL
> > > > > > + )
> > > > > > +{
> > > > > > + return ArchSetupExcpetionStack (StackSwitchData);
> > > > > > +}
> > > > > > diff --git
> > > > > >
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > > index f2c39eb193..0aaf794795 100644
> > > > > > ---
> > > > >
> > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > > +++
> > > > > >
> > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> > > > > > @@ -107,6 +107,173 @@ ArchRestoreExceptionContext (
> > > > > > SystemContext.SystemContextIa32->ExceptionData =
> > > > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > > > }
> > > > > >
> > > > > > +/**
> > > > > > + Setup separate stack for given exceptions.
> > > > > > +
> > > > > > + @param[in] StackSwitchData Pointer to data required for
> > > > setuping
> > > > > > up
> > > > > > + stack switch.
> > > > > > + @retval EFI_SUCCESS The exceptions have been
> > > > successfully
> > > > > > + initialized.
> > > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains
> invalid
> > > > > > content.
> > > > > > +
> > > > > > +**/
> > > > > > +EFI_STATUS
> > > > > > +EFIAPI
> > > > > > +ArchSetupExcpetionStack (
> > > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > > + )
> > > > > > +{
> > > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > > + IA32_DESCRIPTOR Idtr;
> > > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > > + UINTN StackTop;
> > > > > > + UINTN Index;
> > > > > > + UINTN Vector;
> > > > > > + UINTN TssBase;
> > > > > > + UINTN GdtSize;
> > > > > > + EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
> > > > > > +
> > > > > > + if (StackSwitchData == NULL ||
> > > > > > + StackSwitchData->StackTop == 0 ||
> > > > > > + StackSwitchData->StackSize == 0 ||
> > > > > > + StackSwitchData->Exceptions == NULL ||
> > > > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > > > + StackSwitchData->GdtTable == NULL ||
> > > > > > + StackSwitchData->IdtTable == NULL ||
> > > > > > + StackSwitchData->TssDesc == NULL ||
> > > > > > + StackSwitchData->Tss == NULL) {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // The caller is responsible for that the GDT table, no matter the
> > existing
> > > > > > + // one or newly allocated, has enough space to hold descriptors for
> > > > > exception
> > > > > > + // task-state segments.
> > > > > > + //
> > > > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT
> -
> > > 1)) !=
> > > > 0)
> > > > > {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > > > >GdtTable))
> > > > > > {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > > StackSwitchData->GdtSize))
> > > > > > {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > > > + sizeof (IA32_TSS_DESCRIPTOR) *
> > > > > > + (StackSwitchData->ExceptionNumber + 1);
> > > > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // Initialize new GDT table and/or IDT table, if any
> > > > > > + //
> > > > > > + AsmReadIdtr (&Idtr);
> > > > > > + AsmReadGdtr (&Gdtr);
> > > > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base,
> Gdtr.Limit
> > +
> > > > 1);
> > > > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > > > + Gdtr.Limit = (UINT16)StackSwitchData->GdtSize - 1;
> > > > > > + }
> > > > > > +
> > > > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // Fixup current task descriptor. Task-state segment for current task
> > will
> > > > > > + // be filled by processor during task switching.
> > > > > > + //
> > > > > > + TssDesc = StackSwitchData->TssDesc;
> > > > > > + Tss = StackSwitchData->Tss;
> > > > > > +
> > > > > > + TssBase = (UINTN)Tss;
> > > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) -
> 1;
> > > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > > + TssDesc->Bits.P = 1;
> > > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > > > +
> > > > > > + //
> > > > > > + // Fixup exception task descriptor and task-state segment
> > > > > > + //
> > > > > > + AsmGetTssTemplateMap (&TemplateMap);
> > > > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > > > CPU_STACK_ALIGNMENT);
> > > > > > + IdtTable = StackSwitchData->IdtTable;
> > > > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber;
> ++Index) {
> > > > > > + TssDesc += 1;
> > > > > > + Tss += 1;
> > > > > > +
> > > > > > + //
> > > > > > + // Fixup TSS descriptor
> > > > > > + //
> > > > > > + TssBase = (UINTN)Tss;
> > > > > > +
> > > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) -
> 1;
> > > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > > + TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
> > > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > > + TssDesc->Bits.P = 1;
> > > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > > + TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
> > > > > > +
> > > > > > + //
> > > > > > + // Fixup TSS
> > > > > > + //
> > > > > > + Vector = StackSwitchData->Exceptions[Index];
> > > > > > + Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
> > > > > > + + Vector *
> > > > > > TemplateMap.ExceptionStubHeaderSize);
> > > > > > + Tss->EFLAGS = 0x2;
> > > > > > + Tss->ESP = StackTop;
> > > > > > + Tss->CR3 = AsmReadCr3 ();
> > > > > > + Tss->ES = AsmReadEs ();
> > > > > > + Tss->CS = AsmReadCs ();
> > > > > > + Tss->SS = AsmReadSs ();
> > > > > > + Tss->DS = AsmReadDs ();
> > > > > > + Tss->FS = AsmReadFs ();
> > > > > > + Tss->GS = AsmReadGs ();
> > > > > > +
> > > > > > + StackTop -= StackSwitchData->StackSize;
> > > > > > +
> > > > > > + //
> > > > > > + // Update IDT to use Task Gate for given exception
> > > > > > + //
> > > > > > + IdtTable[Vector].Bits.OffsetLow = 0;
> > > > > > + IdtTable[Vector].Bits.Selector = (UINT16)((UINTN)TssDesc -
> > > > Gdtr.Base);
> > > > > > + IdtTable[Vector].Bits.Reserved_0 = 0;
> > > > > > + IdtTable[Vector].Bits.GateType = IA32_IDT_GATE_TYPE_TASK;
> > > > > > + IdtTable[Vector].Bits.OffsetHigh = 0;
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // Publish GDT
> > > > > > + //
> > > > > > + AsmWriteGdtr (&Gdtr);
> > > > > > +
> > > > > > + //
> > > > > > + // Load current task
> > > > > > + //
> > > > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc -
> Gdtr.Base));
> > > > > > +
> > > > > > + //
> > > > > > + // Publish IDT
> > > > > > + //
> > > > > > + AsmWriteIdtr (&Idtr);
> > > > > > +
> > > > > > + return EFI_SUCCESS;
> > > > > > +}
> > > > > > +
> > > > > > /**
> > > > > > Display processor context.
> > > > > >
> > > > > > diff --git
> > > > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > > index a8d3556a80..d9ded5977f 100644
> > > > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > > +++
> > > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
> > > > > > @@ -41,4 +41,12 @@ typedef struct {
> > > > > > UINT8
> HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > > > } RESERVED_VECTORS_DATA;
> > > > > >
> > > > > > +#define CPU_TSS_DESC_SIZE \
> > > > > > + (sizeof (IA32_TSS_DESCRIPTOR) * \
> > > > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > > > +
> > > > > > +#define CPU_TSS_SIZE \
> > > > > > + (sizeof (IA32_TASK_STATE_SEGMENT) * \
> > > > > > + (PcdGetSize (PcdCpuStackSwitchExceptionList) + 1))
> > > > > > +
> > > > > > #endif
> > > > > > diff --git
> > > > > >
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > > m
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > > m
> > > > > > new file mode 100644
> > > > > > index 0000000000..62bcedea1a
> > > > > > --- /dev/null
> > > > > > +++
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nas
> > > > > > m
> > > > > > @@ -0,0 +1,398 @@
> > > > > > +;------------------------------------------------------------------------------ ;
> > > > > > +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> > > > > > +; This program and the accompanying materials
> > > > > > +; are licensed and made available under the terms and conditions of
> the
> > > BSD
> > > > > > License
> > > > > > +; which accompanies this distribution. The full text of the license may
> > be
> > > > > found
> > > > > > at
> > > > > > +; http://opensource.org/licenses/bsd-license.php.
> > > > > > +;
> > > > > > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> > IS"
> > > > > BASIS,
> > > > > > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> > > > > EXPRESS
> > > > > > OR IMPLIED.
> > > > > > +;
> > > > > > +; Module Name:
> > > > > > +;
> > > > > > +; ExceptionTssEntryAsm.Asm
> > > > > > +;
> > > > > > +; Abstract:
> > > > > > +;
> > > > > > +; IA32 CPU Exception Handler with Separate Stack
> > > > > > +;
> > > > > > +; Notes:
> > > > > > +;
> > > > > > +;------------------------------------------------------------------------------
> > > > > > +
> > > > > > +;
> > > > > > +; IA32 TSS Memory Layout Description
> > > > > > +;
> > > > > > +struc IA32_TSS
> > > > > > + resw 1
> > > > > > + resw 1
> > > > > > + .ESP0: resd 1
> > > > > > + .SS0: resw 1
> > > > > > + resw 1
> > > > > > + .ESP1: resd 1
> > > > > > + .SS1: resw 1
> > > > > > + resw 1
> > > > > > + .ESP2: resd 1
> > > > > > + .SS2: resw 1
> > > > > > + resw 1
> > > > > > + ._CR3: resd 1
> > > > > > + .EIP: resd 1
> > > > > > + .EFLAGS: resd 1
> > > > > > + ._EAX: resd 1
> > > > > > + ._ECX: resd 1
> > > > > > + ._EDX: resd 1
> > > > > > + ._EBX: resd 1
> > > > > > + ._ESP: resd 1
> > > > > > + ._EBP: resd 1
> > > > > > + ._ESI: resd 1
> > > > > > + ._EDI: resd 1
> > > > > > + ._ES: resw 1
> > > > > > + resw 1
> > > > > > + ._CS: resw 1
> > > > > > + resw 1
> > > > > > + ._SS: resw 1
> > > > > > + resw 1
> > > > > > + ._DS: resw 1
> > > > > > + resw 1
> > > > > > + ._FS: resw 1
> > > > > > + resw 1
> > > > > > + ._GS: resw 1
> > > > > > + resw 1
> > > > > > + .LDT: resw 1
> > > > > > + resw 1
> > > > > > + resw 1
> > > > > > + resw 1
> > > > > > +endstruc
> > > > > > +
> > > > > > +;
> > > > > > +; CommonExceptionHandler()
> > > > > > +;
> > > > > > +extern ASM_PFX(CommonExceptionHandler)
> > > > > > +
> > > > > > +SECTION .data
> > > > > > +
> > > > > > +SECTION .text
> > > > > > +
> > > > > > +ALIGN 8
> > > > > > +
> > > > > > +;
> > > > > > +; Exception handler stub table
> > > > > > +;
> > > > > > +AsmExceptionEntryBegin:
> > > > > > +%assign Vector 0
> > > > > > +%rep 32
> > > > > > +
> > > > > > +DoIret%[Vector]:
> > > > > > + iretd
> > > > > > +ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
> > > > > > + db 0x6a ; push #VectorNum
> > > > > > + db %[Vector]
> > > > > > + mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > > > + call eax
> > > > > > + mov esp, eax ; Restore stack top
> > > > > > + jmp DoIret%[Vector]
> > > > > > +
> > > > > > +%assign Vector Vector+1
> > > > > > +%endrep
> > > > > > +AsmExceptionEntryEnd:
> > > > > > +
> > > > > > +;
> > > > > > +; Common part of exception handler
> > > > > > +;
> > > > > > +global ASM_PFX(CommonTaskSwtichEntryPoint)
> > > > > > +ASM_PFX(CommonTaskSwtichEntryPoint):
> > > > > > + ;
> > > > > > + ; Stack:
> > > > > > + ; +---------------------+ <-- EBP - 8
> > > > > > + ; + TSS Base +
> > > > > > + ; +---------------------+ <-- EBP - 4
> > > > > > + ; + CPUID.EDX +
> > > > > > + ; +---------------------+ <-- EBP
> > > > > > + ; + EIP +
> > > > > > + ; +---------------------+ <-- EBP + 4
> > > > > > + ; + Vector Number +
> > > > > > + ; +---------------------+ <-- EBP + 8
> > > > > > + ; + Error Code +
> > > > > > + ; +---------------------+
> > > > > > + ;
> > > > > > +
> > > > > > + mov ebp, esp ; Stack frame
> > > > > > +
> > > > > > +; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
> > > > > > + mov eax, 1
> > > > > > + cpuid
> > > > > > + push edx
> > > > > > +
> > > > > > +; Get TSS base of interrupted task through PreviousTaskLink field in
> > > > > > +; current TSS base
> > > > > > + sub esp, 8
> > > > > > + sgdt [esp + 2]
> > > > > > + mov eax, [esp + 4] ; GDT base
> > > > > > + add esp, 8
> > > > > > +
> > > > > > + xor ebx, ebx
> > > > > > + str bx ; Current TR
> > > > > > +
> > > > > > + mov ecx, [eax + ebx + 2]
> > > > > > + shl ecx, 8
> > > > > > + mov cl, [eax + ebx + 7]
> > > > > > + ror ecx, 8 ; ecx = Current TSS base
> > > > > > + push ecx ; keep it in stack for
> later use
> > > > > > +
> > > > > > + movzx ebx, word [ecx] ; Previous Task Link
> > > > > > + mov ecx, [eax + ebx + 2]
> > > > > > + shl ecx, 8
> > > > > > + mov cl, [eax + ebx + 7]
> > > > > > + ror ecx, 8 ; ecx = Previous TSS base
> > > > > > +
> > > > > > +;
> > > > > > +; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of
> > > > > > EFI_SYSTEM_CONTEXT_IA32
> > > > > > +; is 16-byte aligned
> > > > > > +;
> > > > > > + and esp, 0xfffffff0
> > > > > > + sub esp, 12
> > > > > > +
> > > > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > > > + push dword [ecx + IA32_TSS._EAX]
> > > > > > + push dword [ecx + IA32_TSS._ECX]
> > > > > > + push dword [ecx + IA32_TSS._EDX]
> > > > > > + push dword [ecx + IA32_TSS._EBX]
> > > > > > + push dword [ecx + IA32_TSS._ESP]
> > > > > > + push dword [ecx + IA32_TSS._EBP]
> > > > > > + push dword [ecx + IA32_TSS._ESI]
> > > > > > + push dword [ecx + IA32_TSS._EDI]
> > > > > > +
> > > > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > > > + movzx eax, word [ecx + IA32_TSS._SS]
> > > > > > + push eax
> > > > > > + movzx eax, word [ecx + IA32_TSS._CS]
> > > > > > + push eax
> > > > > > + movzx eax, word [ecx + IA32_TSS._DS]
> > > > > > + push eax
> > > > > > + movzx eax, word [ecx + IA32_TSS._ES]
> > > > > > + push eax
> > > > > > + movzx eax, word [ecx + IA32_TSS._FS]
> > > > > > + push eax
> > > > > > + movzx eax, word [ecx + IA32_TSS._GS]
> > > > > > + push eax
> > > > > > +
> > > > > > +;; UINT32 Eip;
> > > > > > + push dword [ecx + IA32_TSS.EIP]
> > > > > > +
> > > > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > > > + sub esp, 8
> > > > > > + sidt [esp]
> > > > > > + mov eax, [esp + 2]
> > > > > > + xchg eax, [esp]
> > > > > > + and eax, 0xFFFF
> > > > > > + mov [esp+4], eax
> > > > > > +
> > > > > > + sub esp, 8
> > > > > > + sgdt [esp]
> > > > > > + mov eax, [esp + 2]
> > > > > > + xchg eax, [esp]
> > > > > > + and eax, 0xFFFF
> > > > > > + mov [esp+4], eax
> > > > > > +
> > > > > > +;; UINT32 Ldtr, Tr;
> > > > > > + mov eax, ebx ; ebx still keeps selector of interrupted task
> > > > > > + push eax
> > > > > > + movzx eax, word [ecx + IA32_TSS.LDT]
> > > > > > + push eax
> > > > > > +
> > > > > > +;; UINT32 EFlags;
> > > > > > + push dword [ecx + IA32_TSS.EFLAGS]
> > > > > > +
> > > > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > > > + mov eax, cr4
> > > > > > + push eax ; push cr4 firstly
> > > > > > +
> > > > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > > > + jz .1
> > > > > > + or eax, BIT9 ; Set CR4.OSFXSR
> > > > > > +.1:
> > > > > > + test edx, BIT2 ; Test for Debugging Extensions support
> > > > > > + jz .2
> > > > > > + or eax, BIT3 ; Set CR4.DE
> > > > > > +.2:
> > > > > > + mov cr4, eax
> > > > > > +
> > > > > > + mov eax, cr3
> > > > > > + push eax
> > > > > > + mov eax, cr2
> > > > > > + push eax
> > > > > > + xor eax, eax
> > > > > > + push eax
> > > > > > + mov eax, cr0
> > > > > > + push eax
> > > > > > +
> > > > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > > > + mov eax, dr7
> > > > > > + push eax
> > > > > > + mov eax, dr6
> > > > > > + push eax
> > > > > > + mov eax, dr3
> > > > > > + push eax
> > > > > > + mov eax, dr2
> > > > > > + push eax
> > > > > > + mov eax, dr1
> > > > > > + push eax
> > > > > > + mov eax, dr0
> > > > > > + push eax
> > > > > > +
> > > > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > > > +;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
> > > > > > +;; when executing fxsave/fxrstor instruction
> > > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
> > > > > > + ; edx still contains result from CPUID
> above
> > > > > > + jz .3
> > > > > > + clts
> > > > > > + sub esp, 512
> > > > > > + mov edi, esp
> > > > > > + db 0xf, 0xae, 0x7 ;fxsave [edi]
> > > > > > +.3:
> > > > > > +
> > > > > > +;; UINT32 ExceptionData;
> > > > > > + push dword [ebp + 8]
> > > > > > +
> > > > > > +;; UEFI calling convention for IA32 requires that Direction flag in
> EFLAGs
> > is
> > > > > clear
> > > > > > + cld
> > > > > > +
> > > > > > +;; call into exception handler
> > > > > > + mov esi, ecx ; Keep TSS base to avoid
> overwrite
> > > > > > + mov eax, ASM_PFX(CommonExceptionHandler)
> > > > > > +
> > > > > > +;; Prepare parameter and call
> > > > > > + mov edx, esp
> > > > > > + push edx ; EFI_SYSTEM_CONTEXT
> > > > > > + push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector
> number)
> > > > > > +
> > > > > > + ;
> > > > > > + ; Call External Exception Handler
> > > > > > + ;
> > > > > > + call eax
> > > > > > + add esp, 8 ; Restore stack before calling
> > > > > > + mov ecx, esi ; Restore TSS base
> > > > > > +
> > > > > > +;; UINT32 ExceptionData;
> > > > > > + add esp, 4
> > > > > > +
> > > > > > +;; FX_SAVE_STATE_IA32 FxSaveState;
> > > > > > + mov edx, [ebp - 4] ; cpuid.edx
> > > > > > + test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
> > > > > > + jz .4
> > > > > > + mov esi, esp
> > > > > > + db 0xf, 0xae, 0xe ; fxrstor [esi]
> > > > > > +.4:
> > > > > > + add esp, 512
> > > > > > +
> > > > > > +;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
> > > > > > +;; Skip restoration of DRx registers to support debuggers
> > > > > > +;; that set breakpoints in interrupt/exception context
> > > > > > + add esp, 4 * 6
> > > > > > +
> > > > > > +;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
> > > > > > + pop eax
> > > > > > + mov cr0, eax
> > > > > > + add esp, 4 ; not for Cr1
> > > > > > + pop eax
> > > > > > + mov cr2, eax
> > > > > > + pop eax
> > > > > > + mov dword [ecx + IA32_TSS._CR3], eax
> > > > > > + pop eax
> > > > > > + mov cr4, eax
> > > > > > +
> > > > > > +;; UINT32 EFlags;
> > > > > > + pop dword [ecx + IA32_TSS.EFLAGS]
> > > > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > > > + btr ebx, 9 ; Do 'cli'
> > > > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx
> > > > > > +
> > > > > > +;; UINT32 Ldtr, Tr;
> > > > > > +;; UINT32 Gdtr[2], Idtr[2];
> > > > > > +;; Best not let anyone mess with these particular registers...
> > > > > > + add esp, 24
> > > > > > +
> > > > > > +;; UINT32 Eip;
> > > > > > + pop dword [ecx + IA32_TSS.EIP]
> > > > > > +
> > > > > > +;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
> > > > > > +;; NOTE - modified segment registers could hang the debugger... We
> > > > > > +;; could attempt to insulate ourselves against this possibility,
> > > > > > +;; but that poses risks as well.
> > > > > > +;;
> > > > > > + pop eax
> > > > > > +o16 mov [ecx + IA32_TSS._GS], ax
> > > > > > + pop eax
> > > > > > +o16 mov [ecx + IA32_TSS._FS], ax
> > > > > > + pop eax
> > > > > > +o16 mov [ecx + IA32_TSS._ES], ax
> > > > > > + pop eax
> > > > > > +o16 mov [ecx + IA32_TSS._DS], ax
> > > > > > + pop eax
> > > > > > +o16 mov [ecx + IA32_TSS._CS], ax
> > > > > > + pop eax
> > > > > > +o16 mov [ecx + IA32_TSS._SS], ax
> > > > > > +
> > > > > > +;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
> > > > > > + pop dword [ecx + IA32_TSS._EDI]
> > > > > > + pop dword [ecx + IA32_TSS._ESI]
> > > > > > + add esp, 4 ; not for ebp
> > > > > > + add esp, 4 ; not for esp
> > > > > > + pop dword [ecx + IA32_TSS._EBX]
> > > > > > + pop dword [ecx + IA32_TSS._EDX]
> > > > > > + pop dword [ecx + IA32_TSS._ECX]
> > > > > > + pop dword [ecx + IA32_TSS._EAX]
> > > > > > +
> > > > > > +; Set single step DB# to allow debugger to able to go back to the EIP
> > > > > > +; where the exception is triggered.
> > > > > > +
> > > > > > +;; Create return context for iretd in stub function
> > > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > > > pointer
> > > > > > + mov ebx, dword [ecx + IA32_TSS.EIP]
> > > > > > + mov [eax - 0xc], ebx ; create EIP in
> old
> > > > stack
> > > > > > + movzx ebx, word [ecx + IA32_TSS._CS]
> > > > > > + mov [eax - 0x8], ebx ; create CS in
> old stack
> > > > > > + mov ebx, dword [ecx + IA32_TSS.EFLAGS]
> > > > > > + bts ebx, 8
> > > > > > + mov [eax - 0x4], ebx ; create eflags
> in old
> > > > stack
> > > > > > + mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags
> in old
> > > > TSS
> > > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack
> > > > pointer
> > > > > > + sub eax, 0xc ; minus 12
> byte
> > > > > > + mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack
> > > > pointer
> > > > > > +
> > > > > > +;; Replace the EIP of interrupted task with stub function
> > > > > > + mov eax, ASM_PFX(SingleStepStubFunction)
> > > > > > + mov dword [ecx + IA32_TSS.EIP], eax
> > > > > > +
> > > > > > + mov ecx, [ebp - 8] ; Get current
> TSS base
> > > > > > + mov eax, dword [ecx + IA32_TSS._ESP] ; Return
> current stack
> > > > top
> > > > > > + mov esp, ebp
> > > > > > +
> > > > > > + ret
> > > > > > +
> > > > > > +global ASM_PFX(SingleStepStubFunction)
> > > > > > +ASM_PFX(SingleStepStubFunction):
> > > > > > +;
> > > > > > +; we need clean TS bit in CR0 to execute
> > > > > > +; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
> > > > > > +;
> > > > > > + clts
> > > > > > + iretd
> > > > > > +
> > > > > > +global ASM_PFX(AsmGetTssTemplateMap)
> > > > > > +ASM_PFX(AsmGetTssTemplateMap):
> > > > > > + push ebp ; C prolog
> > > > > > + mov ebp, esp
> > > > > > + pushad
> > > > > > +
> > > > > > + mov ebx, dword [ebp + 0x8]
> > > > > > + mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
> > > > > > + mov dword [ebx + 0x4], (AsmExceptionEntryEnd -
> > > > AsmExceptionEntryBegin)
> > > > > > / 32
> > > > > > + mov dword [ebx + 0x8], 0
> > > > > > +
> > > > > > + popad
> > > > > > + pop ebp
> > > > > > + ret
> > > > > > +
> > > > > > diff --git
> > > > > >
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > >
> > > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > > index 75443288a9..4c0d435136 100644
> > > > > > ---
> > > > > >
> > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > > +++
> > > > > >
> > > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> > > > > > @@ -30,6 +30,7 @@
> > > > > > [Sources.Ia32]
> > > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > > Ia32/ExceptionHandlerAsm.S
> > > > > > Ia32/ArchExceptionHandler.c
> > > > > > Ia32/ArchInterruptDefs.h
> > > > > > diff --git
> > > > > >
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > > nf
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > > nf
> > > > > > index d70a99c100..e5c03c16c9 100644
> > > > > > ---
> > > > > >
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > > nf
> > > > > > +++
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.i
> > > > > > nf
> > > > > > @@ -30,6 +30,7 @@
> > > > > > [Sources.Ia32]
> > > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > > Ia32/ExceptionHandlerAsm.S
> > > > > > Ia32/ArchExceptionHandler.c
> > > > > > Ia32/ArchInterruptDefs.h
> > > > > > diff --git
> > > > > >
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.in
> f
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.in
> f
> > > > > > index 634ffcb21d..56b875b7c8 100644
> > > > > > ---
> > > > > >
> > > > >
> > > >
> > >
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.in
> f
> > > > > > +++
> > > > > >
> > > > >
> > > >
> > >
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.in
> f
> > > > > > @@ -30,6 +30,7 @@
> > > > > > [Sources.Ia32]
> > > > > > Ia32/ExceptionHandlerAsm.asm
> > > > > > Ia32/ExceptionHandlerAsm.nasm
> > > > > > + Ia32/ExceptionTssEntryAsm.nasm
> > > > > > Ia32/ExceptionHandlerAsm.S
> > > > > > Ia32/ArchExceptionHandler.c
> > > > > > Ia32/ArchInterruptDefs.h
> > > > > > diff --git
> > > > > >
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > >
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > > index 65f0cff680..214aafcc13 100644
> > > > > > ---
> > > > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > > +++
> > > > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> > > > > > @@ -112,6 +112,139 @@ ArchRestoreExceptionContext (
> > > > > > SystemContext.SystemContextX64->ExceptionData =
> > > > > > ReservedVectors[ExceptionType].ExceptionData;
> > > > > > }
> > > > > >
> > > > > > +/**
> > > > > > + Setup separate stack for given exceptions.
> > > > > > +
> > > > > > + @param[in] StackSwitchData Pointer to data required for
> setuping
> > > > up
> > > > > > + stack switch.
> > > > > > +
> > > > > > + @retval EFI_SUCCESS The exceptions have been
> > > > successfully
> > > > > > + initialized.
> > > > > > + @retval EFI_INVALID_PARAMETER StackSwitchData contains
> invalid
> > > > > > content.
> > > > > > +
> > > > > > +**/
> > > > > > +EFI_STATUS
> > > > > > +EFIAPI
> > > > > > +ArchSetupExcpetionStack (
> > > > > > + IN EXCEPTION_STACK_SWITCH_DATA *StackSwitchData
> > > > > > + )
> > > > > > +{
> > > > > > + IA32_DESCRIPTOR Gdtr;
> > > > > > + IA32_DESCRIPTOR Idtr;
> > > > > > + IA32_IDT_GATE_DESCRIPTOR *IdtTable;
> > > > > > + IA32_TSS_DESCRIPTOR *TssDesc;
> > > > > > + IA32_TASK_STATE_SEGMENT *Tss;
> > > > > > + UINTN StackTop;
> > > > > > + UINTN Index;
> > > > > > + UINTN TssBase;
> > > > > > + UINTN GdtSize;
> > > > > > +
> > > > > > + if (StackSwitchData == NULL ||
> > > > > > + StackSwitchData->StackTop == 0 ||
> > > > > > + StackSwitchData->StackSize == 0 ||
> > > > > > + StackSwitchData->Exceptions == NULL ||
> > > > > > + StackSwitchData->ExceptionNumber == 0 ||
> > > > > > + StackSwitchData->GdtTable == NULL ||
> > > > > > + StackSwitchData->IdtTable == NULL ||
> > > > > > + StackSwitchData->TssDesc == NULL ||
> > > > > > + StackSwitchData->Tss == NULL) {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // The caller is responsible for that the GDT table, no matter the
> > existing
> > > > > > + // one or newly allocated, has enough space to hold descriptors for
> > > > > exception
> > > > > > + // task-state segments.
> > > > > > + //
> > > > > > + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT
> -
> > > 1)) !=
> > > > 0)
> > > > > {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + if ((UINTN)StackSwitchData->TssDesc < (UINTN)(StackSwitchData-
> > > > > >GdtTable))
> > > > > > {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + if ((UINTN)StackSwitchData->TssDesc >=
> > > > > > + ((UINTN)(StackSwitchData->GdtTable) +
> > > > StackSwitchData->GdtSize))
> > > > > > {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + GdtSize = (UINTN)StackSwitchData->TssDesc -
> > > > > > + (UINTN)(StackSwitchData->GdtTable) +
> > > > > > + sizeof (IA32_TSS_DESCRIPTOR);
> > > > > > + if (GdtSize > StackSwitchData->GdtSize) {
> > > > > > + return EFI_INVALID_PARAMETER;
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // Initialize new GDT table and/or IDT table, if any
> > > > > > + //
> > > > > > + AsmReadIdtr (&Idtr);
> > > > > > + AsmReadGdtr (&Gdtr);
> > > > > > + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {
> > > > > > + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base,
> Gdtr.Limit
> > +
> > > > 1);
> > > > > > + Gdtr.Base = (UINTN)StackSwitchData->GdtTable;
> > > > > > + Gdtr.Limit = (UINT16)GdtSize - 1;
> > > > > > + }
> > > > > > +
> > > > > > + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {
> > > > > > + Idtr.Base = (UINTN)StackSwitchData->IdtTable;
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // Fixup current task descriptor. Task-state segment for current task
> > will
> > > > > > + // be filled by processor during task switching.
> > > > > > + //
> > > > > > + TssDesc = StackSwitchData->TssDesc;
> > > > > > + Tss = StackSwitchData->Tss;
> > > > > > +
> > > > > > + TssBase = (UINTN)Tss;
> > > > > > + TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) -
> 1;
> > > > > > + TssDesc->Bits.BaseLow = (UINT16)TssBase;
> > > > > > + TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
> > > > > > + TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
> > > > > > + TssDesc->Bits.P = 1;
> > > > > > + TssDesc->Bits.LimitHigh = 0;
> > > > > > + TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
> > > > > > + TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
> > > > > > +
> > > > > > + //
> > > > > > + // Fixup exception task descriptor and task-state segment
> > > > > > + //
> > > > > > + StackTop = StackSwitchData->StackTop - CPU_STACK_ALIGNMENT;
> > > > > > + StackTop = (UINTN)ALIGN_POINTER (StackTop,
> > > > CPU_STACK_ALIGNMENT);
> > > > > > + IdtTable = StackSwitchData->IdtTable;
> > > > > > + for (Index = 0; Index < StackSwitchData->ExceptionNumber;
> ++Index) {
> > > > > > + //
> > > > > > + // Fixup IST
> > > > > > + //
> > > > > > + Tss->IST[Index] = StackTop;
> > > > > > + StackTop -= StackSwitchData->StackSize;
> > > > > > +
> > > > > > + //
> > > > > > + // Set the IST field to enable corresponding IST
> > > > > > + //
> > > > > > + IdtTable[StackSwitchData->Exceptions[Index]].Bits.Reserved_0 =
> > > > > > (UINT8)(Index + 1);
> > > > > > + }
> > > > > > +
> > > > > > + //
> > > > > > + // Publish GDT
> > > > > > + //
> > > > > > + AsmWriteGdtr (&Gdtr);
> > > > > > +
> > > > > > + //
> > > > > > + // Load current task
> > > > > > + //
> > > > > > + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->TssDesc -
> Gdtr.Base));
> > > > > > +
> > > > > > + //
> > > > > > + // Publish IDT
> > > > > > + //
> > > > > > + AsmWriteIdtr (&Idtr);
> > > > > > +
> > > > > > + return EFI_SUCCESS;
> > > > > > +}
> > > > > > +
> > > > > > /**
> > > > > > Display CPU information.
> > > > > >
> > > > > > diff --git
> > > > > >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > > index 906480134a..c88be46286 100644
> > > > > > ---
> > > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > > +++
> > > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
> > > > > > @@ -43,4 +43,7 @@ typedef struct {
> > > > > > UINT8
> HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
> > > > > > } RESERVED_VECTORS_DATA;
> > > > > >
> > > > > > +#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
> > > > > > +#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
> > > > > > +
> > > > > > #endif
> > > > > > --
> > > > > > 2.14.1.windows.1
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2017-11-28 2:01 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-11-22 8:45 [PATCH v2 0/8] Implement stack guard feature Jian J Wang
2017-11-22 8:45 ` [PATCH v2 1/8] MdeModulePkg/metafile: Add PCD PcdCpuStackGuard Jian J Wang
2017-11-22 8:45 ` [PATCH v2 2/8] MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API Jian J Wang
2017-11-23 4:07 ` Yao, Jiewen
2017-11-23 5:06 ` Wang, Jian J
2017-11-25 13:17 ` 答复: " Fan Jeff
2017-11-27 2:20 ` Wang, Jian J
2017-11-22 8:45 ` [PATCH v2 3/8] MdePkg/BaseLib: Add stack switch related definitions for IA32 Jian J Wang
2017-11-22 8:45 ` [PATCH v2 4/8] MdeModulePkg/DxeIpl: Enable paging for Stack Guard Jian J Wang
2017-11-22 8:45 ` [PATCH v2 5/8] UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch Jian J Wang
2017-11-22 8:45 ` [PATCH v2 6/8] UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data Jian J Wang
2017-11-22 8:45 ` [PATCH v2 7/8] UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support Jian J Wang
2017-11-23 5:50 ` Yao, Jiewen
2017-11-23 5:59 ` Yao, Jiewen
2017-11-23 6:09 ` Wang, Jian J
2017-11-23 6:25 ` Yao, Jiewen
2017-11-23 7:54 ` Wang, Jian J
2017-11-23 6:05 ` Wang, Jian J
2017-11-23 6:16 ` Yao, Jiewen
2017-11-23 6:43 ` Wang, Jian J
2017-11-25 13:27 ` 答复: " Fan Jeff
2017-11-27 2:21 ` Wang, Jian J
2017-11-28 1:38 ` Wang, Jian J
2017-11-28 2:06 ` Yao, Jiewen
2017-11-25 13:35 ` 答复: " Fan Jeff
2017-11-22 8:45 ` [PATCH v2 8/8] UefiCpuPkg/CpuDxe: Initialize stack switch for MP Jian J Wang
2017-11-23 4:13 ` Yao, Jiewen
2017-11-23 5:03 ` Wang, Jian J
2017-11-23 5:19 ` Wang, Jian J
2017-11-23 5:39 ` Yao, Jiewen
2017-11-23 3:47 ` [PATCH v2 0/8] Implement stack guard feature Yao, Jiewen
2017-11-23 5:09 ` Wang, Jian J
2017-11-23 5:40 ` Yao, Jiewen
2017-11-25 13:44 ` 答复: " Fan Jeff
2017-11-25 13:55 ` Yao, Jiewen
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