From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 24D3620356240 for ; Mon, 4 Dec 2017 17:58:57 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Dec 2017 18:03:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,362,1508828400"; d="scan'208";a="13091628" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga001.jf.intel.com with ESMTP; 04 Dec 2017 18:03:27 -0800 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 18:03:27 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 18:03:27 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.213]) with mapi id 14.03.0319.002; Tue, 5 Dec 2017 10:03:25 +0800 From: "Yao, Jiewen" To: "Wang, Jian J" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH v3 00/11] Implement stack guard feature Thread-Index: AQHTak1haIcJZkS490mV4F+SAjrOzKMzHx1A Date: Tue, 5 Dec 2017 02:03:25 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA3992D@shsmsx102.ccr.corp.intel.com> References: <20171201023728.4680-1-jian.j.wang@intel.com> In-Reply-To: <20171201023728.4680-1-jian.j.wang@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNmM4YTBkOWItYmYzYS00OTNiLWE0NzEtMDA5NDBlZDExNGIzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJxZ3l0QVd6bFliMkIrMjJVWElLRk1yWkZ0akJ6OFdZNWJDeDNsalBxMnY2MHJOOVhweXJrXC9YK1E4ZjIzMityRyJ9 x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 00/11] Implement stack guard feature X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Dec 2017 01:58:58 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Good enhancement. I think it resolved my compatibility concern for the old = API. Some comment: 1) Can we just use CPU_EXCEPTION_INIT_DATA instead of CPU_EXCEPTION_INIT_DA= TA_EX? I am not sure why we add _EX here. 2) Is CPU_EXCEPTION_INIT_DATA_EX for IA32 only or both IA32/X64? I found "I= a32" may bring confusing here. See EFI_DEBUG_SUPPORT_PROTOCOL, we have Ia32= for IA32 arch, X64 for X64 arch. // // Flag to indicate if default handlers should be initialized or not. // BOOLEAN InitDefaultHandlers; } Ia32; } CPU_EXCEPTION_INIT_DATA_EX; 3) Can we add IdtTableSize in CPU_EXCEPTION_INIT_DATA_EX? 4) Can we add Version field in CPU_EXCEPTION_INIT_DATA_EX? I am not sure if= we need add more entry later. 5) You mentioned "KnownGoodStackTop is for *ALL* exceptions". Does ALL here mean StackSwitchExceptionNumber, or arch specific number such= as 0x20 for X86 system? I think StackSwitchExceptionNumber is enough. 6) There might be more than one TSS entry in GDT. Does TssDesc/Tss in CPU_EXCEPTION_INIT_DATA_EX mean the exception Tss? (nor= mal TSS does not need be reported here) If so, I suggest we use ExceptionTss as the keyword. 7) Below code may cause buffer overrun on IST. for (Index =3D 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumbe= r; ++Index) { // // Fixup IST // Tss->IST[Index] =3D StackTop; I suggest we add some basic check for StackSwitchExceptionNumber. 8) Do you think we need mention the TssDesc/Tss size requirement for that? TssDesc =3D StackSwitchData->Ia32.TssDesc; Tss =3D StackSwitchData->Ia32.Tss; for (Index =3D 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumbe= r; ++Index) { TssDesc +=3D 1; Tss +=3D 1; I suggest we add TssDescSize and TssSize in CPU_EXCEPTION_INIT_DATA_EX and = check the size in the code. 9) Last but not least important, have you evaluated if current CPU_EXCEPTIO= N_INIT_DATA_EX is enough for SMM version stack guard exception? Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ji= an J > Wang > Sent: Friday, December 1, 2017 10:37 AM > To: edk2-devel@lists.01.org > Subject: [edk2] [PATCH v3 00/11] Implement stack guard feature >=20 > > v3: > > a. Change new API InitializeCpuExceptionStackSwitchHandlers() to > > InitializeCpuExceptionHandlersEx(). Related code are updated > accordingly. > > b. Move EXCEPTION_STACK_SWITCH_DATA to CpuExceptionHandlerLib.h > > and change the name to CPU_EXCEPTION_INIT_DATA_EX for the sake > > of the API name change. > > c. Add more general macros in BaseLib.h. > > d. Add dummy implementation of InitializeCpuExceptionHandlersEx for > > SEC, PEI and SMM but implement a full version for DXE. > > e. Add dummy InitializeCpuExceptionHandlersEx for ARM's > CpuExceptionHandlerLib > > and NULL version of CpuExceptionHandlerLib > > f. Call InitializeCpuExceptionHandlersEx() in DxeMain instead of > > InitializeCpuExceptionHandlers(). >=20 >=20 > > v2: > > a. Introduce and implement new API > InitializeCpuExceptionStackSwitchHandlers(). > > b. Add stack switch related general definitions of IA32 in BaseLib.h. > > c. Add two new PCDs to configure exception vector list and stack size. > > d. Add code to save/restore GDTR, IDTR and TR for AP. > > e. Refactor exception handler code for stack switch. > > f. Add code to setup stack switch for AP besides BSP. >=20 > Stack guard feature makes use of paging mechanism to monitor if there's a > stack overflow occurred during boot. A new PCD PcdCpuStackGuard is added = to > enable/disable this feature. PCD PcdCpuStackSwitchExceptionList and > PcdCpuKnownGoodStackSize are introduced to configure the required > exceptions > and stack size. >=20 > If this feature is enabled, DxeIpl will setup page tables and set page wh= ere > the stack bottom is at to be NON-PRESENT. If stack overflow occurs, Page > Fault exception will be triggered. >=20 > In order to make sure exception handler works normally even when the stac= k > is corrupted, stack switching is implemented in exception library. >=20 > Due to the mechanism behind Stack Guard, this feature is only avaiable fo= r > UEFI drivers (memory avaiable). That also means it doesn't support NT32 > emulated platform (paging not supported). >=20 > Jian J Wang (11): > MdeModulePkg/metafile: Add PCD PcdCpuStackGuard > UefiCpuPkg/UefiCpuPkg.dec: Add two new PCDs for stack switch > MdeModulePkg/CpuExceptionHandlerLib.h: Add a new API > InitializeCpuExceptionHandlersEx > MdePkg/BaseLib: Add stack switch related definitions for IA32 > UefiCpuPkg/CpuExceptionHandlerLib: Add stack switch support > MdeModulePkg/CpuExceptionHandlerLibNull: Add new API implementation > ArmPkg/ArmExceptionLib: Add implementation of new API > UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data > UefiCpuPkg/CpuDxe: Initialize stack switch for MP > MdeModulePkg/Core/Dxe: Call new API InitializeCpuExceptionHandlersEx > instead > MdeModulePkg/DxeIpl: Enable paging for Stack Guard >=20 > ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c | 33 ++ > MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 2 +- > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 +- > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 + > MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 1 + > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 51 ++- > .../Include/Library/CpuExceptionHandlerLib.h | 78 ++++ > .../CpuExceptionHandlerLibNull.c | 34 ++ > MdeModulePkg/MdeModulePkg.dec | 7 + > MdeModulePkg/MdeModulePkg.uni | 7 + > MdePkg/Include/Library/BaseLib.h | 117 ++++++ > MdePkg/Library/BaseLib/BaseLib.inf | 3 + > MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 ++ > MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 ++ > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + > UefiCpuPkg/CpuDxe/CpuMp.c | 177 +++++++++ > .../CpuExceptionHandlerLib/CpuExceptionCommon.h | 39 ++ > .../DxeCpuExceptionHandlerLib.inf | 6 + > .../Library/CpuExceptionHandlerLib/DxeException.c | 79 ++++ > .../Ia32/ArchExceptionHandler.c | 167 +++++++++ > .../Ia32/ArchInterruptDefs.h | 8 + > .../Ia32/ExceptionTssEntryAsm.nasm | 398 > +++++++++++++++++++++ > .../CpuExceptionHandlerLib/PeiCpuException.c | 34 +- > .../PeiCpuExceptionHandlerLib.inf | 1 + > .../CpuExceptionHandlerLib/SecPeiCpuException.c | 34 +- > .../SecPeiCpuExceptionHandlerLib.inf | 1 + > .../SmmCpuExceptionHandlerLib.inf | 1 + > .../Library/CpuExceptionHandlerLib/SmmException.c | 34 +- > .../X64/ArchExceptionHandler.c | 134 +++++++ > .../CpuExceptionHandlerLib/X64/ArchInterruptDefs.h | 3 + > UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 + > UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 + > UefiCpuPkg/UefiCpuPkg.dec | 12 + > 33 files changed, 1547 insertions(+), 19 deletions(-) > create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm > create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm > create mode 100644 > UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm >=20 > -- > 2.14.1.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel