From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5B41720356240 for ; Mon, 4 Dec 2017 18:22:16 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Dec 2017 18:26:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,362,1508828400"; d="scan'208";a="184051378" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga006.fm.intel.com with ESMTP; 04 Dec 2017 18:26:46 -0800 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 18:26:45 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 18:26:45 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.159]) with mapi id 14.03.0319.002; Tue, 5 Dec 2017 10:26:43 +0800 From: "Yao, Jiewen" To: "Wang, Jian J" , "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Dong, Eric" Thread-Topic: [edk2] [PATCH v2 0/4] Enable page table write protection Thread-Index: AQHTbNr7CBx7wLF7Uk2bqlxUOIpiVKMyX8mAgAAEUQCAAaLcsA== Date: Tue, 5 Dec 2017 02:26:43 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA39A64@shsmsx102.ccr.corp.intel.com> References: <20171204083556.19416-1-jian.j.wang@intel.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B9BF42B@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjhlMjIxYTYtYjFhYi00YmQ0LTllM2EtZmY5ODVjOGI4ZTQzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ4K29cL1BrUG5ZaFJOUmZkMmpZQWN2N3FtTDR5eGw0RnM3U0k3RVU5WFJ3UG8yYXZKZUhacGVYVjl3MzNkWkwzdSJ9 x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 0/4] Enable page table write protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Dec 2017 02:22:16 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I do not suggest we define PAGE_TABLE_POOL_HEADER. If we can figure out other way, that will be better. Thank you Yao Jiewen > -----Original Message----- > From: Wang, Jian J > Sent: Monday, December 4, 2017 5:26 PM > To: Zeng, Star ; edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Ni, Ruiyu ; D= ong, > Eric > Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection >=20 > That means we can't share page table pool between DxeIpl and CpuDxe. If t= his is > acceptable, I can remove them. >=20 > > -----Original Message----- > > From: Zeng, Star > > Sent: Monday, December 04, 2017 5:11 PM > > To: Wang, Jian J ; edk2-devel@lists.01.org > > Cc: Yao, Jiewen ; Ni, Ruiyu ; > Dong, > > Eric ; Zeng, Star > > Subject: RE: [edk2] [PATCH v2 0/4] Enable page table write protection > > > > Recommend to not introduce the new header file and PCDs as new interfac= es, > > but handle the page table pool separately in DxeIpl and CpuDxe. > > > > Thanks, > > Star > > -----Original Message----- > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of = Jian > J > > Wang > > Sent: Monday, December 4, 2017 4:36 PM > > To: edk2-devel@lists.01.org > > Subject: [edk2] [PATCH v2 0/4] Enable page table write protection > > > > > v2 changes: > > > a. Enable protection on any newly added page table after DxeIpl. > > > b. Introduce page table pool concept to make page table allocation > > > and protection easier and error free. > > > > Write Protect feature (CR0.WP) is always enabled in driver > UefiCpuPkg/CpuDxe. > > But the memory pages used for page table are not set as read-only in th= e driver > > DxeIplPeim, after the paging is setup. This might jeopardize the page t= able > > integrity if there's buffer overflow occured in other part of system. > > > > This patch series will change this situation by clearing R/W bit in pag= e attribute > > of the pages used as page table. > > > > Validation works include booting Windows (10/server 2016) and Linux > > (Fedora/Ubuntu) on OVMF and Intel real platform. > > > > Jian J Wang (4): > > MdeModulePkg/MdeModulePkg.dec: Add new PCDs and Guid > > MdeModulePkg/PageTablePool.h: Page table pool GUID definition file > > MdeModulePkg/DxeIpl: Mark page table as read-only > > UefiCpuPkg/CpuDxe: Enable protection for newly added page table > > > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.h | 34 +++ > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 3 + > > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 8 +- > > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 315 > > +++++++++++++++++++++- > > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 15 ++ > > MdeModulePkg/Include/Guid/PageTablePool.h | 53 ++++ > > MdeModulePkg/MdeModulePkg.dec | 28 ++ > > UefiCpuPkg/CpuDxe/CpuDxe.c | 17 +- > > UefiCpuPkg/CpuDxe/CpuDxe.h | 2 + > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + > > UefiCpuPkg/CpuDxe/CpuPageTable.c | 329 > > ++++++++++++++++++++++- > > UefiCpuPkg/CpuDxe/CpuPageTable.h | 22 ++ > > 12 files changed, 816 insertions(+), 13 deletions(-) create mode 1006= 44 > > MdeModulePkg/Include/Guid/PageTablePool.h > > > > -- > > 2.14.1.windows.1 > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel