From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0A67E220FB335 for ; Tue, 5 Dec 2017 23:07:15 -0800 (PST) Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Dec 2017 23:11:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,367,1508828400"; d="scan'208";a="461289" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga007.jf.intel.com with ESMTP; 05 Dec 2017 23:11:46 -0800 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 5 Dec 2017 23:11:46 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 5 Dec 2017 23:11:46 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Wed, 6 Dec 2017 15:11:44 +0800 From: "Yao, Jiewen" To: "Wang, Jian J" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH v3 0/2] Enable page table write protection Thread-Index: AQHTbaFVum8Ykk4mG0GfLz9uem8m+6M152aQ Date: Wed, 6 Dec 2017 07:11:44 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA3B33C@shsmsx102.ccr.corp.intel.com> References: <20171205081604.11644-1-jian.j.wang@intel.com> In-Reply-To: <20171205081604.11644-1-jian.j.wang@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTdjNTBmN2EtNjU2Yy00NDVmLWI1NjQtODRjMzIyNjJiZmUyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiIra2ZHRzdKZ0FiZ2pUc0doRStWZkZQS1VPWnVYTGk4VzZTSHdocGlFMEozc3ZDN3RwMUs2TWdiOXJUR1RHNG5mIn0= x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 0/2] Enable page table write protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Dec 2017 07:07:16 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks you. It looks good to me. Reviewed-by: Jiewen.yao@intel.com I suggest CPU owner can have double check the code before check in. Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ji= an J > Wang > Sent: Tuesday, December 5, 2017 4:16 PM > To: edk2-devel@lists.01.org > Subject: [edk2] [PATCH v3 0/2] Enable page table write protection >=20 > > v3 changes: > > a. According to code review comments, remove the public definitions of > > page table pool. Now the DxeIpl and CpuDxe will have their own page > > table pool but in the same mechanism. Related PCDs, GUDI and header= s > > are also removed. > > b. Apply protection to all page tables, including new ones added in > > CpuDxe driver. > > c. Code/comments cleanup. >=20 > > v2 changes: > > a. Enable protection on any newly added page table after DxeIpl. > > b. Introduce page table pool concept to make page table allocation > > and protection easier and error free. >=20 > Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/Cpu= Dxe. > But the memory pages used for page table are not set as read-only in the = driver > DxeIplPeim, after the paging is setup. This might jeopardize the page tab= le > integrity if there's buffer overflow occured in other part of system. >=20 > This patch series will change this situation by clearing R/W bit in page = attribute > of the pages used as page table. >=20 > Validation works include booting Windows (10/server 2016) and Linux > (Fedora/Ubuntu) > on OVMF and Intel real platform. >=20 > Jian J Wang (2): > MdeModulePkg/DxeIpl: Mark page table as read-only > UefiCpuPkg/CpuDxe: Enable protection for newly added page table >=20 > MdeModulePkg/Core/DxeIplPeim/DxeIpl.h | 34 +++ > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 8 +- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 301 > ++++++++++++++++++++++- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 26 ++ > UefiCpuPkg/CpuDxe/CpuDxe.c | 17 +- > UefiCpuPkg/CpuDxe/CpuDxe.h | 2 + > UefiCpuPkg/CpuDxe/CpuPageTable.c | 226 > ++++++++++++++++- > UefiCpuPkg/CpuDxe/CpuPageTable.h | 34 +++ > 8 files changed, 635 insertions(+), 13 deletions(-) >=20 > -- > 2.15.1.windows.2 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel