From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E9998221ED75B for ; Wed, 20 Dec 2017 19:04:10 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2017 19:08:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,434,1508828400"; d="scan'208";a="3603009" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga002.fm.intel.com with ESMTP; 20 Dec 2017 19:08:58 -0800 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 20 Dec 2017 19:08:58 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 20 Dec 2017 19:08:57 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.218]) with mapi id 14.03.0319.002; Thu, 21 Dec 2017 11:08:55 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLength & 0x3)!=0 Thread-Index: AQHTegRMl+GQWfSBoEiO5TOXpZS7kqNNHfvQ Date: Thu, 21 Dec 2017 03:08:55 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA4EEDC@shsmsx102.ccr.corp.intel.com> References: <1513823692-6220-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1513823692-6220-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWZhMjYxN2MtMWY3Yi00NTBmLWI5NWItNTZmMWY2MmE3ZDA2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJlZEYwSWVJOVZOcHkxRkxrdU5uSWxISkc4b0NPdkR2aDdCaWNrQWRtUHJGVVdBVmswcE9lRjU1Ykl0NW9OdjlnIn0= x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLength & 0x3)!=0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Dec 2017 03:04:11 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Zeng, Star > Sent: Thursday, December 21, 2017 10:35 AM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Yao, Jiewen ; > Chaganty, Rangasai V > Subject: [PATCH] IntelSiliconPkg MicrocodeUpdateDxe: Fix (ExtendedTableLe= ngth > & 0x3)!=3D0 >=20 > The first 48 bytes contain the microcode update header. > DataSize must be a multiple of DWORDs. > TotalSize is always a multiple of 1024. > Both size of CPU_MICROCODE_EXTENDED_TABLE_HEADER and > CPU_MICROCODE_EXTENDED_TABLE are multiple of DWORDs. >=20 > So (ExtendedTableLength & 0x3)!=3D0 should be > (ExtendedTableLength & 0x3)=3D=3D0. >=20 > Cc: Jiewen Yao > Cc: Rangasai V Chaganty > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c | 4 > ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git > a/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c > b/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c > index 4e8f1d5fd8a8..b99221c9696d 100644 > --- a/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.= c > +++ > b/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c > @@ -8,7 +8,7 @@ >=20 > MicrocodeWrite() and VerifyMicrocode() will receive untrusted input an= d do > basic validation. >=20 > - Copyright (c) 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at > @@ -494,7 +494,7 @@ VerifyMicrocode ( > // > // Calculate Extended Checksum > // > - if ((ExtendedTableLength > > sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADER)) && > ((ExtendedTableLength & 0x3) !=3D 0)) { > + if ((ExtendedTableLength > > sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADER)) && > ((ExtendedTableLength & 0x3) =3D=3D 0)) { > CheckSum32 =3D CalculateSum32((UINT32 *)ExtendedTableHeader, > ExtendedTableLength); > if (CheckSum32 =3D=3D 0) { > // > -- > 2.7.0.windows.1