From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 27EF221F833B3 for ; Thu, 4 Jan 2018 06:30:04 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jan 2018 06:35:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,507,1508828400"; d="scan'208";a="18164652" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga004.fm.intel.com with ESMTP; 04 Jan 2018 06:35:08 -0800 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 4 Jan 2018 06:35:07 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 4 Jan 2018 06:35:07 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.189]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Thu, 4 Jan 2018 22:35:05 +0800 From: "Yao, Jiewen" To: Paulo Alcantara , "edk2-devel@lists.01.org" CC: Laszlo Ersek , "Dong, Eric" Thread-Topic: [edk2] [RFC v4 4/6] UefiCpuPkg/CpuExceptionHandlerLib: Add helper to valid memory addresses Thread-Index: AQHTgF9FSSLCz0Cr/EyZzZ52ilwniKNi8HDQgAAJmrCAAD84gIAAlkww Date: Thu, 4 Jan 2018 14:35:05 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA7079B@shsmsx102.ccr.corp.intel.com> References: <32f06077006939f71560970f6abcbbb2062ea5c3.1514517573.git.paulo@paulo.ac> <74D8A39837DF1E4DA445A8C0B3885C503AA6F95E@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C503AA6FA0F@shsmsx102.ccr.corp.intel.com> <878tddsqf6.fsf@paulo.ac> In-Reply-To: <878tddsqf6.fsf@paulo.ac> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzE4OGNlMjEtZjkyMC00ZGIwLWI4ZWUtNWVhODc3MmE5MmJiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJqQWlXa29XZjRubGdTOWx4Nnp0ZWVqSmRnUTNZTVo1SFExQTNMa3VJanptSkFaZVRcLzlyK3Y5WDFDbzhVTmV3aiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [RFC v4 4/6] UefiCpuPkg/CpuExceptionHandlerLib: Add helper to valid memory addresses X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Jan 2018 14:30:04 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thank you! For 7), you are right that we disable IA32 paging by default. However, we do support IA32 PAE in DxeIpl. Please refer to MdeModulePkg\Cor= e\DxeIplPeim\Ia32\DxeLoadFunc.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PageTables =3D 0; BuildPageTablesIa32Pae =3D (BOOLEAN) (PcdGetBool (PcdSetNxForStack) && = IsIa32PaeSupport () && IsExecuteDisableBitAvailable ()); if (BuildPageTablesIa32Pae) { PageTables =3D Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE); EnableExecuteDisableBit (); } =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Please notice that we only support IA32 PAE, we do not support IA32 non-PAE= mode so far. (no matter PSE is ON/OFF) So, I suggest: 7.1) Please validate IA32 PAE mode. (You can enable PcdSetNxForStack) 7.2) If we cannot validate the IA32 non-PAE code, please remove them. You c= an just print "IA32 non-PAE - UNSUPPORTED" and return invalid address. Then= it can save our development time, review time, and validation time. The ke= y is that we only want to check in the validated code. Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Pa= ulo > Alcantara > Sent: Thursday, January 4, 2018 9:30 PM > To: Yao, Jiewen ; Yao, Jiewen ; > edk2-devel@lists.01.org > Cc: Laszlo Ersek ; Dong, Eric > Subject: Re: [edk2] [RFC v4 4/6] UefiCpuPkg/CpuExceptionHandlerLib: Add > helper to valid memory addresses >=20 > "Yao, Jiewen" writes: >=20 > > 5) For CR4, please use meaning definition for BIT4/BIT5. > > if ((Cr4 & BIT4) !=3D 0 && (*PageDirEntry & BIT7) !=3D 0) { > > if (((Cr4 & BIT5) !=3D 0 && (UINT64)LinearAddress > 0xFFFFFFFFFULL)= || >=20 > OK. >=20 > > > > 6) For IA32 PAE/PSE calculation, same comment for 3 and 4. >=20 > OK. >=20 > > > > 7) Last but not least important, would you please share the information= on > how do you validate the 32bit PAE/PSE/normal 4K page table? >=20 > Since on IA32 we use 32-bit protected flat model and paging disabled > (OK?), I wasn't able to validate the paging modes other than 4-level > paging mode in X64. The memory validation code I wrote is heavily based > upon what I read from Intel SDM Vol 3A manual. >=20 > If you do have any idea on how to validate it -- whether it's a PoC or > test code -- please let me know, and then I validate it. >=20 > Thanks again for your review! >=20 > Paulo >=20 > > > > Thank you > > Yao Jiewen > > > >> -----Original Message----- > >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Yao, > >> Jiewen > >> Sent: Thursday, January 4, 2018 9:36 AM > >> To: Paulo Alcantara ; edk2-devel@lists.01.org > >> Cc: Laszlo Ersek ; Dong, Eric > >> Subject: Re: [edk2] [RFC v4 4/6] UefiCpuPkg/CpuExceptionHandlerLib: Ad= d > >> helper to valid memory addresses > >> > >> Some suggestion: > >> > >> 1) I am not sure if it is proper to use ASSERT in an exception handler= , because > we > >> know something is wrong. > >> > >> ASSERT ((PhysicalAddress & (sizeof (*Pml4TableEntry) - 1)) =3D=3D 0)= ; > >> > >> I suggest we just do the check, and return FALSE, if the prerequisite = is not > >> satisfied. > >> > >> 2) Can we use meaningful definition for BIT0, BIT7? > >> > >> if ((*Pml4TableEntry & BIT0) =3D=3D 0) { > >> if ((*PageDirPtrTableEntry & BIT7) !=3D 0) { > >> > >> 3) I am not sure if I understand below code. > >> > >> PhysicalAddress =3D (UINT64)Cr3 & (((1ULL << MaxPhyAddrBits) - 1) <<= 12); > >> PhysicalAddress =3D *Pml4TableEntry & (((1ULL << MaxPhyAddrBits) - 1= ) << > 12); > >> PhysicalAddress =3D *PageDirPtrTableEntry & (((1ULL << MaxPhyAddrBit= s) - > 1) > >> << 12); > >> PhysicalAddress =3D *PageDirEntry & (((1ULL << MaxPhyAddrBits) - 1) = << > 12); > >> > >> If MaxPhyAddrBits is 48, you will get "Cr3 & 0x0FFFFFFFFFFFF000". Is t= hat > what > >> you want? I think we need "Cr3 & 0x0000FFFFFFFFF000" > >> Should it be: PhysicalAddress =3D (UINT64)Cr3 & ((1ULL << MaxPhyAddrBi= ts) - 1) > & > >> (~0xFFF); > >> > >> 4) Can we use a more readable way to below? Personally, I do not sugge= st > "<< 3", > >> which is just the index calculation. > >> > >> PhysicalAddress =3D (UINT64)Cr3 & (((1ULL << MaxPhyAddrBits) - 1) <<= 12); > >> PhysicalAddress |=3D (((UINT64)LinearAddress >> 39) & 0x1FF) << 3; > >> Pml4TableEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> PhysicalAddress =3D *Pml4TableEntry & (((1ULL << MaxPhyAddrBits) - 1= ) << > 12); > >> > >> For example: > >> PhysicalAddress =3D (UINT64)Cr3 & ((1ULL << MaxPhyAddrBits) - 1) & > (~0xFFF); > >> Pml4TableEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> Index=3D (UINTN)(((UINT64)LinearAddress >> 39) & 0x1FF); > >> PhysicalAddress =3D Pml4TableEntry[Index] & ((1ULL << MaxPhyAddrBits= ) - 1) > & > >> (~0xFFF); > >> > >> > >> > >> Thank you > >> Yao Jiewen > >> > >> > >> > -----Original Message----- > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf = Of > >> Paulo > >> > Alcantara > >> > Sent: Friday, December 29, 2017 12:40 PM > >> > To: edk2-devel@lists.01.org > >> > Cc: Laszlo Ersek ; Dong, Eric > >> > Subject: [edk2] [RFC v4 4/6] UefiCpuPkg/CpuExceptionHandlerLib: Add > helper > >> to > >> > valid memory addresses > >> > > >> > Introduce IsLinearAddressValid() function that will be used for > >> > validating memory addresses that would get dereferenced during stack > >> > traces in IA32 and X64 CPU exceptions. > >> > > >> > Contributed-under: TianoCore Contribution Agreement 1.1 > >> > Cc: Eric Dong > >> > Cc: Laszlo Ersek > >> > Requested-by: Brian Johnson > >> > Requested-by: Jiewen Yao > >> > Signed-off-by: Paulo Alcantara > >> > --- > >> > UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c | > 382 > >> > ++++++++++++++++++++ > >> > UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h | > >> 16 + > >> > 2 files changed, 398 insertions(+) > >> > > >> > diff --git > >> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c > >> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c > >> > index 867c5c01d6..52b3eb1463 100644 > >> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c > >> > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c > >> > @@ -14,6 +14,9 @@ > >> > > >> > #include "CpuExceptionCommon.h" > >> > > >> > +#include > >> > +#include > >> > + > >> > // > >> > // Error code flag indicating whether or not an error code will be > >> > // pushed on the stack if an exception occurs. > >> > @@ -194,3 +197,382 @@ GetPdbFileName ( > >> > } > >> > } > >> > } > >> > + > >> > +/** > >> > + Check if a linear address is valid by walking the page tables in = 4-level > >> > + paging mode. > >> > + > >> > + @param[in] Cr3 CR3 control register. > >> > + @param[in] MaxPhyAddrBits MAXPHYADDRBITS bits. > >> > + @param[in] LinearAddress Linear address to be checked. > >> > +**/ > >> > +STATIC > >> > +BOOLEAN > >> > +Do4LevelPagingModeCheck ( > >> > + IN UINTN Cr3, > >> > + IN UINT8 MaxPhyAddrBits, > >> > + IN UINTN LinearAddress > >> > + ) > >> > +{ > >> > + UINT64 PhysicalAddress; > >> > + UINT64 *Pml4TableEntry; > >> > + UINT64 *PageDirPtrTableEntry; > >> > + UINT64 *PageDirEntry; > >> > + UINT64 *PageTableEntry; > >> > + > >> > + // > >> > + // In 4-level paging mode, linear addresses are 48 bits wide > >> > + // > >> > + if ((UINT64)LinearAddress > (1ULL << 48) - 1) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PML4E > >> > + // > >> > + PhysicalAddress =3D (UINT64)Cr3 & (((1ULL << MaxPhyAddrBits) - 1)= << > 12); > >> > + PhysicalAddress |=3D (((UINT64)LinearAddress >> 39) & 0x1FF) << 3= ; > >> > + > >> > + ASSERT ((PhysicalAddress & (sizeof (*Pml4TableEntry) - 1)) =3D=3D= 0); > >> > + > >> > + Pml4TableEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check if a PDPTE is present > >> > + // > >> > + if ((*Pml4TableEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PDPTE > >> > + // > >> > + PhysicalAddress =3D *Pml4TableEntry & (((1ULL << MaxPhyAddrBits) = - 1) > << > >> > 12); > >> > + PhysicalAddress |=3D (((UINT64)LinearAddress >> 30) & 0x1FF) << 3= ; > >> > + > >> > + ASSERT ((PhysicalAddress & (sizeof (*PageDirPtrTableEntry) - 1)) = =3D=3D 0); > >> > + > >> > + PageDirPtrTableEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check whether a PDPTE or 1GiB page entry is present > >> > + // > >> > + if ((*PageDirPtrTableEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Check if PDPTE maps an 1GiB page > >> > + // > >> > + if ((*PageDirPtrTableEntry & BIT7) !=3D 0) { > >> > + return TRUE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PDE > >> > + // > >> > + PhysicalAddress =3D *PageDirPtrTableEntry & (((1ULL << MaxPhyAddr= Bits) > - > >> 1) > >> > << > >> > + 12); > >> > + PhysicalAddress |=3D (((UINT64)LinearAddress >> 21) & 0x1FF) << 3= ; > >> > + > >> > + ASSERT ((PhysicalAddress & (sizeof (*PageDirEntry) - 1)) =3D=3D 0= ); > >> > + > >> > + PageDirEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check whether a PDE or a 2MiB page entry is present > >> > + // > >> > + if ((*PageDirEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Check if PDE maps a 2MiB page > >> > + // > >> > + if ((*PageDirEntry & BIT7) !=3D 0) { > >> > + return TRUE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PTE > >> > + // > >> > + PhysicalAddress =3D *PageDirEntry & (((1ULL << MaxPhyAddrBits) - = 1) << > >> 12); > >> > + PhysicalAddress |=3D (((UINT64)LinearAddress >> 12) & 0x1FF) << 3= ; > >> > + > >> > + ASSERT ((PhysicalAddress & (sizeof (*PageTableEntry) - 1)) =3D=3D= 0); > >> > + > >> > + PageTableEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check if PTE maps a 4KiB page > >> > + // > >> > + if ((*PageTableEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + return TRUE; > >> > +} > >> > + > >> > +/** > >> > + Check if a linear address is valid by walking the page tables in = 32-bit > paging > >> > + mode. > >> > + > >> > + @param[in] Cr3 CR3 control register. > >> > + @param[in] Cr4 CR4 control register. > >> > + @param[in] LinearAddress Linear address to be checked. > >> > +**/ > >> > +STATIC > >> > +BOOLEAN > >> > +Do32BitPagingModeCheck ( > >> > + IN UINTN Cr3, > >> > + IN UINTN Cr4, > >> > + IN UINTN LinearAddress > >> > + ) > >> > +{ > >> > + UINT64 PhysicalAddress; > >> > + UINT32 *PageDirEntry; > >> > + UINT32 *PageTableEntry; > >> > + > >> > + if (LinearAddress > MAX_UINT32) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PDE > >> > + // > >> > + PhysicalAddress =3D (UINT32)Cr3 & (((1ULL << 20) - 1) << 12); > >> > + PhysicalAddress |=3D (((UINT32)LinearAddress >> 22) & 0x3FF) << 2= ; > >> > + > >> > + ASSERT ((PhysicalAddress & (sizeof (*PageDirEntry) - 1)) =3D=3D 0= ); > >> > + > >> > + PageDirEntry =3D (UINT32 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check whether a PTE or a 4MiB page is present > >> > + // > >> > + if ((*PageDirEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Check if PDE maps a 4MiB page > >> > + // > >> > + if ((Cr4 & BIT4) !=3D 0 && (*PageDirEntry & BIT7) !=3D 0) { > >> > + return TRUE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PTE > >> > + // > >> > + PhysicalAddress =3D *PageDirEntry & (((1ULL << 20) - 1) << 12); > >> > + PhysicalAddress |=3D (((UINT32)LinearAddress >> 12) & 0x3FF) << 2= ; > >> > + > >> > + ASSERT ((PhysicalAddress & (sizeof (*PageTableEntry) - 1)) =3D=3D= 0); > >> > + > >> > + PageTableEntry =3D (UINT32 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check if PTE maps a 4KiB page > >> > + // > >> > + if ((*PageTableEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + return TRUE; > >> > +} > >> > + > >> > +/** > >> > + Check if a linear address is valid by walking the page tables in = PAE paging > >> > + mode. > >> > + > >> > + @param[in] Cr3 CR3 control register. > >> > + @param[in] MaxPhyAddrBits MAXPHYADDRBITS bits. > >> > + @param[in] LinearAddress Linear address to be checked. > >> > +**/ > >> > +STATIC > >> > +BOOLEAN > >> > +DoPAEPagingModeCheck ( > >> > + IN UINTN Cr3, > >> > + IN UINT8 MaxPhyAddrBits, > >> > + IN UINTN LinearAddress > >> > + ) > >> > +{ > >> > + UINT64 PhysicalAddress; > >> > + UINT64 *PageDirPtrTableEntry; > >> > + UINT64 *PageDirEntry; > >> > + UINT64 *PageTableEntry; > >> > + > >> > + if (LinearAddress > MAX_UINT32) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PDPTE > >> > + // > >> > + PhysicalAddress =3D (UINT32)Cr3 >> 5; > >> > + > >> > + // > >> > + // Select PDPTE register > >> > + // > >> > + PhysicalAddress +=3D > >> > + ((UINT32)LinearAddress >> 30) * sizeof (*PageDirPtrTableEntry); > >> > + > >> > + PageDirPtrTableEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check if PDE is present > >> > + // > >> > + if ((*PageDirPtrTableEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + PhysicalAddress =3D *PageDirPtrTableEntry & (((1ULL << MaxPhyAddr= Bits) > - > >> 1) > >> > << > >> > + 12); > >> > + PhysicalAddress |=3D ((LinearAddress >> 21) & 0x1FF) << 3; > >> > + ASSERT ((PhysicalAddress & (sizeof (*PageDirEntry) - 1)) =3D=3D 0= ); > >> > + > >> > + PageDirEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check whether a PTE or a 2MiB page is present > >> > + // > >> > + if ((*PageDirEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Check if PDE maps a 2MiB page > >> > + // > >> > + if ((*PageDirEntry & BIT7) !=3D 0) { > >> > + return TRUE; > >> > + } > >> > + > >> > + // > >> > + // Calculate physical address of PTE > >> > + // > >> > + PhysicalAddress =3D *PageDirEntry & (((1ULL << MaxPhyAddrBits) - = 1) << > >> 12); > >> > + PhysicalAddress |=3D ((LinearAddress >> 12) & 0x1FF) << 3; > >> > + ASSERT ((PhysicalAddress & (sizeof (*PageTableEntry) - 1)) =3D=3D= 0); > >> > + > >> > + PageTableEntry =3D (UINT64 *)(UINTN)PhysicalAddress; > >> > + > >> > + // > >> > + // Check if PTE maps a 4KiB page > >> > + // > >> > + if ((*PageTableEntry & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + return TRUE; > >> > +} > >> > + > >> > +/** > >> > + Check if a linear address is valid. > >> > + > >> > + @param[in] Cr0 CR0 control register. > >> > + @param[in] Cr3 CR3 control register. > >> > + @param[in] Cr4 CR4 control register. > >> > + @param[in] LinearAddress Linear address to be checked. > >> > +**/ > >> > +BOOLEAN > >> > +IsLinearAddressValid ( > >> > + IN UINTN Cr0, > >> > + IN UINTN Cr3, > >> > + IN UINTN Cr4, > >> > + IN UINTN LinearAddress > >> > + ) > >> > +{ > >> > + UINT32 Eax; > >> > + UINT32 Edx; > >> > + UINT8 MaxPhyAddrBits; > >> > + MSR_IA32_EFER_REGISTER Msr; > >> > + BOOLEAN AddressValid; > >> > + > >> > + // > >> > + // Check for valid input parameters > >> > + // > >> > + if (Cr0 =3D=3D 0 || Cr4 =3D=3D 0 || LinearAddress =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Check if paging is disabled > >> > + // > >> > + if ((Cr0 & BIT31) =3D=3D 0) { > >> > + // > >> > + // If CR4.PAE bit is set, then the linear (or physical) address= supports > >> > + // only up to 36 bits. > >> > + // > >> > + if (((Cr4 & BIT5) !=3D 0 && (UINT64)LinearAddress > 0xFFFFFFFFF= ULL) > || > >> > + LinearAddress > 0xFFFFFFFF) { > >> > + return FALSE; > >> > + } > >> > + > >> > + return TRUE; > >> > + } > >> > + > >> > + // > >> > + // Paging can be enabled only if CR0.PE bit is set > >> > + // > >> > + if ((Cr0 & BIT0) =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // CR3 register cannot be zero if paging is enabled > >> > + // > >> > + if (Cr3 =3D=3D 0) { > >> > + return FALSE; > >> > + } > >> > + > >> > + // > >> > + // Get MAXPHYADDR bits > >> > + // > >> > + AsmCpuid (0x80000000, &Eax, NULL, NULL, NULL); > >> > + if (Eax >=3D 0x80000008) { > >> > + AsmCpuid (0x80000008, &Eax, NULL, NULL, NULL); > >> > + MaxPhyAddrBits =3D (UINT8)Eax; > >> > + } else { > >> > + AsmCpuid (1, NULL, NULL, NULL, &Edx); > >> > + if ((Edx & BIT6) !=3D 0) { > >> > + MaxPhyAddrBits =3D 36; > >> > + } else { > >> > + MaxPhyAddrBits =3D 32; > >> > + } > >> > + } > >> > + > >> > + ASSERT (MaxPhyAddrBits > 0); > >> > + > >> > + AddressValid =3D FALSE; > >> > + > >> > + // > >> > + // check if CR4.PAE bit is not set > >> > + // > >> > + if ((Cr4 & BIT5) =3D=3D 0) { > >> > + // > >> > + // Check if linear address is valid in 32-bit paging mode > >> > + // > >> > + AddressValid =3D Do32BitPagingModeCheck (Cr3, Cr4, LinearAddres= s); > >> > + } else { > >> > + if (MaxPhyAddrBits > 52) { > >> > + return FALSE; > >> > + } > >> > + > >> > + Msr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); > >> > + > >> > + if (Msr.Bits.LME =3D=3D 0) { > >> > + // > >> > + // Check if linear address is valid in PAE paging mode > >> > + // > >> > + AddressValid =3D DoPAEPagingModeCheck (Cr3, MaxPhyAddrBits, > >> > LinearAddress); > >> > + } else { > >> > + // > >> > + // Check if linear address is valid in 4-level paging mode > >> > + // > >> > + AddressValid =3D Do4LevelPagingModeCheck (Cr3, MaxPhyAddrBits= , > >> > + LinearAddress); > >> > + } > >> > + } > >> > + > >> > + return AddressValid; > >> > +} > >> > diff --git > >> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > >> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > >> > index ec46c2d9d3..1b51034c25 100644 > >> > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > >> > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h > >> > @@ -330,5 +330,21 @@ GetPdbFileName ( > >> > OUT CHAR8 **PdbFileName > >> > ); > >> > > >> > +/** > >> > + Check if a linear address is valid. > >> > + > >> > + @param[in] Cr0 CR0 control register. > >> > + @param[in] Cr3 CR3 control register. > >> > + @param[in] Cr4 CR4 control register. > >> > + @param[in] LinearAddress Linear address to be checked. > >> > +**/ > >> > +BOOLEAN > >> > +IsLinearAddressValid ( > >> > + IN UINTN Cr0, > >> > + IN UINTN Cr3, > >> > + IN UINTN Cr4, > >> > + IN UINTN LinearAddress > >> > + ); > >> > + > >> > #endif > >> > > >> > -- > >> > 2.14.3 > >> > > >> > _______________________________________________ > >> > edk2-devel mailing list > >> > edk2-devel@lists.01.org > >> > https://lists.01.org/mailman/listinfo/edk2-devel > >> _______________________________________________ > >> edk2-devel mailing list > >> edk2-devel@lists.01.org > >> https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel