From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 294AB21D2BEE0 for ; Tue, 16 Jan 2018 05:15:36 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jan 2018 05:20:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,368,1511856000"; d="scan'208";a="193732577" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga005.jf.intel.com with ESMTP; 16 Jan 2018 05:20:55 -0800 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 16 Jan 2018 05:20:55 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 16 Jan 2018 05:20:54 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.189]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.218]) with mapi id 14.03.0319.002; Tue, 16 Jan 2018 21:20:52 +0800 From: "Yao, Jiewen" To: "Gao, Liming" , "edk2-devel@lists.01.org" CC: Andrew Fish , "Dong, Eric" , "Laszlo Ersek" , "Kinney, Michael D" Thread-Topic: [PATCH v2 5/7] UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain Thread-Index: AQHTirtshQyqTun47EGOzMKhc+VWo6N2gcsw Date: Tue, 16 Jan 2018 13:20:51 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA7F34C@shsmsx102.ccr.corp.intel.com> References: <1515661515-6532-1-git-send-email-liming.gao@intel.com> <1515661515-6532-2-git-send-email-liming.gao@intel.com> In-Reply-To: <1515661515-6532-2-git-send-email-liming.gao@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjExM2YxNDYtYmE1Ni00ZDkyLWFmMDktN2Q0MjEzNzFkYjRhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJxQzNCWmZRYmxJdXRTaXdRd2paSllWUHlsalArb0FUVU41R2ZYT0ZhTzRVS0g3SnZRQk1FV1RxR2tPWERBU0tnIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 5/7] UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Jan 2018 13:15:37 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Gao, Liming > Sent: Thursday, January 11, 2018 5:05 PM > To: edk2-devel@lists.01.org > Cc: Andrew Fish ; Yao, Jiewen ; > Dong, Eric ; Laszlo Ersek ; Kinne= y, > Michael D > Subject: [PATCH v2 5/7] UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 > tool chain >=20 > In V2, use "mov rax, strict qword 0" to replace the hard code db. >=20 > 1. Use lea instruction to get the address instead of mov instruction. > 2. Use the dummy address as jmp destination, and add the logic to fix up > the address to the absolute address at boot time. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Liming Gao > Cc: Andrew Fish > Cc: Jiewen Yao > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: Michael Kinney > --- > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 6 +++- > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8 +++-- > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 11 +++++- > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 39 > ++++++++++++++-------- > .../SmmCpuFeaturesLib/X64/SmiException.nasm | 10 +++--- > 5 files changed, 52 insertions(+), 22 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > index 00c0f067..057ec6d 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > @@ -1,5 +1,5 @@ > ;-----------------------------------------------------------------------= ------- ; > -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
> +; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> ; This program and the accompanying materials > ; are licensed and made available under the terms and conditions of the = BSD > License > ; which accompanies this distribution. The full text of the license may= be found > at > @@ -273,3 +273,7 @@ _StmSmiHandler: >=20 > ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint > ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - > _StmSmiEntryPoint > + > +global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress) > +ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress): > + ret > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > index 45015b8..8dc2d70 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > @@ -1,7 +1,7 @@ > /** @file > SMM STM support functions >=20 > - Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at > @@ -116,7 +116,6 @@ UINTN mMsegSize =3D 0; >=20 > BOOLEAN mStmConfigurationTableInitialized =3D FALSE; >=20 > - > /** > The constructor function >=20 > @@ -139,6 +138,11 @@ SmmCpuFeaturesLibStmConstructor ( > EFI_SMRAM_DESCRIPTOR *SmramDescriptor; >=20 > // > + // Initialize address fixup > + // > + SmmCpuFeaturesLibStmSmiEntryFixupAddress (); > + > + // > // Call the common constructor function > // > Status =3D SmmCpuFeaturesLibConstructor (ImageHandle, SystemTable); > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h > index 92a4dc0..c98b660 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h > @@ -1,7 +1,7 @@ > /** @file > SMM STM support >=20 > - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at > @@ -173,4 +173,13 @@ GetStmResource ( > VOID > ); >=20 > +/** > + This function fixes up the address of the global variable or function > + referred in SmiEntry assembly files to be the absoute address. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesLibStmSmiEntryFixupAddress ( > + ); > + > #endif > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > index ea2d297..90a9fd4 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > @@ -1,5 +1,5 @@ > ;-----------------------------------------------------------------------= ------- ; > -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
> +; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> ; This program and the accompanying materials > ; are licensed and made available under the terms and conditions of the = BSD > License > ; which accompanies this distribution. The full text of the license may= be found > at > @@ -164,7 +164,8 @@ Base: > mov cr0, rbx > retf > @LongMode: ; long mode (64-bit code) > starts here > - mov rax, ASM_PFX(gStmSmiHandlerIdtr) > + mov rax, strict qword 0 ; mov rax, > ASM_PFX(gStmSmiHandlerIdtr) > +StmSmiEntrySmiHandlerIdtrAbsAddr: > lidt [rax] > lea ebx, [rdi + DSC_OFFSET] > mov ax, [rbx + DSC_DS] > @@ -175,7 +176,9 @@ Base: > mov gs, eax > mov ax, [rbx + DSC_SS] > mov ss, eax > - > + mov rax, strict qword 0 ; mov rax, > CommonHandler > +StmSmiEntryCommonHandlerAbsAddr: > + jmp rax > CommonHandler: > mov rbx, [rsp + 0x08] ; rbx <- CpuIndex >=20 > @@ -188,16 +191,13 @@ CommonHandler: > add rsp, -0x20 >=20 > mov rcx, rbx > - mov rax, ASM_PFX(CpuSmmDebugEntry) > - call rax > + call ASM_PFX(CpuSmmDebugEntry) >=20 > mov rcx, rbx > - mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr > of SmiRedezvous > - call rax > + call ASM_PFX(SmiRendezvous) >=20 > mov rcx, rbx > - mov rax, ASM_PFX(CpuSmmDebugExit) > - call rax > + call ASM_PFX(CpuSmmDebugExit) >=20 > add rsp, 0x20 >=20 > @@ -208,7 +208,7 @@ CommonHandler: >=20 > add rsp, 0x200 >=20 > - mov rax, ASM_PFX(gStmXdSupported) > + lea rax, [ASM_PFX(gStmXdSupported)] > mov al, [rax] > cmp al, 0 > jz .1 > @@ -228,7 +228,7 @@ _StmSmiHandler: > ; Check XD disable bit > ; > xor r8, r8 > - mov rax, ASM_PFX(gStmXdSupported) > + lea rax, [ASM_PFX(gStmXdSupported)] > mov al, [rax] > cmp al, 0 > jz @StmXdDone > @@ -249,8 +249,8 @@ _StmSmiHandler: >=20 > ; below step is needed, because STM does not run above code. > ; we have to run below code to set IDT/CR0/CR4 > - > - mov rax, ASM_PFX(gStmSmiHandlerIdtr) > + mov rax, strict qword 0 ; mov rax, > ASM_PFX(gStmSmiHandlerIdtr) > +StmSmiHandlerIdtrAbsAddr: > lidt [rax] >=20 > mov rax, cr0 > @@ -264,3 +264,16 @@ _StmSmiHandler: >=20 > ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint > ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - > _StmSmiEntryPoint > + > +global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress) > +ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress): > + lea rax, [ASM_PFX(gStmSmiHandlerIdtr)] > + lea rcx, [StmSmiEntrySmiHandlerIdtrAbsAddr] > + mov qword [rcx - 8], rax > + lea rcx, [StmSmiHandlerIdtrAbsAddr] > + mov qword [rcx - 8], rax > + > + lea rax, [CommonHandler] > + lea rcx, [StmSmiEntryCommonHandlerAbsAddr] > + mov qword [rcx - 8], rax > + ret > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm > index ce9d7c2..b0ab87b 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm > @@ -1,5 +1,5 @@ > ;-----------------------------------------------------------------------= ------- ; > -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
> +; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> ; This program and the accompanying materials > ; are licensed and made available under the terms and conditions of the = BSD > License > ; which accompanies this distribution. The full text of the license may= be found > at > @@ -95,7 +95,7 @@ ASM_PFX(OnStmSetup): > ; Check XD disable bit > ; > xor r8, r8 > - mov rax, ASM_PFX(gStmXdSupported) > + lea rax, [ASM_PFX(gStmXdSupported)] > mov al, [rax] > cmp al, 0 > jz @StmXdDone1 > @@ -118,7 +118,7 @@ ASM_PFX(OnStmSetup): > call ASM_PFX(SmmStmSetup) > add rsp, 0x20 >=20 > - mov rax, ASM_PFX(gStmXdSupported) > + lea rax, [ASM_PFX(gStmXdSupported)] > mov al, [rax] > cmp al, 0 > jz .11 > @@ -139,7 +139,7 @@ ASM_PFX(OnStmTeardown): > ; Check XD disable bit > ; > xor r8, r8 > - mov rax, ASM_PFX(gStmXdSupported) > + lea rax, [ASM_PFX(gStmXdSupported)] > mov al, [rax] > cmp al, 0 > jz @StmXdDone2 > @@ -162,7 +162,7 @@ ASM_PFX(OnStmTeardown): > call ASM_PFX(SmmStmTeardown) > add rsp, 0x20 >=20 > - mov rax, ASM_PFX(gStmXdSupported) > + lea rax, [ASM_PFX(gStmXdSupported)] > mov al, [rax] > cmp al, 0 > jz .12 > -- > 2.8.0.windows.1