From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B8E5D221F93DC for ; Tue, 16 Jan 2018 05:15:36 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jan 2018 05:20:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,368,1511856000"; d="scan'208";a="10517619" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga008.jf.intel.com with ESMTP; 16 Jan 2018 05:20:55 -0800 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 16 Jan 2018 05:20:55 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 16 Jan 2018 05:20:54 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.189]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.159]) with mapi id 14.03.0319.002; Tue, 16 Jan 2018 21:20:52 +0800 From: "Yao, Jiewen" To: "Gao, Liming" , "edk2-devel@lists.01.org" CC: Andrew Fish , "Dong, Eric" , "Laszlo Ersek" , "Kinney, Michael D" Thread-Topic: [PATCH v2 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain Thread-Index: AQHTirtmILsa7k+phEOSl1DqRH/qUaN2ggKA Date: Tue, 16 Jan 2018 13:20:51 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA7F351@shsmsx102.ccr.corp.intel.com> References: <1515661515-6532-1-git-send-email-liming.gao@intel.com> In-Reply-To: <1515661515-6532-1-git-send-email-liming.gao@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZGI5Y2YwNGQtMTA5OS00MDE0LTg4MjEtOTJlMGQ4ODE0ZmI2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiI2OTJHUG4wUzVKTEg2REVyd1l5NlZmNEJoNEZhYXc4REcrMWhsY3RsRDQ0UmY2dzF4YzIzYnFaeXFxMnU0MnBiIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Jan 2018 13:15:37 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Gao, Liming > Sent: Thursday, January 11, 2018 5:05 PM > To: edk2-devel@lists.01.org > Cc: Andrew Fish ; Yao, Jiewen ; > Dong, Eric ; Laszlo Ersek ; Kinne= y, > Michael D > Subject: [PATCH v2 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass > XCODE5 tool chain >=20 > In V2, use mov rax, strict qword 0 to replace the hard code db. >=20 > Use the dummy address as jmp destination, and add the logic to fix up > the address to the absolute address at boot time. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Liming Gao > Cc: Andrew Fish > Cc: Jiewen Yao > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: Michael Kinney > --- > .../X64/ExceptionHandlerAsm.nasm | 27 > ++++++++++++++++------ > 1 file changed, 20 insertions(+), 7 deletions(-) >=20 > diff --git > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > index ba8993d..7b97810 100644 > --- > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > +++ > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas > m > @@ -1,5 +1,5 @@ > ;-----------------------------------------------------------------------= ------- ; > -; Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.
> +; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
> ; This program and the accompanying materials > ; are licensed and made available under the terms and conditions of the = BSD > License > ; which accompanies this distribution. The full text of the license may= be found > at > @@ -40,7 +40,7 @@ AsmIdtVectorBegin: > db 0x6a ; push #VectorNum > db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - > AsmIdtVectorBegin) / 32) ; VectorNum > push rax > - mov rax, ASM_PFX(CommonInterruptEntry) > + mov rax, strict qword 0 ; mov rax, > ASM_PFX(CommonInterruptEntry) > jmp rax > %endrep > AsmIdtVectorEnd: > @@ -50,7 +50,8 @@ HookAfterStubHeaderBegin: > @VectorNum: > db 0 ; 0 will be fixed > push rax > - mov rax, HookAfterStubHeaderEnd > + mov rax, strict qword 0 ; mov rax, > HookAfterStubHeaderEnd > +JmpAbsoluteAddress: > jmp rax > HookAfterStubHeaderEnd: > mov rax, rsp > @@ -260,8 +261,7 @@ HasErrorCode: > ; and make sure RSP is 16-byte aligned > ; > sub rsp, 4 * 8 + 8 > - mov rax, ASM_PFX(CommonExceptionHandler) > - call rax > + call ASM_PFX(CommonExceptionHandler) > add rsp, 4 * 8 + 8 >=20 > cli > @@ -369,11 +369,24 @@ DoIret: > ; comments here for definition of address map > global ASM_PFX(AsmGetTemplateAddressMap) > ASM_PFX(AsmGetTemplateAddressMap): > - mov rax, AsmIdtVectorBegin > + lea rax, [AsmIdtVectorBegin] > mov qword [rcx], rax > mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / > 32 > - mov rax, HookAfterStubHeaderBegin > + lea rax, [HookAfterStubHeaderBegin] > mov qword [rcx + 0x10], rax > + > +; Fix up CommonInterruptEntry address > + lea rax, [ASM_PFX(CommonInterruptEntry)] > + lea rcx, [AsmIdtVectorBegin] > +%rep 32 > + mov qword [rcx + (JmpAbsoluteAddress - 8 - > HookAfterStubHeaderBegin)], rax > + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32 > +%endrep > +; Fix up HookAfterStubHeaderEnd > + lea rax, [HookAfterStubHeaderEnd] > + lea rcx, [JmpAbsoluteAddress] > + mov qword [rcx - 8], rax > + > ret >=20 > ;-----------------------------------------------------------------------= -------------- > -- > 2.8.0.windows.1