From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4DDB72205B93E for ; Wed, 17 Jan 2018 22:08:44 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jan 2018 22:14:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,376,1511856000"; d="scan'208";a="10643482" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga007.jf.intel.com with ESMTP; 17 Jan 2018 22:14:04 -0800 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 17 Jan 2018 22:14:04 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 17 Jan 2018 22:14:03 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.189]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.152]) with mapi id 14.03.0319.002; Thu, 18 Jan 2018 14:14:01 +0800 From: "Yao, Jiewen" To: "Gao, Liming" , "edk2-devel@lists.01.org" Thread-Topic: [Patch] IntelFsp2WrapperPkg: Update BaseFspWrapperApiLib to pass XCODE5 build Thread-Index: AQHTkAZaJnoufBvAHkSL1QNlv2Jwz6N5JvNA Date: Thu, 18 Jan 2018 06:14:01 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA810BD@shsmsx102.ccr.corp.intel.com> References: <1516243487-3992-1-git-send-email-liming.gao@intel.com> In-Reply-To: <1516243487-3992-1-git-send-email-liming.gao@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOGQwNzczZDctMjczMy00MzRhLTk2MGMtODc3MzliYWEyYmJjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJDWVwvbGxQMjRXZDBnSWJnamZsQURuNlpmM1p3c2UyTHV0MUIwT1wvRXp1V0JCNHJnUlpqZjMweXZCaU5XM0tzMXcifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] IntelFsp2WrapperPkg: Update BaseFspWrapperApiLib to pass XCODE5 build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Jan 2018 06:08:44 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Gao, Liming > Sent: Thursday, January 18, 2018 10:45 AM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen > Subject: [Patch] IntelFsp2WrapperPkg: Update BaseFspWrapperApiLib to pass > XCODE5 build >=20 > XCODE5 doesn't support absolute addressing in the assembly code. > This change uses lea instruction to get the address. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Liming Gao > Cc: Jiewen Yao > --- > .../Library/BaseFspWrapperApiLib/X64/Thunk64To32.nasm | 10 > +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) >=20 > diff --git > a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nas > m > b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nas > m > index bcc6d70..a6ad6cf 100644 > --- > a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nas > m > +++ > b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/Thunk64To32.nas > m > @@ -1,5 +1,5 @@ > ; > -; Copyright (c) 2016, Intel Corporation. All rights reserved.
> +; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> ; This program and the accompanying materials > ; are licensed and made available under the terms and conditions of the = BSD > License > ; which accompanies this distribution. The full text of the license may= be found > at > @@ -81,7 +81,7 @@ ASM_PFX(AsmExecute32BitCode): > ; > mov rax, dword 0x10 ; load long mode selector > shl rax, 32 > - mov r9, ReloadCS ;Assume the ReloadCS is under 4G > + lea r9, [ReloadCS] ;Assume the ReloadCS is under 4G > or rax, r9 > push rax > ; > @@ -95,7 +95,7 @@ ASM_PFX(AsmExecute32BitCode): > ; save the 32-bit function entry and the return address into stack w= hich will > be > ; retrieve in compatibility mode. > ; > - mov rax, ReturnBack ;Assume the ReloadCS is under 4G > + lea rax, [ReturnBack] ;Assume the ReloadCS is under 4G > shl rax, 32 > or rax, rcx > push rax > @@ -110,7 +110,7 @@ ASM_PFX(AsmExecute32BitCode): > ; > mov rcx, dword 0x8 ; load compatible mode selector > shl rcx, 32 > - mov rdx, Compatible ; assume address < 4G > + lea rdx, [Compatible] ; assume address < 4G > or rcx, rdx > push rcx > retf > @@ -208,7 +208,7 @@ ReloadCS: > ; > pop r9 ; get CS > shl r9, 32 ; rcx[32..47] <- Cs > - mov rcx, .0 > + lea rcx, [.0] > or rcx, r9 > push rcx > retf > -- > 2.8.0.windows.1