From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6DC0A21E48F2A for ; Tue, 23 Jan 2018 22:04:44 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jan 2018 22:10:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,405,1511856000"; d="scan'208";a="29026600" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 23 Jan 2018 22:10:11 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 23 Jan 2018 22:10:11 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.189]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.152]) with mapi id 14.03.0319.002; Wed, 24 Jan 2018 14:10:09 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] IntelSiliconPkg IntelVTdDxe: Fix flush cache issue Thread-Index: AQHTlNMfX/SRs10mz06F5Zdyc0vAw6OCijxg Date: Wed, 24 Jan 2018 06:10:08 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AA8980A@shsmsx102.ccr.corp.intel.com> References: <1516771254-11588-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1516771254-11588-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYjk1NzE0MTYtZDQ0My00NTYyLWFhN2EtYjhkNmVkZTM0ZTNiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJvY1htQWFndFh1dldmUlpJVHRza3ZFZHB0ZzQzQVo2STBCRXczbHhlVVlTOVhXZUFqSStybXZaemZYejFGVEhjIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelSiliconPkg IntelVTdDxe: Fix flush cache issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Jan 2018 06:04:44 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable That is good catch. Thanks to fix it. Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Zeng, Star > Sent: Wednesday, January 24, 2018 1:21 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Yao, Jiewen > Subject: [PATCH] IntelSiliconPkg IntelVTdDxe: Fix flush cache issue >=20 > The patch fixes flush cache issue in > CreateSecondLevelPagingEntryTable(). >=20 > We found some video cards still not work even they have > been added to the exception list. >=20 > In CreateSecondLevelPagingEntryTable(), the check > "(BaseAddress >=3D MemoryLimit)" may be TRUE and "goto Done" > will be executed, then the FlushPageTableMemory operations > at the end of the function will be skipped. >=20 > Instead of "goto Done", this patch uses "break" to break > the for loops, then the FlushPageTableMemory operations > at the end of the function could have opportunity to be > executed. >=20 > The patch also fixed a miscalculation for Lvl3End. >=20 > Cc: Jiewen Yao > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 13 > +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) >=20 > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c > index 7bdc4a5146bd..bce5a45105d2 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at > @@ -226,7 +226,7 @@ CreateSecondLevelPagingEntryTable ( >=20 > Lvl3Start =3D RShiftU64 (BaseAddress, 30) & 0x1FF; > if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <=3D > EndAddress) { > - Lvl3End =3D SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY); > + Lvl3End =3D SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) - 1; > } else { > Lvl3End =3D RShiftU64 (EndAddress - 1, 30) & 0x1FF; > } > @@ -252,16 +252,21 @@ CreateSecondLevelPagingEntryTable ( > Lvl2PtEntry[Index2].Bits.PageSize =3D 1; > BaseAddress +=3D SIZE_2MB; > if (BaseAddress >=3D MemoryLimit) { > - goto Done; > + break; > } > } > FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB); > + if (BaseAddress >=3D MemoryLimit) { > + break; > + } > } > FlushPageTableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start], > (UINTN)&Lvl3PtEntry[Lvl3End + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]); > + if (BaseAddress >=3D MemoryLimit) { > + break; > + } > } > FlushPageTableMemory (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start], > (UINTN)&Lvl4PtEntry[Lvl4End + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]); >=20 > -Done: > return SecondLevelPagingEntry; > } >=20 > -- > 2.7.0.windows.1