From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6AC592215BD98 for ; Fri, 2 Feb 2018 04:34:11 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Feb 2018 04:39:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,448,1511856000"; d="scan'208,217";a="200829416" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga006.fm.intel.com with ESMTP; 02 Feb 2018 04:39:48 -0800 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 2 Feb 2018 04:39:48 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 2 Feb 2018 04:39:47 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.124]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.130]) with mapi id 14.03.0319.002; Fri, 2 Feb 2018 20:39:46 +0800 From: "Yao, Jiewen" To: Marvin H?user , "edk2-devel@lists.01.org" Thread-Topic: MinPlatformPkg/PlatformInit: FV code Thread-Index: AdOZ7dDRJ47e1o0uT++5ldvAkWh9yACMtQZQ Date: Fri, 2 Feb 2018 12:39:46 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AAAA932@shsmsx102.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiY2UwNDM5ZTAtNTljNy00ODhhLTkyNjgtZGUyYTg3ZmIxNGNiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ0aVh0U0RoeGtJUHM3OWVReTN2cDBzWlwvZVlwaEx2N3pxTzdRUUVYWkxmRW5JSkt1R3Jncm5XYmc1cDJDanZOMiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: MinPlatformPkg/PlatformInit: FV code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 12:34:11 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Excellent question. Comment inline. From: Marvin H?user [mailto:Marvin.Haeuser@outlook.com] Sent: Wednesday, January 31, 2018 1:54 AM To: edk2-devel@lists.01.org; Yao, Jiewen Subject: MinPlatformPkg/PlatformInit: FV code Dear developers, dear Jiewen, I have been investigating the devel-MinPlatform branch of edk2-platforms fo= r educational purposes and got two questions regarding the Firmware Volume = code in PlatformInitPreMem, if you do not mind. I assume the tree was teste= d, so most likely I misunderstood some things. 1. Why is a Firmware Volume HOB built to cover the entire flash range (h= ttps://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/= Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L379= )? Am I correct that this implies a FV spanning through the entire flash MM= IO range, which would then imply all other FVs are contained within it? Thi= s would make sense, however that's not what I saw in the KabylakeOpenBoardP= kg Flash Map, which has the NV Storage first (https://github.com/tianocore/= edk2-platforms/blob/devel-MinPlatform/Platform/Intel/KabylakeOpenBoardPkg/I= nclude/Fdf/FlashMapInclude.fdf#L25). [Jiewen] You are right. We should not use FD region for FV. Will fix it. 1. Why are FV Info PPIs installed for the UefiBoot and the OsBoot FVs (h= ttps://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/= Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L344= )? If I checked correctly, installing this PPI type will trigger PeiCore to= dispatch PEIMs in the FVs, however there are only DXE drivers in these. Wh= y are no FV HOBs installed, which are gotten by DxeCore? [Jiewen] In DxeIpl, PeiServicesFfsFindNextVolume() is used to search DxeCor= e. In PeiCore, PeiFfsFindNextVolume() calls FindNextCoreFvHandle() for DxeCore= one by one. If PcdFrameworkCompatibilitySupport is FALSE, it returns &Priv= ate->Fv[Instance] directly. And Fv[Instance] is added in FirmwareVolmeInfoPpiNotifyCallback(), when gEf= iPeiFirmwareVolumeInfo2PpiGuid is installed. So if PcdFrameworkCompatibilitySupport is FALSE, install PPI is the only wa= y to let PEI core discover DxeCore. Only if PcdFrameworkCompatibilitySupport is TRUE, install PPI is not requir= ed, but the FindNextCoreFvHandle() will install the PPI for the HobFv. The = result is same. Thank you Yao Jiewen Thanks in advance for your time! Best regards, Marvin.