From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9D23A21B02822 for ; Thu, 13 Sep 2018 06:38:06 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Sep 2018 06:38:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,369,1531810800"; d="scan'208";a="73977060" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga006.jf.intel.com with ESMTP; 13 Sep 2018 06:37:48 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 13 Sep 2018 06:37:47 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 13 Sep 2018 06:37:46 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.226]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.143]) with mapi id 14.03.0319.002; Thu, 13 Sep 2018 21:37:44 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Chaganty, Rangasai V" , "Chang, Tomson" , "Huang, Jenny" , "Chan, Amy" , "Ni, Ruiyu" Thread-Topic: [PATCH] IntelSiliconPkg IntelVTdDxe: Check HeaderType if func 0 is implemented Thread-Index: AQHUSysgoeBz6xFDnUiSnemcvqTaoKTuN30w Date: Thu, 13 Sep 2018 13:37:43 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AD5A2B2@shsmsx102.ccr.corp.intel.com> References: <1536820151-15264-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1536820151-15264-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZmMwYjJjYTEtOTE5MS00MzY2LWFjNTgtM2RiZDFhNjgwMzRmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiQVZzWW0xRmtoMEJKb2laZDd1ZE40XC9rZmp5QnpJQUh3Q0doZXFVbEp2TlVmYXdRNXNtT2dUQlZnRURKYU1rVVEifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelSiliconPkg IntelVTdDxe: Check HeaderType if func 0 is implemented X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 13 Sep 2018 13:38:06 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: jiewen.yao@intel.com > -----Original Message----- > From: Zeng, Star > Sent: Thursday, September 13, 2018 2:29 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Yao, Jiewen ; > Chaganty, Rangasai V ; Chang, Tomson > ; Huang, Jenny ; Chan, > Amy ; Ni, Ruiyu > Subject: [PATCH] IntelSiliconPkg IntelVTdDxe: Check HeaderType if func 0 = is > implemented >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1169 >=20 > Current code checks HeaderType of Function 0 even Function 0 is not > implemented. HeaderType value will be 0xFF if Function 0 is not > implemented, then MaxFunction will be set to PCI_MAX_FUNC + 1. >=20 > The code can be optimized to only check HeaderType if Function 0 is > implemented. >=20 > Test done: > With this patch, the result is same with the result after the patch at > https://lists.01.org/pipermail/edk2-devel/2018-September/029623.html. >=20 > Cc: Jiewen Yao > Cc: Rangasai V Chaganty > Cc: Tomson Chang > Cc: Jenny Huang > Cc: Amy Chan > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c | 20 > ++++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) >=20 > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c > index 305995de032c..6ae5df589c1e 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c > @@ -231,19 +231,13 @@ ScanPciBus ( > UINT8 HeaderType; > UINT8 BaseClass; > UINT8 SubClass; > - UINT32 MaxFunction; > UINT16 VendorID; > UINT16 DeviceID; > EFI_STATUS Status; >=20 > // Scan the PCI bus for devices > - for (Device =3D 0; Device < PCI_MAX_DEVICE + 1; Device++) { > - HeaderType =3D PciSegmentRead8 > (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, 0, > PCI_HEADER_TYPE_OFFSET)); > - MaxFunction =3D PCI_MAX_FUNC + 1; > - if ((HeaderType & HEADER_TYPE_MULTI_FUNCTION) =3D=3D 0x00) { > - MaxFunction =3D 1; > - } > - for (Function =3D 0; Function < MaxFunction; Function++) { > + for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) { > + for (Function =3D 0; Function <=3D PCI_MAX_FUNC; Function++) { > VendorID =3D PciSegmentRead16 > (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, > PCI_VENDOR_ID_OFFSET)); > DeviceID =3D PciSegmentRead16 > (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, > PCI_DEVICE_ID_OFFSET)); > if (VendorID =3D=3D 0xFFFF && DeviceID =3D=3D 0xFFFF) { > @@ -275,6 +269,16 @@ ScanPciBus ( > } > } > } > + > + if (Function =3D=3D 0) { > + HeaderType =3D PciSegmentRead8 > (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, 0, > PCI_HEADER_TYPE_OFFSET)); > + if ((HeaderType & HEADER_TYPE_MULTI_FUNCTION) =3D=3D 0x00) { > + // > + // It is not a multi-function device, do not scan other functi= ons. > + // > + break; > + } > + } > } > } >=20 > -- > 2.7.0.windows.1