From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 54EC221159809 for ; Wed, 26 Sep 2018 17:40:32 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2018 17:40:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,308,1534834800"; d="scan'208";a="92222682" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga004.fm.intel.com with ESMTP; 26 Sep 2018 17:39:51 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 26 Sep 2018 17:39:52 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 26 Sep 2018 17:39:52 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.140]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.27]) with mapi id 14.03.0319.002; Thu, 27 Sep 2018 08:39:50 +0800 From: "Yao, Jiewen" To: "Chiu, Chasel" , "edk2-devel@lists.01.org" CC: "Gao, Liming" , "Zhu, Yonghong" Thread-Topic: [PATCH] IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignment Thread-Index: AQHUVYx02QywWSs84U23/LW9EaOVDqUDSgxQ Date: Thu, 27 Sep 2018 00:39:49 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AD9E844@shsmsx102.ccr.corp.intel.com> References: <20180926112913.11576-1-chasel.chiu@intel.com> In-Reply-To: <20180926112913.11576-1-chasel.chiu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYzVkOGVmZWQtOWY4OS00NjRiLWI2N2ItNDkwNWY1NDM2NWE4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiT3QxOGxZOGFYN0FNTXcxMmdjbVdiUG9ibUV0S1hGZ2pcLzZLR2wxb0FjcVpyS1JIR0VLaWsyMGMzcE95MlpoVEoifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Sep 2018 00:40:32 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: jiewen.yao@intel.com > -----Original Message----- > From: Chiu, Chasel > Sent: Wednesday, September 26, 2018 7:29 PM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Gao, Liming > ; Zhu, Yonghong ; Chiu, > Chasel > Subject: [PATCH] IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto > assignment >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1211 >=20 > For reducing maintenance effort, the UPD offset can be > automatic assigned by GenCfgOpt.py following by alignment > requirements. >=20 > The usage model as below: > . If UPD offset in DSC file are all '*', GenCfgOpt.py will > assign offset for all UPD automatically. In this case no > need to manually hardcode offset to all UPD in DSC. >=20 > . If UPD offset in DSC file are all not '*', GenCfgOpt.py > will use hardcoded offset directly (original usage model) >=20 > . Tool does not support mixing scenario so UPD offset in DSC > should be all '*' or all hardcoded but not mixed. >=20 > In auto mode UPD offset will be assigned following natural > alignment (size aligned) rule and the whole structure size > will align to either 32bits or 64bits depends on maximal UPD > size in the structure. >=20 > Test: Verified by both UPD offset hardcoded or '*' in DSC and > generated UPD header files are correct. >=20 > Cc: Jiewen Yao > Cc: Gao Liming > Cc: Zhu Yonghong > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/Tools/GenCfgOpt.py | 68 > +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 65 insertions(+), 3 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py > b/IntelFsp2Pkg/Tools/GenCfgOpt.py > index c9b7bc5373..9b8943b702 100644 > --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py > +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py > @@ -1,6 +1,6 @@ > ## @ GenCfgOpt.py > # > -# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> # This program and the accompanying materials are licensed and made > available under > # the terms and conditions of the BSD License that accompanies this > distribution. > # The full text of the license may be found at > @@ -418,6 +418,8 @@ EndList > return "" >=20 > def ParseDscFile (self, DscFile, FvDir): > + Hardcode =3D False > + AutoAlign =3D False > self._CfgItemList =3D [] > self._CfgPageDict =3D {} > self._CfgBlkDict =3D {} > @@ -438,6 +440,8 @@ EndList > DscLines =3D DscFd.readlines() > DscFd.close() >=20 > + MaxAlign =3D 32 #Default align to 32, but if there are 64 bit = unit, > align to 64 > + SizeAlign =3D 0 #record the struct max align > while len(DscLines): > DscLine =3D DscLines.pop(0).strip() > Handle =3D False > @@ -464,6 +468,7 @@ EndList > ConfigDict['comment'] =3D '' > ConfigDict['subreg'] =3D [] > IsUpdSect =3D True > + Offset =3D 0 > else: > if IsDefSect or IsPcdSect or IsUpdSect or IsVpdSect: > if re.match("^!else($|\s+#.+)", DscLine): > @@ -530,6 +535,7 @@ EndList > NewDscLines =3D > IncludeDsc.readlines() > IncludeDsc.close() > DscLines =3D NewDscLines + > DscLines > + Offset =3D 0 > else: > if DscLine.startswith('!'): > print("ERROR: > Unrecoginized directive for line '%s'" % DscLine) > @@ -620,13 +626,22 @@ EndList >=20 > # Check VPD/UPD > if IsUpdSect: > - Match =3D > re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s*\|\s*(0x[0-9A-F]+)\s*\|\s*(\= d+ > |0x[0-9a-fA-F]+)\s*\|\s*(.+)",DscLine) > + Match =3D > re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s*\|\s*(0x[0-9A-F]+|\*)\s*\|\s= *( > \d+|0x[0-9a-fA-F]+)\s*\|\s*(.+)",DscLine) > else: > Match =3D > re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s*\|\s*(0x[0-9A-F]+)(?:\s*\|\s= *(. > +))?", DscLine) > if Match: > ConfigDict['space'] =3D Match.group(1) > ConfigDict['cname'] =3D Match.group(2) > - ConfigDict['offset'] =3D int (Match.group(3), 16) > + if Match.group(3) !=3D '*': > + Hardcode =3D True > + Offset =3D int (Match.group(3), 16) > + else: > + AutoAlign =3D True > + > + if Hardcode and AutoAlign: > + print("Hardcode and auto-align mixed mode is > not supported by GenCfgOpt") > + raise SystemExit > + ConfigDict['offset'] =3D Offset > if ConfigDict['order'] =3D=3D -1: > ConfigDict['order'] =3D ConfigDict['offset'] << = 8 > else: > @@ -638,6 +653,7 @@ EndList > Length =3D int (Match.group(4), 16) > else : > Length =3D int (Match.group(4)) > + Offset +=3D Length > else: > Value =3D Match.group(4) > if Value is None: > @@ -665,6 +681,52 @@ EndList > ConfigDict['help'] =3D '' > ConfigDict['type'] =3D '' > ConfigDict['option'] =3D '' > + if IsUpdSect and AutoAlign: > + ItemLength =3D int(ConfigDict['length']) > + ItemOffset =3D int(ConfigDict['offset']) > + ItemStruct =3D ConfigDict['struct'] > + Unit =3D 1 > + if ItemLength in [1, 2, 4, 8] and not > ConfigDict['value'].startswith('{'): > + Unit =3D ItemLength > + # If there are 64 bit unit, align to 64 > + if Unit =3D=3D 8: > + MaxAlign =3D 64 > + SizeAlign =3D 8 > + if ItemStruct !=3D '': > + UnitDict =3D {'UINT8':1, 'UINT16':2, > 'UINT32':4, 'UINT64':8} > + if ItemStruct in ['UINT8', 'UINT16', > 'UINT32', 'UINT64']: > + Unit =3D UnitDict[ItemStruct] > + # If there are 64 bit unit, align to 64 > + if Unit =3D=3D 8: > + MaxAlign =3D 64 > + SizeAlign =3D max(SizeAlign, Unit) > + if (ConfigDict['embed'].find(':START') !=3D -1): > + Base =3D ItemOffset > + SubOffset =3D ItemOffset - Base > + SubRemainder =3D SubOffset % Unit > + if SubRemainder: > + Diff =3D Unit - SubRemainder > + Offset =3D Offset + Diff > + ItemOffset =3D ItemOffset + Diff > + > + if (ConfigDict['embed'].find(':END') !=3D -1): > + Remainder =3D Offset % (MaxAlign/8) # > MaxAlign is either 32 or 64 > + if Remainder: > + Diff =3D (MaxAlign/8) - Remainder > + Offset =3D Offset + Diff > + ItemOffset =3D ItemOffset + Diff > + MaxAlign =3D 32 > # Reset to default 32 align when struct end > + if (ConfigDict['cname'] =3D=3D 'UpdTerminator'): > + # ItemLength is the size of > UpdTerminator > + # Itemlength might be 16, 32, or 64 > + # Struct align to 64 if UpdTerminator > + # or struct size is 64 bit, else align to 32 > + Remainder =3D Offset % max(ItemLength/8, > 4, SizeAlign) > + Offset =3D Offset + ItemLength > + if Remainder: > + Diff =3D max(ItemLength/8, 4, > SizeAlign) - Remainder > + ItemOffset =3D ItemOffset + Diff > + ConfigDict['offset'] =3D ItemOffset >=20 > self._CfgItemList.append(ConfigDict.copy()) > ConfigDict['name'] =3D '' > -- > 2.13.3.windows.1