From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EB9C721162CD9 for ; Wed, 10 Oct 2018 01:00:02 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Oct 2018 01:00:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,363,1534834800"; d="scan'208";a="98084705" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga001.jf.intel.com with ESMTP; 10 Oct 2018 00:58:15 -0700 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 10 Oct 2018 00:58:15 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 10 Oct 2018 00:58:15 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.217]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.183]) with mapi id 14.03.0319.002; Wed, 10 Oct 2018 15:58:11 +0800 From: "Yao, Jiewen" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , Laszlo Ersek Thread-Topic: [edk2] [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table. Thread-Index: AQHUYG0jz+05hFA0Y0uTp6c25jUkgKUYHD+g Date: Wed, 10 Oct 2018 07:58:10 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503ADDBB86@shsmsx102.ccr.corp.intel.com> References: <20181010074339.7804-1-eric.dong@intel.com> In-Reply-To: <20181010074339.7804-1-eric.dong@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZDA2ZWEyYjAtMWU4Ny00ZGM0LTk2NDEtODA1MzdlOWRmMDkzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiczdGYWFKTE9sQ3FqZDRrTTBLU3R5TkIrOVwvcWtjSGhiVjJYdjZIaTRZaHNycXcrRFVHR3prT1wvVnFYTGk2aDR5In0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Oct 2018 08:00:03 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hey I do not think we need add if (sizeof (UINTN) =3D=3D sizeof (UINT32)) This piece of code assume PEI is 32 bit. The following code AsmEnablePaging64() does not work for X64. Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Eric Dong > Sent: Wednesday, October 10, 2018 3:44 PM > To: edk2-devel@lists.01.org > Cc: Ni, Ruiyu ; Laszlo Ersek > Subject: [edk2] [Patch] UefiCpuPkg/S3Resume2Pei: disable paging before > creating new page table. >=20 > V4: > Only disable paging when it is enabled. >=20 > V3 changes: > No need to change inf file. >=20 > V2 changes: > Only disable paging in 32 bit mode, no matter it is enable or not. >=20 > V1 changes: > PEI Stack Guard needs to enable paging. This might cause #GP if code > trying to write CR3 register with PML4 page table while the processor > is enabled with PAE paging. >=20 > Simply disabling paging before updating CR3 can solve this conflict. >=20 > It's an regression caused by change: > 0a0d5296e448fc350de1594c49b9c0deff7fad60 >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1232 >=20 > Change-Id: I99bfdba5daa48a95a4c4ef97eeca1af086558957 > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Cc: Jian J Wang > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by:Eric Dong > Signed-off-by: Eric Dong > --- > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) >=20 > diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > index f164c1713b..c059c42db5 100644 > --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > @@ -964,6 +964,7 @@ S3RestoreConfig2 ( > VOID *GuidHob; > BOOLEAN > Build4GPageTableOnly; > BOOLEAN > InterruptStatus; > + IA32_CR0 CR0Reg; >=20 > TempAcpiS3Context =3D 0; > TempEfiBootScriptExecutorVariable =3D 0; > @@ -1105,6 +1106,17 @@ S3RestoreConfig2 ( > // > SetInterruptState (InterruptStatus); >=20 > + if (sizeof (UINTN) =3D=3D sizeof (UINT32)) { > + CR0Reg.UintN =3D AsmReadCr0 (); > + if (CR0Reg.Bits.PG !=3D 0) { > + // > + // We're in 32-bit mode, with paging enabled. We can't set CR3 > to > + // the 64-bit page tables without first disabling paging. > + // > + CR0Reg.Bits.PG =3D 0; > + AsmWriteCr0 (CR0Reg.UintN); > + } > + } > AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3); >=20 > // > -- > 2.15.0.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel