From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 825952117AE75 for ; Wed, 24 Oct 2018 04:22:38 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Oct 2018 04:22:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,420,1534834800"; d="scan'208";a="94613331" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga003.jf.intel.com with ESMTP; 24 Oct 2018 04:22:37 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 24 Oct 2018 04:22:37 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 24 Oct 2018 04:22:37 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.84]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.199]) with mapi id 14.03.0415.000; Wed, 24 Oct 2018 19:22:35 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Zeng, Star" Thread-Topic: [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force no early access attr request Thread-Index: AQHUa0ojymJDW/RFlkik6JKtM+egwaUuQRNA Date: Wed, 24 Oct 2018 11:22:34 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503AE26320@shsmsx102.ccr.corp.intel.com> References: <1540351913-97208-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1540351913-97208-1-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNDU1NWZmZTEtN2I4NC00N2JhLTljNTItOGI1ZjAyMWYzNmM0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidGlCTFV1RzZyM25Ua3VGdDFYMjhYWGNNR3F6SDB5T21WS0ZxQU9qQnBXK0Y5WEo1RzhSTlUwU3pBejNcL25oNjgifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelSiliconPkg VTdDxe: Option to force no early access attr request X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Oct 2018 11:22:38 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: jiewen.yao@intel.com > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Star Zeng > Sent: Wednesday, October 24, 2018 11:32 AM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Zeng, Star > Subject: [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force no early > access attr request >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1272 >=20 > To have high confidence in usage for platform, add option (BIT2 of > PcdVTdPolicyPropertyMask) to force no IOMMU access attribute request > recording before DMAR table is installed. >=20 > Check PcdVTdPolicyPropertyMask BIT2 before RequestAccessAttribute() > and ProcessRequestedAccessAttribute(), then RequestAccessAttribute(), > ProcessRequestedAccessAttribute() and mAccessRequestXXX variables > could be optimized by compiler when PcdVTdPolicyPropertyMask BIT2 =3D 1. >=20 > Test done: > 1: Created case that has IOMMU access attribute request before DMAR > table is installed, ASSERT was triggered after setting > PcdVTdPolicyPropertyMask BIT2 to 1. >=20 > 2. Confirmed RequestAccessAttribute(), ProcessRequestedAccessAttribute() > and mAccessRequestXXX variables were optimized by compiler after > setting PcdVTdPolicyPropertyMask BIT2 to 1. >=20 > Cc: Jiewen Yao > Cc: Rangasai V Chaganty > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c | 8 +++++++- > IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c | 7 +++++++ > IntelSiliconPkg/IntelSiliconPkg.dec | 1 + > 3 files changed, 15 insertions(+), 1 deletion(-) >=20 > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > index 86d50eb6f288..7784545631b3 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > @@ -515,7 +515,13 @@ SetupVtd ( >=20 > ParseDmarAcpiTableRmrr (); >=20 > - ProcessRequestedAccessAttribute (); > + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) =3D=3D 0) { > + // > + // Support IOMMU access attribute request recording before DMAR > table is installed. > + // Here is to process the requests. > + // > + ProcessRequestedAccessAttribute (); > + } >=20 > for (Index =3D 0; Index < mVtdUnitNumber; Index++) { > DEBUG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index, > mVtdUnitInformation[Index].Segment)); > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > index 25d7c80af1d4..09948ce50e94 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > @@ -254,6 +254,13 @@ VTdSetAttribute ( > // Record the entry to driver global variable. > // As such once VTd is activated, the setting can be adopted. > // > + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) !=3D 0) { > + // > + // Force no IOMMU access attribute request recording before > DMAR table is installed. > + // > + ASSERT_EFI_ERROR (EFI_NOT_READY); > + return EFI_NOT_READY; > + } > Status =3D RequestAccessAttribute (Segment, SourceId, DeviceAddress, > Length, IoMmuAccess); > } else { > PERF_CODE ( > diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec > b/IntelSiliconPkg/IntelSiliconPkg.dec > index b9646d773b95..900e8f63c64d 100644 > --- a/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -64,6 +64,7 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, > PcdsDynamic, PcdsDynamicEx] > ## The mask is used to control VTd behavior.

> # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. = If > VTD_INFO_PPI is installed in PEI.) > # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in > normal boot. EndOfPEI in S3) > + # BIT2: Force no IOMMU access attribute request recording before > DMAR table is installed. > # @Prompt The policy for VTd driver behavior. >=20 > gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x000 > 00002 >=20 > -- > 2.7.0.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel