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From: "Yao, Jiewen" <jiewen.yao@intel.com>
To: "Ni, Ruiyu" <ruiyu.ni@intel.com>,
	"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Subject: Re: [PATCH v3] MdeModulePkg/PiSmmIpl: Do not reset SMRAM to UC when CPU driver runs
Date: Thu, 1 Nov 2018 01:52:46 +0000	[thread overview]
Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F3C0419@shsmsx102.ccr.corp.intel.com> (raw)
In-Reply-To: <20181030025128.60448-1-ruiyu.ni@intel.com>

Thanks. SMRR is used to prevent cache poisoning attack. IMHO, the assumption is valid.

Reviewed-by: Jiewen.yao@intel.com


> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ni,
> Ruiyu
> Sent: Tuesday, October 30, 2018 10:51 AM
> To: edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Yao, Jiewen
> <jiewen.yao@intel.com>
> Subject: [edk2] [PATCH v3] MdeModulePkg/PiSmmIpl: Do not reset SMRAM
> to UC when CPU driver runs
> 
> Today's PiSmmIpl implementation initially sets SMRAM to WB to speed
> up the SMM core/modules loading before SMM CPU driver runs.
> When SMM CPU driver runs, PiSmmIpl resets the SMRAM to UC. It's done
> in SmmIplDxeDispatchEventNotify().
> COMM_BUFFER_SMM_DISPATCH_RESTART
> is returned from SMM core that SMM CPU driver is just dispatched.
> 
> Since now the SMRR is widely used to control the SMRAM cache setting.
> It's not needed to reset the SMRAM to UC anymore.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Michael Kinney <michael.d.kinney@intel.com>
> ---
>  MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c | 15 ++-------------
>  1 file changed, 2 insertions(+), 13 deletions(-)
> 
> diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
> b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
> index f8cbe1704b..2fb877127b 100644
> --- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
> +++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
> @@ -672,21 +672,10 @@ SmmIplDxeDispatchEventNotify (
>        return;
>      }
> 
> -    //
> -    // Attempt to reset SMRAM cacheability to UC
> -    // Assume CPU AP is available at this time
> -    //
> -    Status = gDS->SetMemorySpaceAttributes(
> -                    mSmramCacheBase,
> -                    mSmramCacheSize,
> -                    EFI_MEMORY_UC
> -                    );
> -    if (EFI_ERROR (Status)) {
> -      DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window
> to EFI_MEMORY_UC\n"));
> -    }
> -
>      //
>      // Close all SMRAM ranges to protect SMRAM
> +    // NOTE: SMRR is enabled by CPU SMM driver by calling
> SmmCpuFeaturesInitializeProcessor() from SmmCpuFeaturesLib
> +    //       so no need to reset the SMRAM to UC in MTRR.
>      //
>      Status = mSmmAccess->Close (mSmmAccess);
>      ASSERT_EFI_ERROR (Status);
> --
> 2.16.1.windows.1
> 
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel


      reply	other threads:[~2018-11-01  1:52 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-30  2:51 [PATCH v3] MdeModulePkg/PiSmmIpl: Do not reset SMRAM to UC when CPU driver runs Ruiyu Ni
2018-11-01  1:52 ` Yao, Jiewen [this message]

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