From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2352621184AC8 for ; Wed, 31 Oct 2018 18:52:50 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Oct 2018 18:52:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,450,1534834800"; d="scan'208";a="96731951" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga003.jf.intel.com with ESMTP; 31 Oct 2018 18:52:50 -0700 Received: from fmsmsx152.amr.corp.intel.com (10.18.125.5) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 31 Oct 2018 18:52:50 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX152.amr.corp.intel.com (10.18.125.5) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 31 Oct 2018 18:52:49 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.84]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.102]) with mapi id 14.03.0415.000; Thu, 1 Nov 2018 09:52:47 +0800 From: "Yao, Jiewen" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" Thread-Topic: [edk2] [PATCH v3] MdeModulePkg/PiSmmIpl: Do not reset SMRAM to UC when CPU driver runs Thread-Index: AQHUb/tMX1XUE9x/20KEJ5Pqkym6baU6Kjyw Date: Thu, 1 Nov 2018 01:52:46 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F3C0419@shsmsx102.ccr.corp.intel.com> References: <20181030025128.60448-1-ruiyu.ni@intel.com> In-Reply-To: <20181030025128.60448-1-ruiyu.ni@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWYyMTQ3MWUtMWUxYy00OTQwLTlkMWQtMjk5M2JhY2FlMzg5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMFVkaXN0SFFFREVDTjY3alwvakN5TmZnSmxvMldJRWhcL1FlYmNwaFRTWmREQWpVRlFVUHAxU1wvODcrdFlDOWxFMCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3] MdeModulePkg/PiSmmIpl: Do not reset SMRAM to UC when CPU driver runs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Nov 2018 01:52:51 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks. SMRR is used to prevent cache poisoning attack. IMHO, the assumptio= n is valid. Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ni= , > Ruiyu > Sent: Tuesday, October 30, 2018 10:51 AM > To: edk2-devel@lists.01.org > Cc: Kinney, Michael D ; Yao, Jiewen > > Subject: [edk2] [PATCH v3] MdeModulePkg/PiSmmIpl: Do not reset SMRAM > to UC when CPU driver runs >=20 > Today's PiSmmIpl implementation initially sets SMRAM to WB to speed > up the SMM core/modules loading before SMM CPU driver runs. > When SMM CPU driver runs, PiSmmIpl resets the SMRAM to UC. It's done > in SmmIplDxeDispatchEventNotify(). > COMM_BUFFER_SMM_DISPATCH_RESTART > is returned from SMM core that SMM CPU driver is just dispatched. >=20 > Since now the SMRR is widely used to control the SMRAM cache setting. > It's not needed to reset the SMRAM to UC anymore. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ruiyu Ni > Cc: Jiewen Yao > Cc: Michael Kinney > --- > MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c | 15 ++------------- > 1 file changed, 2 insertions(+), 13 deletions(-) >=20 > diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c > b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c > index f8cbe1704b..2fb877127b 100644 > --- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c > +++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c > @@ -672,21 +672,10 @@ SmmIplDxeDispatchEventNotify ( > return; > } >=20 > - // > - // Attempt to reset SMRAM cacheability to UC > - // Assume CPU AP is available at this time > - // > - Status =3D gDS->SetMemorySpaceAttributes( > - mSmramCacheBase, > - mSmramCacheSize, > - EFI_MEMORY_UC > - ); > - if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window > to EFI_MEMORY_UC\n")); > - } > - > // > // Close all SMRAM ranges to protect SMRAM > + // NOTE: SMRR is enabled by CPU SMM driver by calling > SmmCpuFeaturesInitializeProcessor() from SmmCpuFeaturesLib > + // so no need to reset the SMRAM to UC in MTRR. > // > Status =3D mSmmAccess->Close (mSmmAccess); > ASSERT_EFI_ERROR (Status); > -- > 2.16.1.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel