From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C746B21B02822 for ; Tue, 6 Nov 2018 18:26:59 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2018 18:26:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,474,1534834800"; d="scan'208";a="277724199" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga005.fm.intel.com with ESMTP; 06 Nov 2018 18:26:57 -0800 Received: from fmsmsx161.amr.corp.intel.com (10.18.125.9) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 6 Nov 2018 18:26:57 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX161.amr.corp.intel.com (10.18.125.9) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 6 Nov 2018 18:26:56 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.84]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.117]) with mapi id 14.03.0415.000; Wed, 7 Nov 2018 10:26:54 +0800 From: "Yao, Jiewen" To: "Chiu, Chasel" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH v2] IntelFsp2WrapperPkg: Support FSP Dispatch mode Thread-Index: AQHUdkEbkqp1xitSp0iQdjXRrXi+D6VDliKA Date: Wed, 7 Nov 2018 02:26:54 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F3D72B0@shsmsx102.ccr.corp.intel.com> References: <20181107022446.13152-1-chasel.chiu@intel.com> In-Reply-To: <20181107022446.13152-1-chasel.chiu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZDc2MWUwYjQtYjUzNi00NDcyLTg2NTEtZmUwNWQwNGU4NDcxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiaHJaYnlhU05FM3JxK1wvMmJHd09DNWxjSjVseVFvYTZhUzFLaFFhMlB3SzB5Q2RyWVdxRkhnc0htWkVhaXo3MEoifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2] IntelFsp2WrapperPkg: Support FSP Dispatch mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Nov 2018 02:27:00 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jiewen.yao@intel.com > -----Original Message----- > From: Chiu, Chasel > Sent: Wednesday, November 7, 2018 10:25 AM > To: edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Desimone, Nathaniel L > ; Chiu, Chasel > Subject: [PATCH v2] IntelFsp2WrapperPkg: Support FSP Dispatch mode >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1300 >=20 > Provides PCD selection for FSP Wrapper to support Dispatch > mode. Also PcdFspmBaseAddress should support Dynamic for > recovery scenario (multiple FSP-M binary in flash) >=20 > Test: Verified on internal platform and both API and > DISPATCH modes booted successfully. >=20 > Cc: Jiewen Yao > Cc: Desimone Nathaniel L > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu > --- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 20 > ++++++++++++++++---- > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 14 > ++++++++++++-- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 3 ++- > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++- > IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 13 > +++++++++++-- > 5 files changed, 43 insertions(+), 10 deletions(-) >=20 > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > index 7b7c5f5d86..fa0441ce6c 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > @@ -3,7 +3,7 @@ > register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi > notify to call FspSiliconInit API. >=20 > - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the > BSD License > which accompanies this distribution. The full text of the license may= be > found at > @@ -65,7 +65,7 @@ PeiFspMemoryInit ( > FspHobListPtr =3D NULL; > FspmUpdDataPtr =3D NULL; >=20 > - FspmHeaderPtr =3D (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 > (PcdFspmBaseAddress)); > + FspmHeaderPtr =3D (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 > (PcdFspmBaseAddress)); > DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr)); > if (FspmHeaderPtr =3D=3D NULL) { > return EFI_DEVICE_ERROR; > @@ -155,8 +155,20 @@ FspmWrapperInit ( > { > EFI_STATUS Status; >=20 > - Status =3D PeiFspMemoryInit (); > - ASSERT_EFI_ERROR (Status); > + Status =3D EFI_SUCCESS; > + > + if (FixedPcdGet8 (PcdFspModeSelection) =3D=3D 1) { > + Status =3D PeiFspMemoryInit (); > + ASSERT_EFI_ERROR (Status); > + } else { > + PeiServicesInstallFvInfoPpi ( > + NULL, > + (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress), > + (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFspmBaseAddress))->FvLength, > + NULL, > + NULL > + ); > + } >=20 > return Status; > } > diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > index 70dac7a414..87dd61e5c5 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > @@ -3,7 +3,7 @@ > register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi > notify to call FspSiliconInit API. >=20 > - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the > BSD License > which accompanies this distribution. The full text of the license may= be > found at > @@ -349,7 +349,17 @@ FspsWrapperPeimEntryPoint ( > { > DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n")); >=20 > - FspsWrapperInit (); > + if (FixedPcdGet8 (PcdFspModeSelection) =3D=3D 1) { > + FspsWrapperInit (); > + } else { > + PeiServicesInstallFvInfoPpi ( > + NULL, > + (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress), > + (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 > (PcdFspsBaseAddress))->FvLength, > + NULL, > + NULL > + ); > + } >=20 > return EFI_SUCCESS; > } > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index 542356b582..b3776a80f3 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -6,7 +6,7 @@ > # register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi > # notify to call FspSiliconInit API. > # > -# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. > # > # This program and the accompanying materials > # are licensed and made available under the terms and conditions of the > BSD License > @@ -61,6 +61,7 @@ > [Pcd] > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## > CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## > CONSUMES >=20 > [Sources] > FspmWrapperPeim.c > diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index cd87a99c40..910286982b 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -6,7 +6,7 @@ > # register TemporaryRamDonePpi to call TempRamExit API, and register > MemoryDiscoveredPpi > # notify to call FspSiliconInit API. > # > -# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. > # > # This program and the accompanying materials > # are licensed and made available under the terms and conditions of the > BSD License > @@ -68,6 +68,7 @@ > [Pcd] > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## > CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## > CONSUMES >=20 > [Guids] > gFspHobGuid ## CONSUMES ## HOB > diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > index 69df16452d..96f2858fb4 100644 > --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > @@ -71,9 +71,8 @@ > ## Indicate the PEI memory size platform want to report >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000 > |UINT32|0x40000005 >=20 > - ## This is the base address of FSP-T/M/S > + ## This is the base address of FSP-T >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT3 > 2|0x00000300 > - > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT > 32|0x00000301 >=20 > ## This PCD indicates if FSP APIs are skipped from FSP wrapper.
> # If a bit is set, that means this FSP API is skipped.
> @@ -93,7 +92,17 @@ > # @Prompt Skip FSP API from FSP wrapper. >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x4 > 0000009 >=20 > + ## This PCD decides how Wrapper code utilizes FSP > + # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without > calling FSP API) > + # 1: API mode (FSP Wrapper will call FSP API) > + # > + > gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UIN > T8|0x4000000A > + > [PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx] > + # > + ## These are the base address of FSP-M/S > + # > + > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT > 32|0x00001000 >=20 > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT > 32|0x00001001 > # > # To provide flexibility for platform to pre-allocate FSP UPD buffer > -- > 2.13.3.windows.1