From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DEA7A2119A46D for ; Mon, 17 Dec 2018 00:30:53 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Dec 2018 00:30:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,364,1539673200"; d="scan'208";a="99289328" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2018 00:30:53 -0800 Received: from fmsmsx157.amr.corp.intel.com (10.18.116.73) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 17 Dec 2018 00:30:52 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX157.amr.corp.intel.com (10.18.116.73) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 17 Dec 2018 00:30:52 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.182]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.222]) with mapi id 14.03.0415.000; Mon, 17 Dec 2018 16:30:51 +0800 From: "Yao, Jiewen" To: "Yao, Jiewen" , Ard Biesheuvel , Leif Lindholm CC: "edk2-devel@lists.01.org" , "Zhang, Chao B" , "Gao, Liming" Thread-Topic: [PATCH 05/13] MdePkg/Library/BaseLib/AArch64: Add AsmLfence function Thread-Index: AQHUlazh9asijuz/jUi0/lqlY+s7lKWCOEig///PW4CAAAbjAIAAidDAgAABmLA= Date: Mon, 17 Dec 2018 08:30:50 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F457F7E@shsmsx102.ccr.corp.intel.com> References: <1544789607-11316-1-git-send-email-jagadeesh.ujja@arm.com> <1544789607-11316-6-git-send-email-jagadeesh.ujja@arm.com> <4A89E2EF3DFEDB4C8BFDE51014F606A14E38D42E@SHSMSX104.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C503F457847@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C503F457F55@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503F457F55@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNWFmZmNmZDItMzgzYi00ZDVhLTg5OWItOGQzMjBjNWU1OTVmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMlZQakNPMFNpd2hJUUoxWkxEYnlBWDJocUlPYUdkMjdJZGZjaEtsdnlRUXpnSTdSRmQwOWxnVDNOTjdpdTZDbSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: request-justification,no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 05/13] MdePkg/Library/BaseLib/AArch64: Add AsmLfence function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Dec 2018 08:30:54 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I reviewed the ARM white paper - file:///C:/Users/jyao1/Downloads/Cache_Spe= culation_Side-channels-v2.4.pdf I agree with you that LoadFence might not be the best idea. How about SpeculationBarrier() ? Thank you Yao Jiewen > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Yao, Jiewen > Sent: Monday, December 17, 2018 4:25 PM > To: Ard Biesheuvel ; Leif Lindholm > > Cc: edk2-devel@lists.01.org; Zhang, Chao B ; > Gao, Liming > Subject: Re: [edk2] [PATCH 05/13] MdePkg/Library/BaseLib/AArch64: Add > AsmLfence function >=20 > Hi Ard > I am OK to refine it now. >=20 > Do you have any proposal on the naming from ARM side? >=20 > Thank you > Yao Jiewen >=20 > > -----Original Message----- > > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > > Sent: Monday, December 17, 2018 4:11 PM > > To: Yao, Jiewen ; Leif Lindholm > > > > Cc: Gao, Liming ; Jagadeesh Ujja > > ; edk2-devel@lists.01.org; Zhang, Chao B > > > > Subject: Re: [PATCH 05/13] MdePkg/Library/BaseLib/AArch64: Add > > AsmLfence function > > > > On Mon, 17 Dec 2018 at 08:45, Ard Biesheuvel > > > wrote: > > > > > > On Mon, 17 Dec 2018 at 04:29, Yao, Jiewen > > wrote: > > > > > > > > I think we have below definition. > > > > -- MemoryFence: Serialize load and store operations. > > > > -- LoadFence: Serialize load operations. > > > > -- StoreFence: Serialize store operations. > > > > > > > > According to IA32 SDM, Intel has MFENCE, LFENCE and SFENCE. > > > > If ARM only has DMB, it is possible to use DMB for MemoryFence, > > LoadFence or StoreFence. > > > > > > > > Maybe it is better to use LoadFence, instead of AsmLFence? > > > > Then we can align with MemoryFence. > > > > > > > > > > I think using AsmLfence() all over the code to limit speculation was = a > > > mistake, and I am disappointed nobody from the ARM side was involved > > > at all when these changes were proposed. > > > > > > > OK, I have to apologize here. Hao did cc us on these patches, and so > > we did have the opportunity to respond at the time. > > > > But that doesn't change the fact that AsmLfence() should be replaced > > by an abstraction that describes the specific semantics of the x86 > > Lfence implemetation beyond memory ordering that we are relying on > > here. > > > > > > > > > The code changes rely on specific semantics of the x86 Lfence > > > instructions, i.e., that beyond load serialization, they ensure that > > > all instructions (not just loads) complete before the lfence > > > completes. This is a much stronger notion than a load barrier, and so > > > the abstraction should have been defined as something like a > > > ExecFence() or pipeline barrier etc, and the x86 specific > > > implementation would have been mapped onto Lfence. For the ARM > side, > > > we probably need an ISB instruction here as well as some kind of othe= r > > > barrier. Calling it LoadFence() makes no sense whatsoever. > > > > > > > > > > > > > > > > > > > > > > > > -----Original Message----- > > > > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On > Behalf > > Of > > > > > Gao, Liming > > > > > Sent: Monday, December 17, 2018 10:04 AM > > > > > To: Ard Biesheuvel ; Jagadeesh Ujja > > > > > ; Leif Lindholm > > > > > > Cc: edk2-devel@lists.01.org; Zhang, Chao B > > > > > > > Subject: Re: [edk2] [PATCH 05/13] MdePkg/Library/BaseLib/AArch64: > > Add > > > > > AsmLfence function > > > > > > > > > > Ard: > > > > > My first comment is to suggest updating the caller code for the > arch > > > > > specific code. But, there are two drivers that have the same usa= ge. > > This > > > > > way will introduce the duplicated code logic. So, I suggest anoth= er > way > > to > > > > > extend AsmLfence() API scope for the different ARCHs. If you thi= nk > it > > brings > > > > > the confuse, I just think another way to resolve this case in the= caller > > code. > > > > > > > > > > #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) > > > > > AsmLfence(); > > > > > #else > > > > > MemoryFence() > > > > > #endif > > > > > > > > > > Thanks > > > > > Liming > > > > > >-----Original Message----- > > > > > >From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > > > > > >Sent: Friday, December 14, 2018 9:54 PM > > > > > >To: Jagadeesh Ujja ; Leif Lindholm > > > > > > > > > > > >Cc: edk2-devel@lists.01.org; Gao, Liming ; > > Zhang, > > > > > >Chao B > > > > > >Subject: Re: [PATCH 05/13] MdePkg/Library/BaseLib/AArch64: Add > > > > > >AsmLfence function > > > > > > > > > > > >On Fri, 14 Dec 2018 at 13:13, Jagadeesh Ujja > > > > > > > >wrote: > > > > > >> > > > > > >> Variable service driver includes a call to AsmLfence. To reuse= this > > > > > >> driver on AArch64 based platforms, add an implementation of > > AsmLfence > > > > > >> that acts as a wrapper on the AArch64 specific MemoryFence > > function. > > > > > >> > > > > > >> Contributed-under: TianoCore Contribution Agreement 1.1 > > > > > >> Signed-off-by: Jagadeesh Ujja > > > > > >> --- > > > > > >> MdePkg/Include/Library/BaseLib.h | 33 > > +++++++++------ > > > > > >> MdePkg/Library/BaseLib/AArch64/AsmLfence.S | 42 > > > > > >++++++++++++++++++++ > > > > > >> MdePkg/Library/BaseLib/AArch64/AsmLfence.asm | 41 > > > > > >+++++++++++++++++++ > > > > > >> MdePkg/Library/BaseLib/BaseLib.inf | 2 + > > > > > >> 4 files changed, 105 insertions(+), 13 deletions(-) > > > > > >> > > > > > >> diff --git a/MdePkg/Include/Library/BaseLib.h > > > > > >b/MdePkg/Include/Library/BaseLib.h > > > > > >> index 8cc0869..ca961ee 100644 > > > > > >> --- a/MdePkg/Include/Library/BaseLib.h > > > > > >> +++ b/MdePkg/Include/Library/BaseLib.h > > > > > >> @@ -7697,19 +7697,6 @@ AsmWriteTr ( > > > > > >> ); > > > > > >> > > > > > >> /** > > > > > >> - Performs a serializing operation on all load-from-memory > > instructions > > > > > that > > > > > >> - were issued prior the AsmLfence function. > > > > > >> - > > > > > >> - Executes a LFENCE instruction. This function is only availa= ble > on > > IA-32 > > > > > and > > > > > >x64. > > > > > >> - > > > > > >> -**/ > > > > > >> -VOID > > > > > >> -EFIAPI > > > > > >> -AsmLfence ( > > > > > >> - VOID > > > > > >> - ); > > > > > >> - > > > > > >> -/** > > > > > >> Patch the immediate operand of an IA32 or X64 instruction > such > > that > > > > > the > > > > > >byte, > > > > > >> word, dword or qword operand is encoded at the end of the > > > > > instruction's > > > > > >> binary representation. > > > > > >> @@ -7752,4 +7739,24 @@ PatchInstructionX86 ( > > > > > >> ); > > > > > >> > > > > > >> #endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) > > > > > >> + > > > > > >> +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) || > > defined > > > > > >(MDE_CPU_AARCH64) > > > > > >> + > > > > > >> +/** > > > > > >> + Performs a serializing operation on all load-from-memory > > instructions > > > > > that > > > > > >> + were issued prior the AsmLfence function. > > > > > >> + > > > > > >> + In case of IA-32 and x64, Executes a LFENCE instruction. > > > > > >> + > > > > > >> + In case of AArch64 this acts as a wrapper on the AArch64 > > > > > >> + specific MemoryFence function > > > > > >> + > > > > > >> +**/ > > > > > >> +VOID > > > > > >> +EFIAPI > > > > > >> +AsmLfence ( > > > > > >> + VOID > > > > > >> + ); > > > > > >> + > > > > > >> +#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) > > || > > > > > >defined (MDE_CPU_AARCH64) > > > > > >> #endif // !defined (__BASE_LIB__) > > > > > >> diff --git a/MdePkg/Library/BaseLib/AArch64/AsmLfence.S > > > > > >b/MdePkg/Library/BaseLib/AArch64/AsmLfence.S > > > > > >> new file mode 100644 > > > > > >> index 0000000..2fd804b > > > > > >> --- /dev/null > > > > > >> +++ b/MdePkg/Library/BaseLib/AArch64/AsmLfence.S > > > > > >> @@ -0,0 +1,42 @@ > > > > > >> > +##----------------------------------------------------------------------= -------- > > > > > >> +# > > > > > >> +# AsmLfence() for AArch64 > > > > > >> +# > > > > > >> +# Copyright (c) 2013-2018, ARM Ltd. All rights reserved. > > > > > >> +# > > > > > >> +# This program and the accompanying materials > > > > > >> +# are licensed and made available under the terms and conditi= ons > > of the > > > > > >BSD License > > > > > >> +# which accompanies this distribution. The full text of the > license > > may > > > > > be > > > > > >found at > > > > > >> +# http://opensource.org/licenses/bsd-license.php. > > > > > >> +# > > > > > >> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON > AN > > "AS > > > > > IS" > > > > > >BASIS, > > > > > >> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, > > EITHER > > > > > >EXPRESS OR IMPLIED. > > > > > >> +# > > > > > >> > +##----------------------------------------------------------------------= -------- > > > > > >> + > > > > > >> +.text > > > > > >> +.p2align 2 > > > > > >> + > > > > > >> +GCC_ASM_EXPORT(AsmLfence) > > > > > >> + > > > > > >> +# IMPORT > > > > > >> +GCC_ASM_IMPORT(MemoryFence) > > > > > >> + > > > > > >> +#/** > > > > > >> +# Used to serialize load and store operations. > > > > > >> +# > > > > > >> +# All loads and stores that proceed calls to this function a= re > > > > > guaranteed to > > > > > >be > > > > > >> +# globally visible when this function returns. > > > > > >> +# > > > > > >> +#**/ > > > > > >> +#VOID > > > > > >> +#EFIAPI > > > > > >> +#AsmLfence ( > > > > > >> +# VOID > > > > > >> +# ); > > > > > >> +# > > > > > >> +ASM_PFX(AsmLfence): > > > > > >> + stp x29, x30, [sp, #-16]! > > > > > >> + bl MemoryFence > > > > > >> + ldp x29, x30, [sp], #0x10 > > > > > >> + ret > > > > > > > > > > > >Any reason we can't simply do > > > > > > > > > > > >b MemoryFence > > > > > > > > > > > >here? > > > > > > > > > > > >Also, why I understand the rationale, I still think it would be = better > > > > > >to change callers of the [x86 specific] AsmLfence() than to intr= oduce > > > > > >an alias of MemoryFence() for architectures where Lfence is not > > > > > >defined. > > > > > > > > > > > >This is not only about tidiness, but also about potentially havi= ng > > > > > >different semantics, which we can't provide in general on ARM, b= ut > > > > > >only in particular cases [such as the code that is modified in t= his > > > > > >series] > > > > > > > > > > > >In other words, newly introduced occurrences of AsmLfence() now > > have > > > > > >to be audited for being appropriate on AArc64 if they are added = to > > > > > >generic code. > > > > > > > > > > > > > > > > > >> diff --git a/MdePkg/Library/BaseLib/AArch64/AsmLfence.asm > > > > > >b/MdePkg/Library/BaseLib/AArch64/AsmLfence.asm > > > > > >> new file mode 100644 > > > > > >> index 0000000..7dd5659 > > > > > >> --- /dev/null > > > > > >> +++ b/MdePkg/Library/BaseLib/AArch64/AsmLfence.asm > > > > > >> @@ -0,0 +1,41 @@ > > > > > >> +;------------------------------------------------------------= ------------------ > > > > > >> +; > > > > > >> +; AsmLfence() for AArch64 > > > > > >> +; > > > > > >> +; Copyright (c) 2013-2018, ARM Ltd. All rights reserved. > > > > > >> +; > > > > > >> +; This program and the accompanying materials > > > > > >> +; are licensed and made available under the terms and conditi= ons > > of the > > > > > >BSD License > > > > > >> +; which accompanies this distribution. The full text of the > license > > may > > > > > be > > > > > >found at > > > > > >> +; http://opensource.org/licenses/bsd-license.php. > > > > > >> +; > > > > > >> +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON > AN > > "AS > > > > > IS" > > > > > >BASIS, > > > > > >> +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, > > EITHER > > > > > >EXPRESS OR IMPLIED. > > > > > >> +; > > > > > >> +;------------------------------------------------------------= ------------------ > > > > > >> + > > > > > >> + EXPORT AsmLfence > > > > > >> + AREA BaseLib_LowLevel, CODE, READONLY > > > > > >> + # IMPORT > > > > > >> + GCC_ASM_IMPORT(MemoryFence) > > > > > >> + > > > > > >> +;/** > > > > > >> +; Used to serialize load and store operations. > > > > > >> +; > > > > > >> +; All loads and stores that proceed calls to this function a= re > > guaranteed > > > > > to > > > > > >be > > > > > >> +; globally visible when this function returns. > > > > > >> +; > > > > > >> +;**/ > > > > > >> +;VOID > > > > > >> +;EFIAPI > > > > > >> +;AsmLfence ( > > > > > >> +; VOID > > > > > >> +; ); > > > > > >> +; > > > > > >> +AsmLfence > > > > > >> + stp x29, x30, [sp, #-16]! > > > > > >> + bl MemoryFence > > > > > >> + ldp x29, x30, [sp], #0x10 > > > > > >> + ret > > > > > >> + > > > > > >> + END > > > > > >> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf > > > > > >b/MdePkg/Library/BaseLib/BaseLib.inf > > > > > >> index b84e583..b7d7bcb 100644 > > > > > >> --- a/MdePkg/Library/BaseLib/BaseLib.inf > > > > > >> +++ b/MdePkg/Library/BaseLib/BaseLib.inf > > > > > >> @@ -585,6 +585,7 @@ > > > > > >> Math64.c > > > > > >> > > > > > >> AArch64/MemoryFence.S | GCC > > > > > >> + AArch64/AsmLfence.S | GCC > > > > > >> AArch64/SwitchStack.S | GCC > > > > > >> AArch64/EnableInterrupts.S | GCC > > > > > >> AArch64/DisableInterrupts.S | GCC > > > > > >> @@ -593,6 +594,7 @@ > > > > > >> AArch64/CpuBreakpoint.S | GCC > > > > > >> > > > > > >> AArch64/MemoryFence.asm | MSFT > > > > > >> + AArch64/AsmLfence.asm | MSFT > > > > > >> AArch64/SwitchStack.asm | MSFT > > > > > >> AArch64/EnableInterrupts.asm | MSFT > > > > > >> AArch64/DisableInterrupts.asm | MSFT > > > > > >> -- > > > > > >> 2.7.4 > > > > > >> > > > > > _______________________________________________ > > > > > edk2-devel mailing list > > > > > edk2-devel@lists.01.org > > > > > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel