From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: jiewen.yao@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Sun, 19 May 2019 23:09:05 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 May 2019 23:09:04 -0700 X-ExtLoop1: 1 Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga003.jf.intel.com with ESMTP; 19 May 2019 23:09:04 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sun, 19 May 2019 23:09:03 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.249]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.18]) with mapi id 14.03.0415.000; Mon, 20 May 2019 14:09:01 +0800 From: "Yao, Jiewen" To: "Zeng, Star" , "Jerry Zhou(BJ-RD)" , "edk2-devel@lists.01.org" , "devel@edk2.groups.io" CC: "Ni, Ray" , "Yao, Jiewen" Subject: Re: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code Thread-Topic: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code Thread-Index: AdUJNci9WEC63Y3xT7KjRAFsJUkP5QARFuIgAAC+ShABT1l1wAACY4gg Date: Mon, 20 May 2019 06:09:01 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F65159E@shsmsx102.ccr.corp.intel.com> References: <0C09AFA07DD0434D9E2A0C6AEB048310402DECF5@shsmsx102.ccr.corp.intel.com> <9b07851c347d4810a691ebaa64d1fa5e@zhaoxin.com> <0C09AFA07DD0434D9E2A0C6AEB048310402E56C9@shsmsx102.ccr.corp.intel.com> In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB048310402E56C9@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: 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Thanks.=

We are = also reviewing the VTd disabling flow and may update recently.

&n= bsp;

If you = want to file Bugzilla, please go ahead.

&n= bsp;

Thank y= ou

Yao Jie= wen

 

From: Zeng, Sta= r
Sent: Sunday, May 19, 2019 8:33 PM
To: Jerry Zhou(BJ-RD) <JerryZhou@zhaoxin.com>; edk2-devel@list= s.01.org; devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ray <ray.ni@int= el.com>; Zeng, Star <star.zeng@intel.com>
Subject: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about= the source code

 

Actually, I agree with you.

Personally, I think more rigorous flow could be like below.<= /o:p>

1.      Clear B_GMCD_REG_TE, wait B_GSTS_REG_TE to be cleared.

2.      Set B_GMCD_REG_SRTP, wait B_GSTS_REG_RTPS to be set.=

3.      Zero R_RTADDR_REG.

 

Not sure original code developer Jiewen=A1=AFs thought about this= .

 

 

You may submit Bugzilla at https://bug= zilla.tianocore.org if you wait.

 

 

Thanks,

Star

 

From: Jerry Zhou(BJ-RD) [mailto:JerryZhou@zhaoxin.com]
Sent: Monday, May 13, 2019 7:28 PM
To: Zeng, Star <star.zeng@intel.com>; edk2-devel@lists.01.org; devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, R= ay <ray.ni@intel.com>
Subject: = =B4=F0=B8=B4: [edk2]= [PATCH] IntelSiliconPkg VTdDxe: a question about the source code

 

Got it!= Thanks for your reply.

But you= should still poll the B_GSTS_REG_TE bit, not the B_GSTS_REG_RTPS bit, in t= he judgement code of while() loop.

After &= amp; operation between Reg32 and B_GSTS_REG_RTPS, the status of B_GSTS_REG_= TE will be lost.

&n= bsp;

A more = tedious but more reliable operation sequence is recommended in Vt-d specifi= cation 2.4 below:

&n= bsp;

to update a bit field in t= his register at offset X with value of Y, software

must follow below steps:

1. Tmp =3D Read GSTS_REG

2. Status =3D (Tmp & 9= 6FFFFFFh) // Reset the one-shot bits

3. Command =3D (Status | (= Y << X))

4. Write Command to GCMD_R= EG

5. Wait until GSTS_REG[X] = indicates command is serviced.

=B7=A2=BC=FE=C8=CB: Zeng, Star [mailto:star.zeng@intel.com]
=B7=A2=CB=CD= =CA=B1=BC=E4: 2019=C4=EA5=D4=C2<= span lang=3D"EN-US">13=C8=D5 18:54
=CA=D5=BC=FE=C8=CB: Jerry Zhou(BJ-RD); edk2-devel@lists.01.= org
=B3=AD=CB=CD<= span lang=3D"EN-US">: Yao, Jiewen; Ni, Ray; Zeng, Star
=D6=F7=CC=E2<= span lang=3D"EN-US">: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: = a question about the source code

 

Good question, my understanding is setting B_GMCD_REG_SRTP(BIT30)= ONLY also means clearing B_GMCD_REG_TE (BIT31).

 

Thanks,

Star

From: Jerry Zhou(BJ-RD) [mailto:JerryZhou@zhaoxin.com]
Sent: Monday, May 13, 2019 10:59 AM
To: Zeng, Star <star.zeng@intel.com>; edk2-devel@lists.01.org
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, R= ay <ray.ni@intel.com>
Subject: = =B4=F0=B8=B4: [edk2]= [PATCH] IntelSiliconPkg VTdDxe: a question about the source code

 

Hi Star,

    &nbs= p;    I'am so interested in DMA protection in UEFI. It's a r= eally good design!

    &nbs= p;    But I have a question about the implemention of DisableDmar() in IntelSiliconPkg\feature\vtd\intelvtddxe\VtdReg.c

    &nbs= p;    Is it a typing error in the code segment below?

 

    //

    // Disabl= e VTd

    //

    MmioWrite= 32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);=

    do {=

    &nbs= p; Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress += ; R_GSTS_REG);

} while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0);

 

The software should program the B_GMCD_REG_TE field in global command register and then poll the = B_GSTS_REG_TE field in global status register if the DMAR is expected t= o be disabled or enabled according to Vt-d specification.=

 

Thanks

Jerry Zhou=

Ext:892418=

 

 

 

-----=D3=CA=BC=FE=D4=AD=BC=FE----= -
=B7=A2=BC=FE=C8=CB: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] =B4=FA=B1=ED Star Zeng
=B7=A2=CB=CD=CA=B1=BC=E4: 2018=C4=EA10=D4= =C224= =C8=D5 11:32
=CA=D5=BC=FE=C8=CB: edk2-devel@lists.01.org
=B3=AD=CB=CD: Jiewen Yao; Star Zeng
=D6=F7=CC=E2: [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force no early ac= cess attr request

 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1272=

 

To have high confidence in u= sage for platform, add option (BIT2 of

PcdVTdPolicyPropertyMask) to= force no IOMMU access attribute request

recording before DMAR table = is installed.

 

Check PcdVTdPolicyPropertyMa= sk BIT2 before RequestAccessAttribute()

and ProcessRequestedAccessAt= tribute(), then RequestAccessAttribute(),

ProcessRequestedAccessAttrib= ute() and mAccessRequestXXX variables

could be optimized by compil= er when PcdVTdPolicyPropertyMask BIT2 =3D 1.

 

Test done:=

1: Created case that has IOM= MU access attribute request before DMAR

   table is instal= led, ASSERT was triggered after setting

   PcdVTdPolicyPro= pertyMask BIT2 to 1.

 

2. Confirmed RequestAccessAt= tribute(), ProcessRequestedAccessAttribute()

   and mAccessRequ= estXXX variables were optimized by compiler after

   setting PcdVTdP= olicyPropertyMask BIT2 to 1.

 

Cc: Jiewen Yao <jiewen.yao@intel.com>

Cc: Rangasai V Chaganty <= rangasai.v.chaganty@intel.= com>

Contributed-under: TianoCore= Contribution Agreement 1.1

Signed-off-by: Star Zeng <= ;star.zeng@intel.com>

---

IntelSiliconPkg/Feature/VTd/= IntelVTdDxe/DmaProtection.c | 8 +++++++-

IntelSiliconPkg/Feature/VTd/= IntelVTdDxe/IntelVTdDxe.c   | 7 ++++++= 3;

IntelSiliconPkg/IntelSilicon= Pkg.dec           &n= bsp;         | 1 +

3 files changed, 15 insertio= ns(+), 1 deletion(-)

 

diff --git a/IntelSiliconPkg= /Feature/VTd/IntelVTdDxe/DmaProtection.c b/IntelSiliconPkg/Feature/VTd/Inte= lVTdDxe/DmaProtection.c

index 86d50eb6f288..77845456= 31b3 100644

--- a/IntelSiliconPkg/Featur= e/VTd/IntelVTdDxe/DmaProtection.c

+++ b/IntelSilic= onPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c

@@ -515,7 +515,13 @@ Set= upVtd (

 

   ParseDmarA= cpiTableRmrr ();

 

-  ProcessRequestedAcce= ssAttribute ();

+  if ((PcdGet8 (Pc= dVTdPolicyPropertyMask) & BIT2) =3D=3D 0) {

+    //

+    // S= upport IOMMU access attribute request recording before DMAR table is instal= led.

+    // H= ere is to process the requests.

+    //

+    Proc= essRequestedAccessAttribute ();

+  }

 

   for (Index= =3D 0; Index < mVtdUnitNumber; Index++) {

     DEB= UG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index, mVtdUnitI= nformation[Index].Segment));

diff --git a/IntelSiliconPkg= /Feature/VTd/IntelVTdDxe/IntelVTdDxe.c b/IntelSiliconPkg/Feature/VTd/IntelV= TdDxe/IntelVTdDxe.c

index 25d7c80af1d4..09948ce5= 0e94 100644

--- a/IntelSiliconPkg/Featur= e/VTd/IntelVTdDxe/IntelVTdDxe.c

+++ b/IntelSilic= onPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c

@@ -254,6 +254,13 @@ VTd= SetAttribute (

     // = Record the entry to driver global variable.

     // = As such once VTd is activated, the setting can be adopted.

     //<= o:p>

+    if (= (PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) !=3D 0) {=

+    = ;  //

+    = ;  // Force no IOMMU access attribute request recording before DMAR ta= ble is installed.

+    = ;  //

+    = ;  ASSERT_EFI_ERROR (EFI_NOT_READY);

+    = ;  return EFI_NOT_READY;

+    }

     Sta= tus =3D RequestAccessAttribute (Segment, SourceId, DeviceAddress, Length, I= oMmuAccess);

   } else {

     PER= F_CODE (

diff --git a/IntelSiliconPkg= /IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSiliconPkg.dec

index b9646d773b95..900e8f63= c64d 100644

--- a/IntelSiliconPkg/IntelS= iliconPkg.dec

+++ b/IntelSilic= onPkg/IntelSiliconPkg.dec

@@ -64,6 +64,7 @@ [PcdsF= ixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]<= /span>

   ## The mask is = used to control VTd behavior.<BR><BR>

   #  BIT0: E= nable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PPI= is installed in PEI.)

   #  BIT1: E= nable IOMMU when transfer control to OS (ExitBootService in normal boot. En= dOfPEI in S3)

+  #  BIT2: Fo= rce no IOMMU access attribute request recording before DMAR table is instal= led.

   # @Prompt The p= olicy for VTd driver behavior.

   gIntelSiliconPk= gTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x00000002

 

--

2.7.0.windows.1

 

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--_000_74D8A39837DF1E4DA445A8C0B3885C503F65159Eshsmsx102ccrcor_--