From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: jiewen.yao@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Thu, 08 Aug 2019 06:41:21 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 06:41:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,361,1559545200"; d="scan'208";a="186353095" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga002.jf.intel.com with ESMTP; 08 Aug 2019 06:41:20 -0700 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 8 Aug 2019 06:41:20 -0700 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 8 Aug 2019 06:41:19 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.19]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.15]) with mapi id 14.03.0439.000; Thu, 8 Aug 2019 21:41:17 +0800 From: "Yao, Jiewen" To: "Wang, Iwen Evelyn" , "devel@edk2.groups.io" CC: "Huang, Jenny" Subject: Re: [PATCH] Extened PMR feature: allow silicon code to adjust PLMR/PHMR region base on the project needs Thread-Topic: [PATCH] Extened PMR feature: allow silicon code to adjust PLMR/PHMR region base on the project needs Thread-Index: AQHVTYBYv9UDB+nxJEC5g9OMn/+fxKbxQZkw Date: Thu, 8 Aug 2019 13:41:17 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F749D38@shsmsx102.ccr.corp.intel.com> References: <20190808002911.4972-1-iwen.evelyn.wang@intel.com> In-Reply-To: <20190808002911.4972-1-iwen.evelyn.wang@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjEyZDE1ZWEtMjgwOS00M2ZmLWIyY2UtZGUzNWM2MjBmY2JiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiY01uY1wvZDF5NVRkRk5leXRUZFloMjUzTlVxWTg0djhDSk9tc2VSK09LRit6ekFDNlNhTE1wWW1FM0FDSFBtNmcifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: jiewen.yao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Evelyn Thanks for the enhancement. However, I fail to apply the patch to the latest tree. Please be aware that: 1) We updated the license header. 2) We moved the IntelSiliconPkg from edkii repo to edkii-platform repo. Would you please pull the latest tree and apply the patch, then send it aga= in? Some format issue: 1) "Cd: more.shih@intel.com" should be "Cc: more.shih@intel.com", right? 2) Please also add the full name such as: Cc: Jiewen Yao 3) Please remove "Change-Id: Ia80394183522f7a4a921a75a1fa6e3779053d4eb" 4) Please add "PackageName/ModuleName:" in the title. Thank you Yao Jiewen > -----Original Message----- > From: Wang, Iwen Evelyn > Sent: Thursday, August 8, 2019 8:29 AM > To: devel@edk2.groups.io > Cc: Huang, Jenny ; Yao, Jiewen > > Subject: [PATCH] Extened PMR feature: allow silicon code to adjust > PLMR/PHMR region base on the project needs >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1770 >=20 > 1) IOMMU PMR feature should be generic to support different hardware > architecture. > Some platforms may request no overlap between PMR regions and system > reserve memory regions. Create an interface to control PLMR/PHMR > regions. >=20 > 2) DisableDMAr Function Code Optimization > Currently, DisableDMAr flow functional-wise has no issues. However, it wi= ll > be great if we can optimize the flow to follow the VT-d spec requirements= . >=20 > 3) Renamed InitDmar() to InitGlobalVtd() > The oringal function name is misleading >=20 > Change-Id: Ia80394183522f7a4a921a75a1fa6e3779053d4eb > Cc: jenny.huang@intel.com > Cc: jiewen.yao@intel.com > Cd: more.shih@intel.com > Signed-off-by: Evelyn Wang > --- > IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > | 28 ++++++++++++++++++++++++++-- > IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c > | 76 > ++++++++++++++++++++++++++++++++++++++++++++++++++------------------ > -------- > IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > | 5 ++++- > IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > | 27 +++++++++++++++++++++++++-- > IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h > | 31 +++++++++++++++++++++++++++++++ > IntelSiliconPkg/Include/SysMemInfoHob.h > | 28 ++++++++++++++++++++++++++++ > IntelSiliconPkg/IntelSiliconPkg.dec > | 4 +++- > IntelSiliconPkg/IntelSiliconPkg.dsc > | 3 ++- > IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c > | 170 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++ > IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf > | 38 ++++++++++++++++++++++++++++++++++++++ > 10 files changed, 377 insertions(+), 33 deletions(-) >=20 > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > index 8dbc83fa2d..6a66a860b4 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the > BSD License > which accompanies this distribution. The full text of the license may= be > found at > @@ -315,6 +315,8 @@ DisableDmar ( > UINTN Index; > UINTN SubIndex; > UINT32 Reg32; > + UINT32 Status; > + UINT32 Command; >=20 > for (Index =3D 0; Index < mVtdUnitNumber; Index++) { > DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", > Index)); > @@ -327,7 +329,29 @@ DisableDmar ( > // > // Disable VTd > // > - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + > R_GCMD_REG, B_GMCD_REG_SRTP); > + // > + // Set TE (Translation Enable: BIT31) of Global command register to > zero > + // > + Reg32 =3D MmioRead32 > (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status & ~B_GMCD_REG_TE); > + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + > R_GCMD_REG, Command); > + > + // > + // Poll on TE Status bit of Global status register to become zero > + // > + do { > + Reg32 =3D MmioRead32 > (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG); > + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); > + > + // > + // Set SRTP (Set Root Table Pointer: BIT30) of Global command > register in order to update the root table pointerDisable VTd > + // > + Reg32 =3D MmioRead32 > (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status | B_GMCD_REG_SRTP); > + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + > R_GCMD_REG, Command); > + > do { > Reg32 =3D MmioRead32 > (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG); > } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c > b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c > index 27847f4331..c8a2cae5ff 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > This program and the accompanying materials are licensed and made > available under > the terms and conditions of the BSD License which accompanies this > distribution. > @@ -26,7 +26,7 @@ > #include > #include > #include > - > +#include > #include "IntelVTdPmrPei.h" >=20 > EFI_GUID mVTdInfoGuid =3D { > @@ -430,38 +430,65 @@ InitDmaProtection ( > UINTN MemoryAlignment; > UINTN LowBottom; > UINTN LowTop; > - UINTN HighBottom; > + UINT64 HighBottom; > UINT64 HighTop; > DMA_BUFFER_INFO *DmaBufferInfo; > VOID *Hob; > EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; > EDKII_IOMMU_PPI *OldIoMmuPpi; > + SYSTEM_MEM_INFO_HOB *SysMemHob; > + VOID *SysMemHobPtr; >=20 > Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); > DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); > - > - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", > DmaBufferInfo->DmaBufferSize)); > - > - LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, > VTdInfo->EngineMask); > - HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, > VTdInfo->EngineMask); > - if (LowMemoryAlignment < HighMemoryAlignment) { > - MemoryAlignment =3D (UINTN)HighMemoryAlignment; > + > + SysMemHobPtr =3D GetFirstGuidHob (&gSysMemInfoDataHobGuid); > + > + if (SysMemHobPtr =3D=3D NULL) { > + // > + // Calcuate the PMR memory alignment > + // > + LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, > VTdInfo->EngineMask); > + HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, > VTdInfo->EngineMask); > + if (LowMemoryAlignment < HighMemoryAlignment) { > + MemoryAlignment =3D (UINTN)HighMemoryAlignment; > + } else { > + MemoryAlignment =3D LowMemoryAlignment; > + } > + ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D > ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment)); > + > + // > + // Allocate memory for DMA buffer > + // > + DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages > (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); > + ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); > + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { > + DEBUG ((DEBUG_INFO, " InitDmaProtection : > OutOfResource\n")); > + return EFI_OUT_OF_RESOURCES; > + } > + > + DmaBufferInfo->DmaBufferCurrentTop =3D > DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize; > + DmaBufferInfo->DmaBufferCurrentBottom =3D > DmaBufferInfo->DmaBufferBase; > + LowBottom =3D 0; > + LowTop =3D DmaBufferInfo->DmaBufferBase; > + HighBottom =3D DmaBufferInfo->DmaBufferBase + > DmaBufferInfo->DmaBufferSize; > + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); > } else { > - MemoryAlignment =3D LowMemoryAlignment; > - } > - ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D > ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment)); > - DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages > (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); > - ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); > - if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { > - DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); > - return EFI_OUT_OF_RESOURCES; > - } >=20 > + // > + // Get the PMR ranges information for the hob > + // > + SysMemHob =3D GET_GUID_HOB_DATA (SysMemHobPtr); > + DmaBufferInfo->DmaBufferBase =3D SysMemHob->ProtectedLowLimit > << 20; > + LowBottom =3D SysMemHob->ProtectedLowBase; > + LowTop =3D SysMemHob->ProtectedLowLimit << 20; > + HighBottom =3D (UINT64) BASE_4GB; > + HighTop =3D (UINT64) SysMemHob->ProtectedHighLimit << 20; > + } > + > + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", > DmaBufferInfo->DmaBufferSize)); > DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", > DmaBufferInfo->DmaBufferBase)); >=20 > - DmaBufferInfo->DmaBufferCurrentTop =3D > DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize; > - DmaBufferInfo->DmaBufferCurrentBottom =3D > DmaBufferInfo->DmaBufferBase; > - > // > // (Re)Install PPI. > // > @@ -478,10 +505,7 @@ InitDmaProtection ( > } > ASSERT_EFI_ERROR (Status); >=20 > - LowBottom =3D 0; > - LowTop =3D DmaBufferInfo->DmaBufferBase; > - HighBottom =3D DmaBufferInfo->DmaBufferBase + > DmaBufferInfo->DmaBufferSize; > - HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); > + >=20 > Status =3D SetDmaProtectedRange ( > VTdInfo, > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.in= f > b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > index 5b688d5cbf..427c9a830c 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > @@ -4,7 +4,7 @@ > # This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI > # and provide DMA protection in PEI. > # > -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> # This program and the accompanying materials > # are licensed and made available under the terms and conditions of the > BSD License > # which accompanies this distribution. The full text of the license may= be > found at > @@ -46,6 +46,9 @@ > IoLib > CacheMaintenanceLib >=20 > +[Guids] > + gSysMemInfoDataHobGuid ## CONSUMES > + > [Ppis] > gEdkiiIoMmuPpiGuid ## PRODUCES > gEdkiiVTdInfoPpiGuid ## CONSUMES > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > index 888905d40d..b6a3614e75 100644 > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > This program and the accompanying materials are licensed and made > available under > the terms and conditions of the BSD License which accompanies this > distribution. > @@ -203,6 +203,8 @@ DisableDmar ( > ) > { > UINT32 Reg32; > + UINT32 Status; > + UINT32 Command; >=20 > DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", > VtdUnitBaseAddress)); >=20 > @@ -214,7 +216,28 @@ DisableDmar ( > // > // Disable VTd > // > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, > B_GMCD_REG_SRTP); > + // > + // Set TE (Translation Enable: BIT31) of Global command register to ze= ro > + // > + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status & ~B_GMCD_REG_TE); > + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); > + > + // > + // Poll on TE Status bit of Global status register to become zero > + // > + do { > + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); > + > + // > + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register > in order to update the root table pointerDisable VTd > + // > + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status | B_GMCD_REG_SRTP); > + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); > do { > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); > diff --git a/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h > b/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h > new file mode 100644 > index 0000000000..537d013783 > --- /dev/null > +++ b/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h > @@ -0,0 +1,31 @@ > +/** @file > + Get Global VTd PMR alignment information library. > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the > BSD License > + which accompanies this distribution. The full text of the license may= be > found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > + > +**/ > + > + > +#ifndef __GET_VTD_PMR_ALIGN_LIB_H__ > +#define __GET_VTD_PMR_ALIGN_LIB_H__ > +#include > + > +/** > + Get Global VT-d Protected Memory alignment. > + > + > + @return protected high memory alignment. > +**/ > + > +UINTN > +GetGlobalVtdPmrAlignment ( > +); > + > +#endif // __GET_VTD_PMR_ALIGN_LIB_H__ > diff --git a/IntelSiliconPkg/Include/SysMemInfoHob.h > b/IntelSiliconPkg/Include/SysMemInfoHob.h > new file mode 100644 > index 0000000000..d3045b2c7a > --- /dev/null > +++ b/IntelSiliconPkg/Include/SysMemInfoHob.h > @@ -0,0 +1,28 @@ > +/** @file > + The definition for VTD System information Hob. > + > + This is a lightweight VTd information report in PEI phase. > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the > BSD License > + which accompanies this distribution. The full text of the license may= be > found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef _SYS_MEM_INFO_HOB_H_ > +#define _SYS_MEM_INFO_HOB_H_ > + > +typedef struct { > + UINTN ProtectedLowBase; > + UINTN ProtectedLowLimit; > + UINTN ProtectedHighBase; > + UINTN ProtectedHighLimit; > +} SYSTEM_MEM_INFO_HOB; > + > +#endif // _SYS_MEM_INFO_HOB_H_ > + > diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec > b/IntelSiliconPkg/IntelSiliconPkg.dec > index c0cf58fa6c..d2efac71c0 100644 > --- a/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -3,7 +3,7 @@ > # > # This package provides common open source Intel silicon modules. > # > -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> # This program and the accompanying materials are licensed and made > available under > # the terms and conditions of the BSD License that accompanies this > distribution. > # The full text of the license may be found at > @@ -27,6 +27,7 @@ > ## @libraryclass Provides services to access Microcode region on flas= h > device. > # > MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h > + GetVtdPmrAlignmentLib|Include/Library/GetVtdPmrAlignmentLib.h >=20 > [Guids] > ## GUID for Package token space > @@ -40,6 +41,7 @@ >=20 > ## Include/Guid/MicrocodeFmp.h > gMicrocodeFmpImageTypeIdGuid =3D { 0x96d4fdcd, 0x1502, 0x424d, > { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } > + gSysMemInfoDataHobGuid =3D {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, > 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } } >=20 > [Ppis] > gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0= x67, > 0xaf, 0x2b, 0x25, 0x68, 0x4a } } > diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc > b/IntelSiliconPkg/IntelSiliconPkg.dsc > index 790870e2f1..99061e3715 100644 > --- a/IntelSiliconPkg/IntelSiliconPkg.dsc > +++ b/IntelSiliconPkg/IntelSiliconPkg.dsc > @@ -1,7 +1,7 @@ > ## @file > # This package provides common open source Intel silicon modules. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> # > # This program and the accompanying materials > # are licensed and made available under the terms and conditions of > the BSD License > @@ -40,6 +40,7 @@ >=20 > SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.= in > f >=20 > CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac > heMaintenanceLib.inf >=20 > MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/Microcod > eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf > + > GetVtdPmrAlignmentLib|IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/Get > VtdPmrAlignmentLib.inf >=20 > [LibraryClasses.common.PEIM] > PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf > diff --git > a/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c > b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c > new file mode 100644 > index 0000000000..28fb8d4978 > --- /dev/null > +++ > b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c > @@ -0,0 +1,170 @@ > +/** @file > + Library to get Global VTd PMR alignment information. > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + > + This program and the accompanying materials are licensed and made > available under > + the terms and conditions of the BSD License which accompanies this > distribution. > + The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > + > +**/ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +typedef union { > + struct { > + UINT32 Low; > + UINT32 High; > + } Data32; > + UINT64 Data; > +} UINT64_STRUCT; > + > +/** > + Get protected low memory alignment. > + > + @param HostAddressWidth The host address width. > + @param VtdUnitBaseAddress The base address of the VTd engine. > + > + @return protected low memory alignment. > +**/ > +UINT32 > +GetGlobalVTdPlmrAlignment ( > + IN UINT8 HostAddressWidth, > + IN UINTN VtdUnitBaseAddress > + ) > +{ > + UINT32 Data32; > + > + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, > 0xFFFFFFFF); > + Data32 =3D MmioRead32 (VtdUnitBaseAddress + > R_PMEN_LOW_BASE_REG); > + Data32 =3D ~Data32 + 1; > + > + return Data32; > +} > + > +/** > + Get protected high memory alignment. > + > + @param HostAddressWidth The host address width. > + @param VtdUnitBaseAddress The base address of the VTd engine. > + > + @return protected high memory alignment. > +**/ > +UINT64_STRUCT > +GetGlobalVTdPhmrAlignment ( > + IN UINT8 HostAddressWidth, > + IN UINTN VtdUnitBaseAddress > + ) > +{ > + UINT64_STRUCT Data64; > + > + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, > 0xFFFFFFFFFFFFFFFF); > + Data64.Data =3D MmioRead64 (VtdUnitBaseAddress + > R_PMEN_HIGH_BASE_REG); > + Data64.Data =3D ~Data64.Data + 1; > + Data64.Data =3D Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1); > + > + return Data64; > +} > + > +/** > + Get Global VT-d Protected Memory Aignment. > + > + @return protected high memory alignment. > +**/ > +UINTN > +GetGlobalVtdPmrAlignment ( > +) > +{ > + UINT32 LowMemoryAlignment; > + UINT64_STRUCT HighMemoryAlignment; > + UINTN MemoryAlignment; > + UINT32 GlobalVTdBaseAddress; > + EFI_STATUS Status; > + UINTN VtdIndex; > + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; > + EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader; > + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; > + > + // > + // Initialization > + // > + GlobalVTdBaseAddress =3D 0xFFFFFFFF; > + LowMemoryAlignment =3D 0; > + HighMemoryAlignment.Data =3D 0; > + MemoryAlignment =3D 0; > + Status =3D EFI_UNSUPPORTED; > + VtdIndex =3D 0; > + DmarHeader =3D NULL; > + DrhdHeader =3D NULL; > + AcpiDmarTable =3D NULL; > + > + // > + // Fatch the PEI DMAR ACPU Table that created and installed in > PlatformVTdInfoSamplePei.c > + // > + Status =3D PeiServicesLocatePpi ( > + &gEdkiiVTdInfoPpiGuid, > + 0, > + NULL, > + (VOID **)&AcpiDmarTable > + ); > + if (EFI_ERROR (Status)) { > + > + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid > failed\n")); > + Status =3D EFI_NOT_FOUND; > + MemoryAlignment =3D SIZE_1MB; > + > + } else { > + > + // > + // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global > VT-d > + // > + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER > *)((UINTN)(AcpiDmarTable + 1)); > + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + > AcpiDmarTable->Header.Length) { > + switch (DmarHeader->Type) { > + case EFI_ACPI_DMAR_TYPE_DRHD: > + DrhdHeader =3D (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader; > + if ((DrhdHeader->Flags & BIT0) =3D=3D BIT0) { > + GlobalVTdBaseAddress =3D > (UINT32)DrhdHeader->RegisterBaseAddress; > + DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n", > GlobalVTdBaseAddress)); > + } > + VtdIndex++; > + > + break; > + > + default: > + break; > + } > + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER > *)((UINTN)DmarHeader + DmarHeader->Length); > + } > + > + if (GlobalVTdBaseAddress =3D=3D 0xFFFFFFFF) { > + > + DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag > to your Global VT-d\n")); > + MemoryAlignment =3D SIZE_1MB; > + > + } else { > + // > + // Get the alignment information from VT-d register > + // > + LowMemoryAlignment =3D GetGlobalVTdPlmrAlignment > (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress); > + HighMemoryAlignment =3D GetGlobalVTdPhmrAlignment > (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress); > + if (LowMemoryAlignment < HighMemoryAlignment.Data) { > + MemoryAlignment =3D (UINTN)HighMemoryAlignment.Data; > + } else { > + MemoryAlignment =3D LowMemoryAlignment; > + } > + } > + } > + > + return MemoryAlignment; > +} > \ No newline at end of file > diff --git > a/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.in > f > b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.in > f > new file mode 100644 > index 0000000000..2ef199c92e > --- /dev/null > +++ > b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.in > f > @@ -0,0 +1,38 @@ > +## @file > +# Component INF file for the GetVtdPmrAlignment library. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# This program and the accompanying materials are licensed and made > available under > +# the terms and conditions of the BSD License which accompanies this > distribution. > +# The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > +# > +## > + > +[Defines] > +INF_VERSION =3D 0x00010017 > +BASE_NAME =3D GetVtdPmrAlignmentLib > +FILE_GUID =3D 0332BE93-0547-4D87-A7FA-0D9D76C53187 > +MODULE_TYPE =3D BASE > +LIBRARY_CLASS =3D GetVtdPmrAlignmentLib > + > +[Packages] > +MdePkg/MdePkg.dec > +IntelSiliconPkg/IntelSiliconPkg.dec > + > +[Sources] > +GetVtdPmrAlignmentLib.c > + > +[LibraryClasses] > +DebugLib > +BaseMemoryLib > +MemoryAllocationLib > +BaseLib > +PeiServicesLib > + > +[Ppis] > +gEdkiiVTdInfoPpiGuid > -- > 2.16.2.windows.1