From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.5407.1573022921096632024 for ; Tue, 05 Nov 2019 22:48:41 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: jiewen.yao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Nov 2019 22:48:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,272,1569308400"; d="scan'208";a="212703386" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 05 Nov 2019 22:48:40 -0800 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 5 Nov 2019 22:48:40 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX153.amr.corp.intel.com (10.18.125.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 5 Nov 2019 22:48:40 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.108]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.127]) with mapi id 14.03.0439.000; Wed, 6 Nov 2019 14:48:38 +0800 From: "Yao, Jiewen" To: "devel@edk2.groups.io" , "Yao, Jiewen" CC: "Ni, Ray" , "Chaganty, Rangasai V" , "Lou, Yun" Subject: Re: [edk2-devel] [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Topic: [edk2-devel] [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Index: AQHVj+cuUYGT4qt6hUavbmYf4FKzBKd9vJpg Date: Wed, 6 Nov 2019 06:48:37 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F83EAA4@shsmsx102.ccr.corp.intel.com> References: <20191031123127.10900-1-jiewen.yao@intel.com> <15D2BB3E0A913641.22120@groups.io> In-Reply-To: <15D2BB3E0A913641.22120@groups.io> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTIwODk5YjMtYTU1Mi00NWRkLWJlMWItZjZiZmMyM2Y2ZjA3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRXgyZFwvcGI1WXZubStLTm1FcDFGd1lyRnVZenMrNExWNTRMZ3M5YlN5SG9MbWhHVHQzcmVmcGlYeFk4MjBCaXoifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: jiewen.yao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Ray/Sai Would you please review this patch? We need this feature in next stable tag as planned. Thank you Yao Jiewen > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Yao, Jiew= en > Sent: Thursday, October 31, 2019 8:31 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V > ; Lou, Yun > Subject: [edk2-devel] [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel > PciSecurity definition. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2303 >=20 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Yun Lou > Signed-off-by: Jiewen Yao > --- > Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h | 66 > ++++++++++++++++++++ > 1 file changed, 66 insertions(+) >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurit= y.h > b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurit= y.h > new file mode 100644 > index 0000000000..a8c5483165 > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSec= urity.h > @@ -0,0 +1,66 @@ > +/** @file > + Intel PCI security data structure > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef __INTEL_PCI_SECURITY_H__ > +#define __INTEL_PCI_SECURITY_H__ > + > +#pragma pack(1) > + > +typedef struct { > + UINT16 CapId; // 0x23: DVSEC > + UINT16 CapVersion:4; // 1 > + UINT16 NextOffset:12; > + UINT16 DvSecVendorId; // 0x8086 > + UINT16 DvSecRevision:4; // 1 > + UINT16 DvSecLength:12; > + UINT16 DvSecId; // 0x3E: Measure > +} INTEL_PCI_DIGEST_CAPABILITY_HEADER; > + > +#define INTEL_PCI_CAPID_DVSEC 0x23 > +#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086 > +#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E > + > +typedef union { > + struct { > + UINT8 DigestModified:1; // RW1C > + UINT8 Reserved0:7; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_MODIFIED; > + > +#define INTEL_PCI_DIGEST_MODIFIED BIT0 > + > +typedef union { > + struct { > + UINT8 Digest0Valid:1; // RO > + UINT8 Digest0Locked:1; // RO > + UINT8 Digest1Valid:1; // RO > + UINT8 Digest1Locked:1; // RO > + UINT8 Reserved1:4; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_VALID; > + > +#define INTEL_PCI_DIGEST_0_VALID BIT0 > +#define INTEL_PCI_DIGEST_0_LOCKED BIT1 > +#define INTEL_PCI_DIGEST_1_VALID BIT2 > +#define INTEL_PCI_DIGEST_1_LOCKED BIT3 > + > +typedef struct { > + INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C > + INTEL_PCI_DIGEST_DATA_VALID Valid; // RO > + UINT16 TcgAlgId; // RO > + UINT8 FirmwareID; // RO > + UINT8 Reserved; > +//UINT8 Digest[]; > +} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE; > + > +#pragma pack() > + > +#endif > + > -- > 2.19.2.windows.1 >=20 >=20 >=20