From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web09.2866.1573096968973910728 for ; Wed, 06 Nov 2019 19:22:49 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: jiewen.yao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2019 19:22:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,276,1569308400"; d="scan'208";a="377282430" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga005.jf.intel.com with ESMTP; 06 Nov 2019 19:22:48 -0800 Received: from fmsmsx125.amr.corp.intel.com (10.18.125.40) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 6 Nov 2019 19:22:47 -0800 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 6 Nov 2019 19:22:47 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.108]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.200]) with mapi id 14.03.0439.000; Thu, 7 Nov 2019 11:22:44 +0800 From: "Yao, Jiewen" To: "Chaganty, Rangasai V" , "devel@edk2.groups.io" CC: "Ni, Ray" , "Lou, Yun" Subject: Re: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Topic: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Index: AQHVj+cpS3zlf7NEKU+zkxkm4yjEwqd+l7LwgAB62wA= Date: Thu, 7 Nov 2019 03:22:43 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F8416B8@shsmsx102.ccr.corp.intel.com> References: <20191031123127.10900-1-jiewen.yao@intel.com> <20191031123127.10900-2-jiewen.yao@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjgwNzgwNmMtMTIwNC00ZDM5LWEwODEtNzdiMmJhODZmYTg4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWU1OdkpRUXJ5NkFRRnRpT3R4dGlRZnNUV0ZGUEVsdVZJRTJcL0dlWXpPUW9jS2ZPb2FwbGluUjIzMTFtT2NXcG8ifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: jiewen.yao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks. Comments below: > -----Original Message----- > From: Chaganty, Rangasai V > Sent: Thursday, November 7, 2019 4:00 AM > To: Yao, Jiewen ; devel@edk2.groups.io > Cc: Ni, Ray ; Lou, Yun > Subject: RE: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurit= y > definition. >=20 > Hi Jiewen, > Few comments: > 1. Can we put a reference to the spec at the file header? [Jiewen] Agree. Will add in V3. > 2. Can we group all the macros at the top followed by structure definitio= ns? [Jiewen] I believe we had better to keep macro close to the data structure = definition. Take UefiSpec.h as example. EFI_MEMORY_xxx is close to EFI_MEMORY_DESCRIPTOR EVT_xxx is close to EFI_EVENT_NOTIFY TPL_xxx is close to EFI_RAISE_TPL Same example in Acpi.h We put definition close to the structure, instead of put all definition tog= ether on the top. > 3. Is it possible to add some high level description above the structure = definition > that describes the structure? [Jiewen] Agree. Will add in V3. > 4. I see line 80 is commented out. Can we remove that line? [Jiewen] This is a typical way to define a variable length field. You may find similar examples in EDKII. Just search []; C:\home\edkii\edk2\MdePkg\Include\Guid\CapsuleReport.h(84): /// CHAR16 C= apsuleFileName[]; C:\home\edkii\edk2\MdePkg\Include\Guid\CapsuleReport.h(92): /// CHAR16 C= apsuleTarget[]; C:\home\edkii\edk2\MdePkg\Include\Guid\FmpCapsule.h(46): // UINT64 ItemO= ffsetList[]; C:\home\edkii\edk2\MdePkg\Include\Guid\ImageAuthentication.h(300): /// C= HAR16 Name[]; C:\home\edkii\edk2\MdePkg\Include\Guid\StatusCodeDataTypeId.h(230): // = UINT8 ReqRes[]; C:\home\edkii\edk2\MdePkg\Include\Guid\StatusCodeDataTypeId.h(235): // = UINT8 AllocRes[]; C:\home\edkii\edk2\MdePkg\Include\Guid\SystemResourceTable.h(114): //EFI= _SYSTEM_RESOURCE_ENTRY Entries[]; C:\home\edkii\edk2\MdePkg\Include\Guid\WinCertificate.h(116): /// UINT8 = Signature[]; > 5. Please add some description about the change after line 5. [Jiewen] Line 5 ? It is about license. Would you please clarify what description is required there? >=20 > Thanks, > Sai >=20 > -----Original Message----- > From: Yao, Jiewen > Sent: Thursday, October 31, 2019 5:31 AM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V > ; Lou, Yun > Subject: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity de= finition. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2303 >=20 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Yun Lou > Signed-off-by: Jiewen Yao > --- > Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.= h | 66 > ++++++++++++++++++++ > 1 file changed, 66 insertions(+) >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h > b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h > new file mode 100644 > index 0000000000..a8c5483165 > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecu= rity.h > @@ -0,0 +1,66 @@ > +/** @file > + Intel PCI security data structure > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef __INTEL_PCI_SECURITY_H__ > +#define __INTEL_PCI_SECURITY_H__ > + > +#pragma pack(1) > + > +typedef struct { > + UINT16 CapId; // 0x23: DVSEC > + UINT16 CapVersion:4; // 1 > + UINT16 NextOffset:12; > + UINT16 DvSecVendorId; // 0x8086 > + UINT16 DvSecRevision:4; // 1 > + UINT16 DvSecLength:12; > + UINT16 DvSecId; // 0x3E: Measure > +} INTEL_PCI_DIGEST_CAPABILITY_HEADER; > + > +#define INTEL_PCI_CAPID_DVSEC 0x23 > +#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086 > +#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E > + > +typedef union { > + struct { > + UINT8 DigestModified:1; // RW1C > + UINT8 Reserved0:7; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_MODIFIED; > + > +#define INTEL_PCI_DIGEST_MODIFIED BIT0 > + > +typedef union { > + struct { > + UINT8 Digest0Valid:1; // RO > + UINT8 Digest0Locked:1; // RO > + UINT8 Digest1Valid:1; // RO > + UINT8 Digest1Locked:1; // RO > + UINT8 Reserved1:4; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_VALID; > + > +#define INTEL_PCI_DIGEST_0_VALID BIT0 > +#define INTEL_PCI_DIGEST_0_LOCKED BIT1 > +#define INTEL_PCI_DIGEST_1_VALID BIT2 > +#define INTEL_PCI_DIGEST_1_LOCKED BIT3 > + > +typedef struct { > + INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C > + INTEL_PCI_DIGEST_DATA_VALID Valid; // RO > + UINT16 TcgAlgId; // RO > + UINT8 FirmwareID; // RO > + UINT8 Reserved; > +//UINT8 Digest[]; > +} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE; > + > +#pragma pack() > + > +#endif > + > -- > 2.19.2.windows.1