From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.1075.1573110815449559227 for ; Wed, 06 Nov 2019 23:13:35 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: jiewen.yao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2019 23:13:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,277,1569308400"; d="scan'208";a="200958589" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga008.fm.intel.com with ESMTP; 06 Nov 2019 23:13:35 -0800 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 6 Nov 2019 23:13:34 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.108]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.200]) with mapi id 14.03.0439.000; Thu, 7 Nov 2019 15:13:32 +0800 From: "Yao, Jiewen" To: "Ni, Ray" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Lou, Yun" Subject: Re: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Topic: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Index: AQHVj+cqS3zlf7NEKU+zkxkm4yjEwqd/LCrAgAApqyA= Date: Thu, 7 Nov 2019 07:13:32 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F841FE2@shsmsx102.ccr.corp.intel.com> References: <20191031123127.10900-1-jiewen.yao@intel.com> <20191031123127.10900-2-jiewen.yao@intel.com> <734D49CCEBEEF84792F5B80ED585239D5C352D67@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C352D67@SHSMSX104.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTc4N2Q2NjMtMWFiOS00MWM2LWI2NzctODIwOTEyZDFlNmExIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieCtUWlJHeHZZR29xWUdGdStpU1BiSmxYMUY2VHRkWlgyd3AzNGN3NWxxUWJ5SjBiRGFaemVYbjg3XC9kdU42aDMifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: jiewen.yao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Yes, I will add the reference spec in the header in V3. > -----Original Message----- > From: Ni, Ray > Sent: Thursday, November 7, 2019 12:47 PM > To: Yao, Jiewen ; devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Lou, Yun > > Subject: RE: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurit= y > definition. >=20 > Jiewen, > You could use "UINT8 Digest[0];" in structure > INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE. >=20 > Same comments as what Sai raised, better to have the referenced spec in t= he > file header. >=20 > Thanks, > Ray >=20 > > -----Original Message----- > > From: Yao, Jiewen > > Sent: Thursday, October 31, 2019 8:31 PM > > To: devel@edk2.groups.io > > Cc: Ni, Ray ; Chaganty, Rangasai V > > ; Lou, Yun > > Subject: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity > > definition. > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2303 > > > > Cc: Ray Ni > > Cc: Rangasai V Chaganty > > Cc: Yun Lou > > Signed-off-by: Jiewen Yao > > --- > > Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurit= y.h | > > 66 ++++++++++++++++++++ > > 1 file changed, 66 insertions(+) > > > > diff --git > > a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecuri= ty.h > > b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecuri= ty.h > > new file mode 100644 > > index 0000000000..a8c5483165 > > --- /dev/null > > +++ > > b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecuri= ty.h > > @@ -0,0 +1,66 @@ > > +/** @file > > + Intel PCI security data structure > > + > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > +SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef __INTEL_PCI_SECURITY_H__ > > +#define __INTEL_PCI_SECURITY_H__ > > + > > +#pragma pack(1) > > + > > +typedef struct { > > + UINT16 CapId; // 0x23: DVSEC > > + UINT16 CapVersion:4; // 1 > > + UINT16 NextOffset:12; > > + UINT16 DvSecVendorId; // 0x8086 > > + UINT16 DvSecRevision:4; // 1 > > + UINT16 DvSecLength:12; > > + UINT16 DvSecId; // 0x3E: Measure > > +} INTEL_PCI_DIGEST_CAPABILITY_HEADER; > > + > > +#define INTEL_PCI_CAPID_DVSEC 0x23 > > +#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086 > > +#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E > > + > > +typedef union { > > + struct { > > + UINT8 DigestModified:1; // RW1C > > + UINT8 Reserved0:7; > > + } Bits; > > + UINT8 Data; > > +} INTEL_PCI_DIGEST_DATA_MODIFIED; > > + > > +#define INTEL_PCI_DIGEST_MODIFIED BIT0 > > + > > +typedef union { > > + struct { > > + UINT8 Digest0Valid:1; // RO > > + UINT8 Digest0Locked:1; // RO > > + UINT8 Digest1Valid:1; // RO > > + UINT8 Digest1Locked:1; // RO > > + UINT8 Reserved1:4; > > + } Bits; > > + UINT8 Data; > > +} INTEL_PCI_DIGEST_DATA_VALID; > > + > > +#define INTEL_PCI_DIGEST_0_VALID BIT0 > > +#define INTEL_PCI_DIGEST_0_LOCKED BIT1 > > +#define INTEL_PCI_DIGEST_1_VALID BIT2 > > +#define INTEL_PCI_DIGEST_1_LOCKED BIT3 > > + > > +typedef struct { > > + INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C > > + INTEL_PCI_DIGEST_DATA_VALID Valid; // RO > > + UINT16 TcgAlgId; // RO > > + UINT8 FirmwareID; // RO > > + UINT8 Reserved; > > +//UINT8 Digest[]; > > +} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE; > > + > > +#pragma pack() > > + > > +#endif > > + > > -- > > 2.19.2.windows.1