From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web09.1188.1583192744027349925 for ; Mon, 02 Mar 2020 15:45:44 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: jiewen.yao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Mar 2020 15:45:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,509,1574150400"; d="scan'208,217";a="232059337" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga007.fm.intel.com with ESMTP; 02 Mar 2020 15:45:43 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 2 Mar 2020 15:45:42 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.50]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.155]) with mapi id 14.03.0439.000; Tue, 3 Mar 2020 07:45:39 +0800 From: "Yao, Jiewen" To: "De Leon Vazquez, Lorena R" , "devel@edk2.groups.io" CC: "Kinney, Michael D" Subject: Re: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Thread-Topic: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Thread-Index: AdXw5cIqcI9g1CYLQByg/sbQxnIlIgABtlAQ Date: Mon, 2 Mar 2020 23:45:38 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F96301F@shsmsx102.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: jiewen.yao@intel.com Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_74D8A39837DF1E4DA445A8C0B3885C503F96301Fshsmsx102ccrcor_" --_000_74D8A39837DF1E4DA445A8C0B3885C503F96301Fshsmsx102ccrcor_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: jiewen.yao@intel.com From: De Leon Vazquez, Lorena R Sent: Tuesday, March 3, 2020 7:04 AM To: devel@edk2.groups.io Cc: Yao, Jiewen ; Kinney, Michael D Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Looks like Addresswidth is BIT wise values. Right now these values are not = used any Suggested-by: Star Zeng star.zeng@intel.com Signed-off-by: lorena.r.de.leon.vazquez@intel.com -- .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 11 ++++------- .../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 11 ++++------- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c index cc970c0..61fbb4a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c @@ -128,14 +128,11 @@ CreateContextEntry ( DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInform= ation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.= Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)= { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD= %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Roo= tEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transl= ationTableEx.c index 0da1611..6bd31b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= eEx.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= eEx.c @@ -78,14 +78,11 @@ CreateExtContextEntry ( DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInfor= mation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId= .Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ExtContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ExtContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)= { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD= %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ext= RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); -- 2.21.0.windows.1 --_000_74D8A39837DF1E4DA445A8C0B3885C503F96301Fshsmsx102ccrcor_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Reviewed-by: jiewen.yao@intel.com

 

From: De Leon Vazquez, Lorena R <lorena.r.= de.leon.vazquez@intel.com>
Sent: Tuesday, March 3, 2020 7:04 AM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Kinney, Michael D <= michael.d.kinney@intel.com>
Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug= fix

 

Looks like Addresswidth is BIT wise values. Right no= w these values are not used any

 

Suggested-by: Star= Zeng star.zeng@intel.com

Signed-off-by: lorena.r.de.leon.vazq= uez@intel.com

 

--

.../Feature/VTd/IntelVTdDxe/TranslationTable.c =        | 11 ++++-------<= /o:p>

.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c&nbs= p;     | 11 ++++-------

2 files changed, 8 insertions(+), 14 deletions(-= )

 

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/IntelVTdDxe/TranslationTable.c

index cc970c0..61fbb4a 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Inte= lVTdDxe/TranslationTable.c

+++ b/Silicon/Intel/IntelSiliconPkg/Feat= ure/VTd/IntelVTdDxe/TranslationTable.c

@@ -128,14 +128,11 @@ CreateContextEntry (<= /o:p>

 

     DEBUG ((DEBUG_INFO,&qu= ot;Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].S= egment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));<= o:p>

 

-    switch (mVtdUnitInformation[VtdI= ndex].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ContextEntry->Bit= s.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ContextEntry->Bit= s.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ERR= OR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", = VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addres= sWidth =3D 0x2;

   }

 

   FlushPageTableMemory (VtdIndex, (U= INTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(EntryT= ablePages));

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature= /VTd/IntelVTdDxe/TranslationTableEx.c

index 0da1611..6bd31b7 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Inte= lVTdDxe/TranslationTableEx.c

+++ b/Silicon/Intel/IntelSiliconPkg/Feat= ure/VTd/IntelVTdDxe/TranslationTableEx.c

@@ -78,14 +78,11 @@ CreateExtContextEntry (=

 

     DEBUG ((DEBUG_INFO,&qu= ot;DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].= Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));=

 

-    switch (mVtdUnitInformation[VtdI= ndex].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ExtContextEntry->= Bits.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ExtContextEntry->= Bits.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ERR= OR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n", = VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addres= sWidth =3D 0x2;

   }

 

   FlushPageTableMemory (VtdIndex, (U= INTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(Ent= ryTablePages));

--

2.21.0.windows.1

 

--_000_74D8A39837DF1E4DA445A8C0B3885C503F96301Fshsmsx102ccrcor_--